Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray .
Low-Cost Inter-Linked Subarrays (LISA):Enabling Fast Inter-Subarray Data Movement in DRAMKevin K. Chang† , Prashant J. Nair? , Donghyuk Lee† , Saugata Ghose† , Moinuddin K. Qureshi? , and Onur Mutlu††Carnegie Mellon University?Georgia Institute of Technologychannel (typically 64 bits wide). Then, the data is written backto memory, again one cache line at a time over the pin-limitedchannel, into the destination location. By going through theprocessor, this data movement incurs a significant penalty interms of latency and energy consumption.To address the inefficiencies of traversing the pin-limitedchannel, a number of mechanisms have been proposed to accelerate bulk data movement (e.g., [26, 45, 69, 83]). The state-ofthe-art mechanism, RowClone [69], performs data movementcompletely within a DRAM chip, avoiding costly data transfersover the pin-limited memory channel. However, its effectiveness is limited because RowClone can enable fast data movement only when the source and destination are within thesame DRAM subarray. A DRAM chip is divided into multiplebanks (typically 8), each of which is further split into many subarrays (16 to 64) [36], shown in Figure 1a, to ensure reasonableread and write latencies at high density [4, 22, 24, 36, 77]. Eachsubarray is a two-dimensional array with hundreds of rows ofDRAM cells, and contains only a few megabytes of data (e.g.,4MB in a rank of eight 1Gb DDR3 DRAM chips with 32 subarrays per bank). While two DRAM rows in the same subarrayare connected via a wide (e.g., 8K bits) bitline interface, rows indifferent subarrays are connected via only a narrow 64-bit databus within the DRAM chip (Figure 1a). Therefore, even forpreviously-proposed in-DRAM data movement mechanismssuch as RowClone [69], inter-subarray bulk data movementincurs long latency and high memory energy consumptioneven though data does not move out of the DRAM chip.ABSTRACTThis paper introduces a new DRAM design that enables fastand energy-efficient bulk data movement across subarrays in aDRAM chip. While bulk data movement is a key operation inmany applications and operating systems, contemporary systemsperform this movement inefficiently, by transferring data fromDRAM to the processor, and then back to DRAM, across a narrowoff-chip channel. The use of this narrow channel for bulk datamovement results in high latency and energy consumption. Priorwork proposed to avoid these high costs by exploiting the existingwide internal DRAM bandwidth for bulk data movement, butthe limited connectivity of wires within DRAM allows fast datamovement within only a single DRAM subarray. Each subarrayis only a few megabytes in size, greatly restricting the range overwhich fast bulk data movement can happen within DRAM.We propose a new DRAM substrate, Low-Cost Inter-LinkedSubarrays (LISA), whose goal is to enable fast and efficient datamovement across a large range of memory at low cost. LISA addslow-cost connections between adjacent subarrays. By using theseconnections to interconnect the existing internal wires (bitlines)of adjacent subarrays, LISA enables wide-bandwidth data transfer across multiple subarrays with little (only 0.8%) DRAM areaoverhead. As a DRAM substrate, LISA is versatile, enabling anarray of new applications. We describe and evaluate three suchapplications in detail: (1) fast inter-subarray bulk data copy,(2) in-DRAM caching using a DRAM architecture whose rowshave heterogeneous access latencies, and (3) accelerated bitlineprecharging by linking multiple precharge units together. Ourextensive evaluations show that each of LISA’s three applicationssignificantly improves performance and memory energy efficiency, and their combined benefit is higher than the benefit ofeach alone, on a variety of workloads and system configurations.CellSubarrayRow Buffer1. IntroductionInternalData Bus64bBulk data movement, the movement of thousands or millions of bytes between two memory locations, is a commonoperation performed by an increasing number of real-worldapplications (e.g., [28, 40, 56, 63, 67, 69, 71, 74, 83]). Therefore,it has been the target of several architectural optimizations(e.g., [1, 26, 69, 80, 83]). In fact, bulk data movement is important enough that modern commercial processors are addingspecialized support to improve its performance, such as theERMSB instruction recently added to the x86 ISA [17].In today’s systems, to perform a bulk data movement between two locations in memory, the data needs to go throughthe processor even though both the source and destination arewithin memory. To perform the movement, the data is firstread out one cache line at a time from the source location inmemory into the processor caches, over a pin-limited off-chip978-1-4673-9211-2/16/ 31.00 2016 IEEEIsolationTransistorBitlinesSlow(a) RowClone [69]8KbFast(b) LISAFigure 1: Transferring data between subarrays using the internal data bus takes a long time in state-of-the-art DRAMdesign, RowClone [69] (a). Our work, LISA, enables fast intersubarray data movement with a low-cost substrate (b).While it is clear that fast inter-subarray data movement canhave several applications that improve system performanceand memory energy efficiency [28, 56, 63, 67, 69, 83], there iscurrently no mechanism that performs such data movementquickly and efficiently. This is because no wide datapath exists today between subarrays within the same bank (i.e., theconnectivity of subarrays is low in modern DRAM). Our goalis to design a low-cost DRAM substrate that enables fast andenergy-efficient data movement across subarrays.1
We make two key observations that allow us to improve theconnectivity of subarrays within each bank in modern DRAM.First, accessing data in DRAM causes the transfer of an entirerow of DRAM cells to a buffer (i.e., the row buffer, where therow data temporarily resides while it is read or written) viathe subarray’s bitlines. Each bitline connects a column of cellsto the row buffer, interconnecting every row within the samesubarray (Figure 1a). Therefore, the bitlines essentially serveas a very wide bus that transfers a row’s worth of data (e.g.,8K bits) at once. Second, subarrays within the same bank areplaced in close proximity to each other. Thus, the bitlines of asubarray are very close to (but are not currently connected to)the bitlines of neighboring subarrays (as shown in Figure 1a).we propose a new DRAM design, VarIabLe LAtency (VILLA)DRAM, with asymmetric subarrays that reduce the accesslatency to hot rows by up to 63%, delivering high systemperformance and achieving both goals of low overhead andfast data movement (§5). Reducing precharge latency. Precharge is the process ofpreparing the subarray for the next memory access [22, 36,39, 40]. It incurs latency that is on the critical path of abank-conflict memory access. The precharge latency of asubarray is limited by the drive strength of the prechargeunit attached to its row buffer. We demonstrate that LISAenables a new mechanism, LInked Precharge (LIP), whichconnects a subarray’s precharge unit with the idle prechargeunits in the neighboring subarrays, thereby acceleratingprecharge and reducing its latency by 2.6x (§6).These three mechanisms are complementary to each other, andwe show that when combined, they provide additive systemperformance and energy efficiency improvements (§9.4). LISAis a versatile DRAM substrate, capable of supporting severalother applications beyond these three, such as performingefficient data remapping to avoid conflicts in systems thatsupport subarray-level parallelism [36], and improving theefficiency of bulk bitwise operations in DRAM [67] (see §10).This paper makes the following major contributions: We propose a new DRAM substrate, Low-cost Inter-linkedSubArrays (LISA), which provides high-bandwidth connectivity between subarrays within the same bank to supportbulk data movement at low latency, energy, and cost (§3). We propose and evaluate three new applications that takeadvantage of LISA: (1) Rapid Inter-Subarray Copy (RISC),which copies data across subarrays at low latency and lowDRAM energy; (2) Variable Latency (VILLA) DRAM, whichreduces the access latency of hot data by caching it in fastsubarrays; and (3) Linked Precharge (LIP), which reducesthe precharge latency for a subarray by linking its prechargeunits with neighboring idle precharge units. We extensively evaluate LISA’s applications individuallyand combined together. Our evaluation shows that (1) RISCimproves average system performance by 66% over workloads that perform intensive bulk data movement and(2) VILLA/LIP improve performance by 5%/8% over a widevariety of workloads. Combining all three applications improves system performance by 94% and reduces memoryenergy by 49% on a 4-core system running workloads withintensive bulk data movement (§9.4).Key Idea. Based on these two observations, we introduce a new DRAM substrate, called Low-cost Inter-linkedSubArrays (LISA). LISA enables low-latency, high-bandwidthinter-subarray connectivity by linking neighboring subarrays’bitlines together with isolation transistors, as illustrated in Figure 1b. We use the new inter-subarray connection in LISA todevelop a new DRAM operation, row buffer movement (RBM),which moves data that is latched in an activated row buffer inone subarray into an inactive row buffer in another subarray,without having to send data through the narrow internal databus in DRAM. RBM exploits the fact that the activated rowbuffer has enough drive strength to induce charge perturbation within the idle (i.e., precharged) bitlines of neighboringsubarrays, allowing the destination row buffer to sense andlatch this data when the isolation transistors are enabled.By using a rigorous DRAM circuit model that conforms tothe JEDEC standards [22] and ITRS specifications [18, 19], weshow that RBM performs inter-subarray data movement at 26xthe bandwidth of a modern 64-bit DDR4-2400 memory channel(500 GB/s vs. 19.2 GB/s; see §3.3), even after we conservativelyadd a large (60%) timing margin to account for process andtemperature variation.Applications of LISA. We exploit LISA’s fast inter-subarraymovement to enable many applications that can improve system performance and energy efficiency. We implement andevaluate the following three applications of LISA: Bulk data copying. Fast inter-subarray data movementcan eliminate long data movement latencies for copies between two locations in the same DRAM chip. Prior workshowed that such copy operations are widely used in today’soperating systems [56, 63] and datacenters [28]. We proposeRapid Inter-Subarray Copy (RISC), a new bulk data copyingmechanism based on LISA’s RBM operation, to reduce thelatency and DRAM energy of an inter-subarray copy by 9.2xand 48.1x, respectively, over the best previous mechanism,RowClone [69] (§4). Enabling access latency heterogeneity within DRAM.Prior works [40, 71] introduced non-uniform access latencies within DRAM, and harnessed this heterogeneity to provide a data caching mechanism within DRAM for hot (i.e.,frequently-accessed) pages. However, these works do notachieve either one of the following goals: (1) low area overhead, and (2) fast data movement from the slow portion ofDRAM to the fast portion. By exploiting the LISA substrate,2. Background: DRAM OrganizationA modern DRAM system consists of a hierarchy of components: channels, ranks, banks, and subarrays. A memory channel drives DRAM commands, addresses, and data between amemory controller and a group of DRAM ranks. Within a rank,there are multiple banks that can serve memory requests (i.e.,reads or writes) concurrently, independent of one another.11 Physically, a rank consists of multiple DRAM chips. Every chip in a rankoperates in lockstep to serve fragments of data for the same request. Manyprior works provide further details on DRAM rank organization [77, 82].2
to the bank I/O logic 5 , which sends the data out of the DRAMchip to the memory controller.While the row is activated, a consecutive column commandto the same row can access the data from the row buffer without performing an additional ACTIVATE. This is called a rowbuffer hit. In order to access a different row, a PRECHARGE command is required to reinitialize the bitlines’ values for anotherACTIVATE. This re-initialization process is completed by a set ofprecharge units 6 in the row buffer. For more detail on DRAMcommands and internal DRAM operation, we refer the readerto prior works [36, 39, 40, 44, 69, 71].2.1. DRAM SubarraysRow DecoderIn this work, we focus on operations across subarrays withinthe same bank. Typically, a bank is subdivided into multiplesubarrays [4, 36, 69, 79], as shown in Figure 2. Each subarrayconsists of a 2D-array of DRAM cells that are connected tosense amplifiers through bitlines. Because the size of a senseamplifier is more than 100x the size of a cell [40], modernDRAM designs fit in only enough sense amplifiers in a rowto sense half a row of cells. To sense the entire row of cells,each subarray has bitlines that connect to two rows of senseamplifiers — one above and one below the cell array ( 1 and2 in Figure 2, for Subarray 1). This DRAM design is known asthe open bitline architecture, and is commonly used to achievehigh-density DRAM [42, 75]. For the rest of the paper, we referto a single row of sense amplifiers, which holds the data fromhalf a row of activated cells, as a row buffer.Internal Bitline BitlineData 3Subarray 0Bus64b1SASASASASASASA.5Bank I/OWe propose a new DRAM substrate, LISA, which enablesfast and energy-efficient data movement across subarrayswithin a DRAM chip. First, we discuss the low-cost designchanges to DRAM to enable high-bandwidth connectivityacross neighboring subarrays (Section 3.1). We then introducea new DRAM command that uses this new connectivity toperform bulk data movement (Section 3.2). Finally, we conductcircuit-level studies to determine the latency of this command(Sections 3.3 and 3.4).WordlineSenseAmplifierSubarray 123. Low-Cost Inter-Linked Subarrays (LISA)3.1. LISA DesignPrechargeUnit 6SAGSA4GlobalSense AmplifiersBitlineLISA is built upon two key characteristics of DRAM. First,large data bandwidth within a subarray is already availablein today’s DRAM chips. A row activation transfers an entireDRAM row (e.g., 8KB across all chips in a rank) into the rowbuffer via the bitlines of the subarray. These bitlines essentially serve as a wide bus that transfers an entire row of data inparallel to the respective subarray’s row buffer. Second, everysubarray has its own set of bitlines, and subarrays within thesame bank are placed in close proximity to each other. Therefore, a subarray’s bitlines are very close to its neighboringsubarrays’ bitlines, although these bitlines are not directlyconnected together.2By leveraging these two characteristics, we propose to builda wide connection path between subarrays within the same bankat low cost, to overcome the problem of a narrow connectionpath between subarrays in commodity DRAM chips (i.e., theinternal data bus 3 in Figure 2). Figure 3 shows the subarraystructures in LISA. To form a new, low-cost inter-subarray datapath with the same wide bandwidth that already exists insidea subarray, we join neighboring subarrays’ bitlines togetherusing isolation transistors. We call each of these isolation transistors a link. A link connects the bitlines for the same columnof two adjacent subarrays.When the isolation transistor is turned on (i.e., the link isenabled), the bitlines of two adjacent subarrays are connected.Thus, the sense amplifier of a subarray that has already drivenits bitlines (due to an ACTIVATE) can also drive its neighboringsubarray’s precharged bitlines through the enabled link. Thiscauses the neighboring sense amplifiers to sense the chargedifference, and simultaneously help drive both sets of bitlines.When the isolation transistor is turned off (i.e., the link isBitlineFigure 2: Bank and subarray organization in a DRAM chip.2.2. DRAM Subarray OperationAccessing data in a subarray requires two steps. The DRAMrow (typically 8KB across a rank of eight x8 chips) must first beactivated. Only after activation completes, a column command(i.e., a READ/WRITE) can operate on a piece of data (typically 64Bacross a rank; the size of a single cache line) from that row.When an ACTIVATE command with a row address is issued,the data stored within a row in a subarray is read by two rowbuffers (i.e., the row buffer at the top of the subarray 1 andthe one at the bottom 2 ). First, a wordline correspondingto the row address is selected by the subarray’s row decoder.Then, the top row buffer and the bottom row buffer each sensethe charge stored in half of the row’s cells through the bitlines,and amplify the charge to full digital logic values (0 or 1) tolatch in the cells’ data.After an ACTIVATE finishes latching a row of cells into therow buffers, a READ or a WRITE can be issued. Because a typicalread/write memory request is made at the granularity of asingle cache line, only a subset of bits are selected from asubarray’s row buffer by the column decoder. On a READ, theselected column bits are sent to the global sense amplifiersthrough the internal data bus (also known as the global datalines) 3 , which has a narrow width of 64B across a rank ofeight chips. The global sense amplifiers 4 then drive the data2 Note that matching the bitline pitch across subarrays is important for ahigh-yield DRAM process [42, 75].3
Subarray 0BL BLActivatedsrcSubarray 2dstsrcVDD-VDDVDD/2-Precharged dst(VDD/2)0dstVDD/2 VDDŁFigure 3: Inter-linked subarrays in LISA.disabled), the neighboring subarrays are disconnected fromeach other and thus operate as in conventional DRAM.0srcLinkVDDBottom Row Buffer(dst)BL BL0 0Subarray 1B2 Double Amplification 3 Fully SensedBL BLTop Row Buffer(src)ACharge Sharing &1 Activated RBIsolationTransistor (Link)Figure 4: Row buffer movement process using LISA.in Figure 4), which connect the bitlines of dst to the bitlinesof dst2, in state 2 . By enabling RBM to perform row buffermovement across non-adjacent subarrays via a single command, instead of requiring multiple commands, the movementlatency and command bandwidth are reduced.3.2. Row Buffer Movement (RBM) Through LISANow that we have inserted physical links to provide highbandwidth connections across subarrays, we must providea way for the memory controller to make use of these newconnections. Therefore, we introduce a new DRAM command,RBM, which triggers an operation to move data from one rowbuffer (half a row of data) to another row buffer within thesame bank through these links. This operation serves as thebuilding block for our architectural optimizations.To help explain the RBM process between two row buffers,we assume that the top row buffer and the bottom row bufferin Figure 3 are the source (src) and destination (dst) of anexample RBM operation, respectively, and that src is activatedwith the content of a row from Subarray 0. To perform thisRBM, the memory controller enables the links ( A and B )between src and dst, thereby connecting the two row buffers’bitlines together (bitline of src to bitline of dst, and bitlineof src to bitline of dst).Figure 4 illustrates how RBM drives the data from src todst. For clarity, we show only one column from each rowbuffer. State 1 shows the initial values of the bitlines (BL andBL) attached to the row buffers — src is activated and hasfully driven its bitlines (indicated by thick bitlines), and dstis in the precharged state (thin bitlines indicating a voltagestate of VDD /2). In state 2 , the links between src and dstare turned on. The charge of the src bitline (BL) flows to theconnected bitline (BL) of dst, raising the voltage level of dst’sBL to VDD /2 . The other bitlines (BL) have the oppositecharge flow direction, where the charge flows from the BL ofdst to the BL of src. This phase of charge flowing betweenthe bitlines is known as charge sharing. It triggers dst’s rowbuffer to sense the increase of differential voltage betweenBL and BL, and amplify the voltage difference further. Asa result, both src and dst start driving the bitlines with thesame values. This double sense amplification process pushesboth sets of bitlines to reach the final fully sensed state ( 3 ),thus completing the RBM from src to dst.Extending this process, RBM can move data between tworow buffers that are not adjacent to each other as well. Forexample, RBM can move data from the src row buffer (in Figure 3) to a row buffer, dst2, that is two subarrays away (i.e.,the bottom row buffer of Subarray 2, not shown in Figure 3).This operation is similar to the movement shown in Figure 4,except that the RBM command turns on two extra links (Ł 23.3. Row Buffer Movement (RBM) LatencyTo validate the RBM process over LISA links and evaluateits latency, we build a model of LISA using the Spectre CircuitSimulator [2], with the NCSU FreePDK 45nm library [54]. Weconfigure the DRAM using the JEDEC DDR3-1600 timings [22],and attach each bitline to 512 DRAM cells [40, 71]. We conservatively perform our evaluations using worst-case cells, withthe resistance and capacitance parameters specified in theITRS reports [18, 19] for the metal lanes. Furthermore, weconservatively model the worst RC drop (and hence latency)by evaluating cells located at the edges of subarrays.We now analyze the process of using one RBM operation tomove data between two non-adjacent row buffers that are twosubarrays apart. To help the explanation, we use an examplethat performs RBM from RB0 to RB2, as shown on the left sideof Figure 5. The right side of the figure shows the voltageof a single bitline BL from each subarray during the RBMprocess over time. The voltage of the BL bitlines show thesame behavior, but have inverted values. We now explain thisRBM process step by step.BL BLRB0.BL (src)RB1Voltage (V)1.3RB2(dst)RBMRB0(src)RB1.BL1VDD1.1RB2.BL (dst)24ACTIVATERBM0.930.7 V /2DD0.505101520253035404550Time (ns)Figure 5: SPICE simulation results for transferring data acrosstwo subarrays with LISA.First, before the RBM command is issued, an ACTIVATE command is sent to RB0 at time 0. After roughly 21ns ( 1 ), thebitline reaches VDD , which indicates the cells have been fullyrestored (tRAS). Note that, in our simulation, restoration happens more quickly than the standard-specified tRAS value of35ns, as the standard includes a guardband on top of the typicalcell restoration time to account for process and temperature4
variation [3, 39]. This amount of margin is on par with valuesexperimentally observed in commodity DRAMs at 55 C [39].Second, at 35ns ( 2 ), the memory controller sends the RBMcommand to move data from RB0 to RB2. RBM simultaneouslyturns on the four links (circled on the left in Figure 5) thatconnect the subarrays’ bitlines.Third, after a small amount of time ( 3 ), the voltage ofRB0’s bitline drops to about 0.9V, as the fully-driven bitlinesof RB0 are now charge sharing with the precharged bitlinesattached to RB1 and RB2. This causes both RB1 and RB2 to sensethe charge difference and start amplifying the bitline values.Finally, after amplifying the bitlines for a few nanoseconds( 4 at 40ns), all three bitlines become fully driven with thevalue that is originally stored in RB0.We thus demonstrate that RBM moves data from one rowbuffer to a row buffer two subarrays away at very low latency.Our SPICE simulation shows that the RBM latency across twoLISA links is approximately 5ns ( 2 4 ). To be conservative, we do not allow data movement across more than twosubarrays with a single RBM command.34.1. Shortcomings of the State-of-the-Art3.4. Handling Process and Temperature VariationWeighted SpeedupOn top of using worst-case cells in our SPICE model, weadd in a latency guardband to the RBM latency to account forprocess and temperature variation, as DRAM manufacturerscommonly do [3, 39]. For instance, the ACTIVATE timing (tRCD)has been observed to have margins of 13.3% [3] and 17.3% [39]for different types of commodity DRAMs. To conservativelyaccount for process and temperature variation in LISA, we adda large timing margin, of 60%, to the RBM latency. Even then,RBM latency is 8ns and RBM provides a 500 GB/s data transferbandwidth across two subarrays that are one subarray apartfrom each other, which is 26x the bandwidth of a DDR4-2400DRAM channel (19.2 GB/s) [24].4. Application 1: Rapid Inter-Subarray BulkData Copying (LISA-RISC)Due to the narrow memory channel width, bulk copy operations used by applications and operating systems are performance limiters in today’s systems [26, 28, 69, 83]. Theseoperations are commonly performed due to the memcpy andmemmov. Recent work reported that these two operations consume 4-5% of all of Google’s datacenter cycles, making theman important target for lightweight hardware acceleration [28].As we show in Section 4.1, the state-of-the-art solution, RowClone [69], has poor performance for such operations whenthey are performed across subarrays in the same bank.Our goal is to provide an architectural mechanism to accelerate these inter-subarray copy operations in DRAM. Wepropose LISA-RISC, which uses the RBM operation in LISA toperform rapid data copying. We describe the high-level operation of LISA-RISC (Section 4.2), and then provide a detailedlook at the memory controller command sequence required toimplement LISA-RISC (Section 4.3).32-24.0%10GMeanQueueing Latency(cycles)Previously, we have described the state-of-the-art work,RowClone [69], which addresses the problem of costly datamovement over memory channels by coping data completelyin DRAM. However, RowClone does not provide fast data copybetween subarrays. The main latency benefit of RowClonecomes from intra-subarray copy (RC-IntraSA for short) as itcopies data at the row granularity. In contrast, inter-subarrayRowClone (RC-InterSA) requires transferring data at the cacheline granularity (64B) through the internal data bus in DRAM.Consequently, RC-InterSA incurs 16x longer latency than RCIntraSA. Furthermore, RC-InterSA is a long blocking operationthat prevents reading from or writing to the other banks inthe same rank, reducing bank-level parallelism [38, 53].To demonstrate the ineffectiveness of RC-InterSA, we compare it to today’s currently-used copy mechanism, memcpy,which moves data via the memory channel. In contrast toRC-InterSA, which copies data in DRAM, memcpy copies databy sequentially reading out source data from the memory andthen writing it to the destination data in the on-chip caches.Figure 6 compares the average system performance and queuing latency of RC-InterSA and memcpy, on a quad-core systemacross 50 workloads that contain bulk (8KB) data copies (seeSection 8 for our methodology). RC-InterSA actually degradessystem performance by 24% relative to memcpy, mainly because RC-InterSA increases the overall memory queuing latency by 2.88x, as it blocks other memory requests from beingserviced by the memory controller performing the RC-InterSAcopy. In contrast, memcpy is not a long or blocking DRAMcommand, but rather a long sequence of memory requeststhat can be interrupted by other critical memory requests,as the memory scheduler can issue memory requests out oforder [34, 35, 52, 53, 62, 73, 78, ure 6: Comparison of RowClone to memcpy over the memory channel, on workloads that perform bulk data copy acrosssubarrays on a 4-core system.On the other hand, RC-InterSA offers energy savings of5.1% on average over memcpy by not transferring the data overthe memory channel. Overall, these results show that neitherof the existing mechanisms (memcpy or RowClone) offers fastand energy-efficient bulk data copy across subarrays.4.2. In-DRAM Rapid Inter-Subarray Copy (RISC)Our goal is to design a new mechanism that enables lowlatency and energy-efficient memory copy between rows indifferent subarrays within the same bank. To this end, wepropose a new in-DRAM copy mechanism that uses LISA toexploit the high-bandwidth links between subarrays. The keyidea, step by step, is to: (1) activate a source row in a subarray;(2) rapidly transfer the data in the activated source row buffersto the destination subarray’s row buffers, through LISA’s wide3 In other words, RBM has two variants, one that moves data betweenimmediately adjacent subarrays (Figure 4) and one that moves data betweensubarrays that are one subarray apart from each other (Figure 5).5
inter-subarray links, without using the narrow internal databus; and (3) activate the destination row, which enables thecontents of the destination row buffers to be latched into thedestination row. We call this inter-subarray row-to-row copymechanism LISA-Rapid Inter-Subarray Copy (LISA-RISC).As LISA-RISC uses the full row bandwidth provided by LISA,it reduces the copy latency by 9.2x compared to RC-InterSA(see Section 4.5). An additional benefit of using LISA-RISC isthat its inter-subarray copy operations are performed completely inside a bank. As the internal DRAM data bus is untouched, other banks can concurrently serve memory requests,exploiting bank-level parallelism. This new mechanism is complementary to RowClone, which performs fast intra-subarraycopies. Together, our mechanism and RowClone can enablea complete set of fast in-DRAM copy techniques in futuresystems. We now explain the step-by-step operation of howLISA-RISC copies data across subarrays.Third, to move data from RB0 to RB2 to complete the copytransaction, we need to precharge both RB1 and RB2. Thechallenge here is to precharge all row buffers except RB0. Thiscannot be accomplished in today’s DRAM because a prechargeis applied at the bank level to all row buffers. Therefore, wepropose to add a new precharge-exception command, whichprevents a row buffer from being precharged and keeps itactivated. This bank-wide excepti
8Kb Fast Isolation Transistor (b) LISA Figure 1: Transferring data between subarrays using the in-ternal data bus takes a long time in state-of-the-art DRAM design, RowClone [69] (a). Our work, LISA, enables fast inter-subarray data movement with a low-cost substrate (b). While it is clear that fast inter-subarray data movement can
ABSTRACT The scanning performance of wide-angular scanning linear arrays is primarily degraded by the limited angular pro le of the employed elements' patterns. This paper introduces an innovative strategy for compensating this degradation by using subarrays. Our design uses a uniform linear array
EA 4-1 CHAPTER 4 JOB COSTING 4-1 Define cost pool, cost tracing, cost allocation, and cost-allocation base. Cost pool––a grouping of individual indirect cost items. Cost tracing––the assigning of direct costs to the chosen cost object. Cost allocation––the assigning of indirect costs to the chosen cost object. Cost-alloca
Cost Accounting 1.2 Objectives and Functions of Cost Accounting 1.3 Cost Accounting and Financial Accounting — Comparison 1.3 Application of Cost Accounting 1.5 Advantages of Cost Accounting 1.6 Limitations or Objections Against cost Accounting 1.7 Installation of a costing system 1.7 Concept of Cost 1.9 Cost Centre 1.10 Cost Unit 1.11 Cost .File Size: 1MB
Linked List Basics Linked lists and arrays are similar since they both store collections of data. The array's features all follow from its strategy of allocating the memory for all its elements in one block of memory. Linked lists use an entirely different strategy: linked lists allocate memory for each element
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Anatomy is largely taught in the early years of the curriculum, with 133 some curricula offering spiral learning into later years (Evans and Watt, 2005). This 134 spiral learning frequently includes anatomy relating to laparoscopic, endoscopic, and . 7 .
