Outline - Superaid7

3D Devices: Experiment & SimulationS. BARRAUD, CEA, LETI, Minatec Campus, Grenoble, FRANCEESSDERC/ ESSCIRC Workshop “Process Variations from EquipmentEffects to Circuit and Design Impacts”September 3, 2018, Dresden, GermanySlide 1SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenOutline Introduction and Motivation Performance and Design Consideration 3D Process Integration for Stacked-Wires FETs Electrical Characterization Conclusions and OutlookSlide 2SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden

Context of this work?Two main MOSFET architectures for advanced CMOS3D FinFET14nm SAMSUNG14nm INTEL10nm INTEL22nm INTELNew MOSFETarchitecturesneed to beproposed16nm TSMC22nm GFBBack-gatecontrol usingtthinh BOX capacitive28nm ST2D FDSOISlide 3SSingle-gateiÆ reductionoff SCE controlled byotthinnerhTSi or TBOXSUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenContext of this workRecent press releaseMay 2017Samsung set to lead the future of foundry with comprehensive process roadmap down to 4nm4LPP (4nm Low Power Plus): 4LPP will be the first implementation of next generation devicearchitecture – MBCFETTM structure (Multi Bridge Channel FET). MBCFETTM is Samsung’s uniqueGAAFET (Gate All Around FET) technology that uses a Nanosheet device to overcome thephysical scaling and performance limitations of the FinFET sive-process-roadmap-down-to-4nmJune 2017IBM claims 5nm Nanosheet breakthoughIBM researchers and their partners have developed a new transistor architecture based on StackedSilicon Nanosheets that they believe will make FinFETs obsolete at the 5nm nodehttp://www.eetimes.com/document.asp?doc id 1331850&GAA MOSFET devices are becoming an industrial realitySlide 4SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden

MotivationfootprintWFinFP14nm INTEL [1]WNW WFinIMEC [2]FPLETI [3][1] S. Natarajan et al., IEDM, 2014.[2] H. Mertens et al., VLSI Technology, 2016.[3] C. Dupré et al., IEDM, 2008.Hfin 45nm W 7nmLG 10nm4020Slide 5FinFET60DIBL (mV/V)footprint Wire FETs can be view as anevolutionary step from the FinFET Wire FETs share many of the sameprocess steps as the FinFET GAA FETs provides a betterelectrostatics than FinFETTCAD resultsGAA Wire FETsFin FETsGAA 7nm10152025303540Gate length (nm)SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenIntroduction – Goals and StrategyMain Objective of SUPERAID7Simulation of the impact of systematic and statistical process variations on devices,interconnects and circuits down to the 5nm nodeWP1ProjectmanagmentWP2: Specifications and benchmarksDefine specifications for two generations of devices (7nm Trigate and 5nmGAA Stacked-Wires FETs) – process-flow/morphological data/electrical data to provide input data for the calibration/validation of simulation tools to give a feedback to other WP after the comparison between simulationand experimentWP3: Variationaware equipmentand processsimulationWP4: Variationaware device andinterconnectsimulationWP5: Software integration and compact modelsDissemination (WP6) and exploitation (WP7)Slide 6SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden

Outline Introduction and Motivation Performance and Design Consideration 3D Process Integration for Stacked-Wires FETs Electrical Characterization Conclusions and OutlookSlide 7SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenPerformance and Design ConsiderationNanowire (NW)FinFET (FF)FFFP 25nmHFin 43nm HFinWFin 7nmHFinSNWFP 25nmTriple Stack (3S) H 43nmFin 3GAATS 8nmTSHNW 6.3nmWNW 7nmNanosheet (NS)Nanosheet (NS)HFinTSSNSHFin 43nmHNS 6.3nmWNS WNWTS 8nmDouble Stack (1S) 3GAASlide 8SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenHFinTSSingle Stack (2S) 3GAA

Effective width of FinFETFootprint ܫ ௌFPFootprintFootprint (nm)FPFootprintWFinFF120ଶܸ ௌܸ ௌ െʹW 7nmHFin 43nm8040TCAD0,2Slide 9ܸீௌ െ ܸ௧ FFWFinWFinܹ ൌ Ɋ ൈ ܥ ௫ ൈ ீܮ 0,40,60,8Weff (μm)FPS. Barraud et al., IEDM 2017SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenFinFET versus GAA NanowiresFootprint (nm) ܫ ௌ120ܹ ൌ Ɋ ൈ ܥ ௫ ൈ ீܮ NWNWFF-14%80ܸீௌ െ ܸ௧ FFଶܸ ௌܸ ௌ െʹW 7nmHFin 43nm?Improvement of Wefffor a constant surfaceoccupation40TCAD0,20,40,60,8Weff (μm)Slide 10SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenS. Barraud et al., IEDM 2017

GAA Nanowires versus GAA NanosheetsFootprint (nm) ܫ ௌܹ ൌ Ɋ ൈ ܥ ௫ ൈ ீܮ ܸீௌ െ ܸ௧ 42% WeffWNSNW 132nmNSFF 107nm120ଶܸ ௌܸ ௌ െʹ 24% Weff82nm8057nm40 3GAA32nm0,20,40,6 5% Weff0,8 5%Weff (μm)Slide 11SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenTradeoff between SCE and WeffLFFootprint 57nm6060DIBL (mV/V)FFFootprint 82nm50825719.5NS3240Footprint ,2LG 16nm:HII wP0,42030LG 16nmNW0,4:HII wP0,620NWLG 16nm0,40,6SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenFPLF:HII wPGAA stacked-nanosheets maximize Weff (i.e. drive current)per layout footprint with improved channel electrostatics.Slide 12WNW WFinWNSS. Barraud et al., IEDM 2017

Power/Performance OptimizationFP 25nm; 3 stacked GAA; LG 16nm; HNW 6.5nmLFLFNormalized IOFF100FP 25nm 3 W WFin10-2FP19.5nm13nmLF 57nmLF 82nmLF 107nmW 7nm0,557nm32nm1,01,5Normalized IONSlide 13SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenParasitic capacitances and delayA delay reduction of around 20% is expected for WNS 30nmNW ܥ Ǥ ܸௗௗɒൌܰ ݇ܿܽݐݏ Ǥ ܫ ܥ ൎ ʹǤ Ǥ ܥ ௗ Slide 14W: DelayIeff: Effective drive currentIeff (IH IL)/2IH IDS(VGS VDD, VDS VDD/2)IL IDS(VGS VDD/2, VDS VDD)Supply voltage VDD 0.7VFO 3LG 16nmSpacer size: 4.2nmEOT 0.67nmCback-end 2fFM 2: Miller effect in inverterߝௌ ைమ Ǥ ܮ Ǥ ݓ ܥ ି ௗ ൗͶ ǤǤ ݐ ௩ʹSUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden20LF 82nm (4 fins with FP 25nm)LF 57nm (3 fins with FP 0-40(W 7nm)-20Wp(%)020Wp(%)40

What have we learned? GAA NS structures could be used to maximize the effectivewidth which will improve the drive current without increasingpower density (lower DIBL than in short-channel FinFETdevices). A delay reduction of around 20% is expected for WNS 30nm Nanosheet transistors offer more freedom to designers for thepower-performance optimization thanks to a fine tuning of thedevice widthSlide 15SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenOutline Introduction and Motivation Performance and Design Consideration 3D Process Integration for Stacked-Wires FETs Electrical Characterization Conclusions and OutlookSlide 16SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden

Process Flow of GAA Stacked Wires * Blue module: specific technical requirementsfor stacked wires FETs (as compared to FinFETdevices)Slide 17SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenDevice Fabrication – (Si/SiGe) multilayerVertically Stacked GAA Si Nanosheet FETSOI substrateSiGe/Si epitaxyFin patterning (SIT process)Dumy gate deposition / CMPDummy gate patterningInner/Outer spacer formationnIn-situ doped (Si:P) source/drainILD deposition / CMPDummy gate removalRelease of Si NW (SiGe etching))Gate dielectric (HfO2 2nm)TiN depositionFill metal (W) deposition / CMPSelf-aligned contact (SAC) M1 BEOLS. Barraud et al., IEDM 2016Slide 18Epitaxial growth of (Si0.7Ge0.3/Si) multilayersSUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden

Device Fabrication – Fin patterningTEM images after etching of (Si/SiGe) fins. Two types of fins patterning were used:(Left) single-Fin process and (Right) dense arrays of fins with a SIT process. OurSIT-based patterning technique yields 40 nm-pitch fins which are 60 nm high and20 nm wide for both Si and SiGe channelsSlide 19SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenDevice Fabrication – Outer/Inner SpacerVertically Stacked GAA Si Nanosheet FET(a) Anisotropic etching of (Si0.7Ge0.3/Si) multilayers(b) Selective etching of Si0.7Ge0.350nmSlide 20SSUPERAID7Workshop “ProcessVariations from Equipment Effects toVCircuit and Design Impacts”September 3, 2018, Dresden(c) Deposition/etching of SiN

Device Fabrication – RMG moduleDummy-Gate removalHard mask removal(Si/SiGe) FinsDummy gateoxydeoxydePoly-SiActive can bevisualized bytransparency(b)(a)(Si/SiGe) FinsoxydeoxydePoly-SiSlide 21SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenVertically Stacked-Wires FETsNW/NS Cross-sectionNWNSAlong source-drain directionSiGeSi channelSi channelSiGeInner spacerLong-LG ( 300nm)Short-LG (20nm)After HfO2/TiN/W deposition (LG 200nm)Slide 22S. Barraud et al., IEDM 2016SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden

Simulation of Device Fabrication (WP3) LETI data (SEM, TEM, strainmapping, ) provided for thecalibration/validation of processsimulation Identification of relevantprocess parameter for variability Influence of process parameterson electrical performance of 3DdevicesFraunhofer IISBTU WienSynopsysSlide 23SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenStrain CharacterizationStrain engineering is another keyfactor for stacked-wires FETs.1.2.Strain maps were obtained by TEMusingPrecessionElectronDiffraction technique*3.4.Is initial strain(substrate-inducedstrain) can be used toboost performances?* M.P. Vigouroux et al., APL 105, 191906 (2014)* D. Cooper et al., Nano Lett. 15, 5289 (2015)Slide 24SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden

Strain CharacterizationDeformation maps acquired by PED after Si Source/DrainThe silicon channels aswell as the source anddrain are unstrainedÆ A deformation closeto 0% is observedDeformation maps acquired by PED after SiGe Source/DrainOptimized engineeringof process-inducedstress techniques canbe efficient in 3Dstacked-NWs devicesS. Barraud et al., IEDM 2016Slide 25SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, DresdenWhat have we learned? Horizontal GAA NW and NS also have the advantage of beingfabricated with minimal deviation from FinFET (FF) devices incontrast to vertical NWs which require more disruptivetechnological changes. The benefits of epitaxially regrown SiGe:B S/D junctions wasevidenced, with a significant compressive strain ( 1%) injected intop and bottom Si p-channels need to be extrapolated at 5nmdesign rules. Process Simulation well reproduces morphological characterization relevant process parameter can now be used for variabilitystudies.Slide 26SUPERAID7 Workshop “ProcessVariations from Equipment Effects toCircuit and Design Impacts”September 3, 2018, Dresden