Discussion 10 Sp2022 - Inst.eecs.berkeley.edu

EECS 151/251ASP2022 Discussion 10GSI: DIMA NIKIFOROV, YIKUAN CHEN

Agenda Latches Flip-Flops SRAMs

Latches3

Latch Timing A positive latch is transparent (q d) when the clock is high and opaque (q d, sampled atnegedge clock) when the clock is lowtd- q : delay from d to q when the latch is transparenttclk- q : delay from the rising clock edge to d propagating to qEECS 151/251A DISCUSSION 94

Latch Circuits‘Feedback-breaking’ latchTransparent high‘State-forcing’ latchTransparent lowSR latchCommon interview question5

Building a Flip-Flop from Latches Clock pulsed latch Latch becomes transparent for the pulseduration only, then holds dataNot common anymore, sometimes used in highperformance circuitsPositive hold timePair of latches – edge triggered (posedge clk!!!) Commonly used techniqueL2 holds output data stable when clock is high.Negative hold time6

Flip-Flops7

Hold, Setup, clk- q Time Hold time: data must be stable after the clock edge Violations are FATAL! (why?)Can be negative! (how?) This is a negative edgeflip-flop as drawnWe’ll consider the positiveedge case Setup time: data must be stable before the clockedge Violations can be avoided (how?) Clk-to-q time: delay from a clock edge to q d EECS 151/251A DISCUSSION 9Essentially the delay of 1 latch8

Path Timing Constraints Setup constraint: Tclk tclk- q tlogic,max tsetup The clock period must be greater than the delay of the critical pathHold constraint: thold tclk- q tlogic,min The minimum logic delay must be greater than the hold timeEECS 151/251A DISCUSSION 99

False Paths Be careful about finding the critical path by statically adding up delaysSome paths may not be exercised based on logic expressionsHere, the critical path is not 400ns. What is it?a200 ns200 nsb100 ns0011c100 nssEECS 151/251A DISCUSSION 910

Clock Skew Skew: the deterministic clock arrival time differencebetween 2 flops 2 flops referred to as launching & receiving Positive clock to receiving arrives later than to launchingNegative clock to receiving arrives earlier than tolaunchingNew timing equations: Setup: Tclk tclk- q tlogic,max tsetup - tskew Positive skew can improve clock frequencyNegative skew hurts setup marginHold: thold tskew tclk- q tlogic,min EECS 151/251A DISCUSSION 9Skew effect is opposite from setup11

Clock Jitter Jitter is the non-deterministic difference in clock arrival times Types: period & cycle-to-cycleCan be treated like skew in timing calculationsAssume worst case jitter in the unfavorable direction for timing calculationLump jitter of both the launching and receiving FFs into an equivalent skew“Dual-dirac”model (source)12

SRAMs13

SRAM Structure:14

SRAM Structure:15

SRAM: Basic Static Memory Component:16

SRAM: How to Write? Challenge: How do you overpower thefeedback loop?Challenge: Writing 0 vs writing 1?17

SRAM: How to Write? Challenge: How do you overpower thefeedback loop?Challenge: Writing 0 vs writing 1?18

6T SRAM Cell19

6T SRAM Operation20

6T SRAM Cell Sizing Read Sizing: Write Sizing:21

Dual Port SRAM Modifications: 1 Read 1 Write What additional logic is needed?22

Questions?23

11 Clock Skew Skew: the deterministic clock arrival time difference between 2 flops 2 flops referred to as launching & receiving Positive clock to receiving arrives later than to launching Negative clock to receiving arrives earlier than to launching New timing equations: Setup: T clk t clk- q t logic,max t setup - t skew Positive skew can improve clock frequency