A Full-Chip ESD Protection Circuit Simulation And Fast Dynamic Checking .
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2818707, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) 1A Full-Chip ESD Protection Circuit Simulationand Fast Dynamic Checking Method UsingSPICE and ESD Behavior ModelsFeilong Zhang, Chenkun Wang, Fei Lu, Qi Chen, Cheng Li, X. Shawn Wang, Daguang Li and AlbertWang, Fellow, IEEE Abstract— Full-chip electrostatic discharge (ESD) protectioncircuit design verification is needed for complex ICs at advancedtechnology nodes, which however is still largely impractical due tothe limitation of ESD device models and CAD tools. This paperreports a new circuit-level ESD protection design simulation anddynamic checking method using SPICE and ESD device behaviormodels, which allows comprehensive, quantitative and dynamicverification of ESD protection circuit designs at chip level basedentirely on ESD discharging functions. The new ESD protectioncircuit simulation method is validated using ICs designed andfabricated in a 28nm CMOS. This ESD-function-based ESDcircuit simulation method is technology independent, which canhandle various ICs including complex multiple power domaincircuits and ICs using non-traditional ESD protection structures.Index Terms— ESD design method, circuit-level ESDsimulation, behavior model, SPICE, I/O, RF switch.I. INTRODUCTIONAsemiconductor technologies rapidly advance into nanonodes and FinFET technology domains, meanwhile ICchip complexity continuously increases, on-chip ESDprotection design becomes extremely challenging. Circuitsimulation can be conducted for simple timing analysis, whichhowever cannot simulate ESD protection functions for most ICsthat typically uses ESD protection structures featuring complexsnapback I-V behaviors. Due to lack of accurate ESD devicemodels and suitable full-chip ESD simulation CAD tools thatcan fully address the complex electro-thermal-process-devicecircuit-layout coupling effects associated with ESD dischargingbehaviors, chip-scale ESD protection circuit design verificationis still impractical for real world designs [1-8]. Over years,tremendous research efforts have been given to develop variousESD modeling and simulation techniques. TCAD-based mixedmode ESD simulation-design method was reported to simulatesmall I/O blocks (circuit simulation) with ESD protectionstructures (numerical simulation) that do not require physicsbased compact models for ESD devices [9, 10], which ishowever limited by the availability of process technologySManuscript received on August 30, 2017, revised on November 1, 2017 andJanuary 21, 2018, and accepted on March 3, 2018.Zhang, C. Wang, Chen, C. Li and A. Wang are with the Department ofElectrical and Computer Engineering, University of California, Riverside, CAinformation and impractical to handle large circuits due to itsnumerical simulation nature. Physics-equation-based ESDdevice compact models were reported for ESD simulation [1114], which however require full understanding of ESD devicephysics, often impossible, and extraction of too many deviceparameters. This makes using compact ESD device models verychallenging and largely impractical for fabless designs thatcannot ensure the model accuracy for arbitrary ESD devices andhandle other simulation challenges, such as the convergenceproblem often seen in practical ESD circuit simulation [11, 15].A new technology-independent ESD CAD tool was reported forwhole-chip ESD protection circuit design verification [16, 17].[16] discusses a novel CAD algorithm, featuring subgraphisomorphism and decomposition techniques, to extract arbitraryESD structures and ESD-critical parameters of the extractedESD devices. [17] presents a CAD flow that can generate anESD netlist directly from an IC layout data file and thenperform ESD-function-based design verification at chip level.While the ultimate goal was to allow ESD-function-based fullchip ESD protection circuit design verification, this ESD CADmethod requires IC layout data and technology data, which maynot be available to IC designers in fabless design houses [16,17]. Alternative circuit and layout level ESD simulationtechniques were also reported [18-22]. For example, [18]reports a chip-level dynamic ESD simulation technique.However, this simulation flow heavily relies on a numericalCAD method for substrate analysis, as well as technology andlayout data, which are impractical for ordinary circuitdesigners. [19] describes using ESD sub-circuit models for ESDsimulation by SPICE where ESD device models for simplediode and NMOS/PMOS ESD devices were discussed andvalidation using simple Zener ESD diodes and an RC-MOSpower clamp was reported. This is a typical ESD simulationflow that has limited value in real-world ESD circuit simulationbecause of its limitation in availability, accuracy and scalabilityof ESD device models for arbitrary ESD structures due to thecomplexity of ESD discharging behaviors, such as high currentand over-heating phenomena, layout irregularity and transientdV/dt effect. For example, the transient overshoot effect oftenobserved in various ESD structures are very difficult to model92507 USA (e-mail: aw@ece.ucr.edu, fzhan008@ucr.edu). Lu is with MarvellTechnology, Santa Clara, CA, USA, X. S. Wang is with UCLA, D. Li is withTrustChip Technology, Inc., China.0278-0070 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2818707, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) 2Circuit and ESD design SpecsESD structure designComprehensive TLP testing and extract ESD-criticalbehavior parametersincluding triggering (Vt1, It1), holding (Vh, Ih), ESD dischargingresistance (RON) and ESD thermal failure threshold (Vt2, It2)Partition TLP I-V curvesinto piece-wisefunctional statesCharacterize devicebehavior under ESDstress in different statesValidate ESD model bySPICE simulationESD device fabricationExtractionCore IC design ation)Transient ESD testing(TLP, VFTLP & zapping)BeginIf(device state off) thenVoltage Function off(Current)Else(device state trigger on)Voltage Function on(Current)Else(device state snapback)Voltage Function sb(Current)Extract ESD-critical parameters(Vt1, It1, Vh, Ih, RON, Vt2, It2)Build ESD behavior modelsESD device librarySmooth state changeESD zapperBuild Core ESD IC chip(add ESD bus-R)Build and validateBehavior modelSet chip-level ESD zapping routines & ESD failure criterion(IMAX for each path, VMAX for each node)Build ESD device and model libraryFull-chip ESD zapping simulation and analysis(HBM, CDM, etc.)FailFull-chip ESD simulation report(Pass/Fail?)PassIC tapeout & fabricationst(1 -Si success)Fig. 1. A flow chart for the new full-chip circuit-level ESD protection circuit simulation and analysis method.[20]. [21] depicts an integrated ESD checking flow focusing onDRC, topology and interconnect checking, which is a layoutcentric static checking technique that cannot be used fortransient ESD-function-based design verification. [22] presentsa full-chip ESD simulation method, however, it can only checknode voltage failures, ignored ESD current failures, and wasonly validated using simple ESD diodes. In summary, thereported ESD CAD methods still cannot allow ordinary ICdesigners to conduct quick transient and quantitative ESDcircuit simulation without been limited by the availability oftechnology and layout data, and complexity, accuracy andscalability of physics-based ESD device compact models. Inreal-world IC designs, there is a strong and urgent demand fora practical circuit-level transient ESD simulation and quickdynamic ESD pass/fail checking technique, which shall allowordinary IC designers to conduct comprehensive, quantitativeand efficient full-chip ESD protection circuit simulation anddesign verification that is entirely based on ESD dischargingfunctions. To address this need and based on a simple case study[23], this paper provides a comprehensive discussion of a newschematic-level ESD simulation and dynamic ESD checkingmethod using SPICE and accurate ESD device behaviormodels, which was developed to enable ordinary IC designersto quickly and quantitatively verify ESD protection circuitdesigns at full chip level. This paper is organized as following:After the Introduction, Section II describes the general flow ofthe new circuit-level ESD protection design simulation method.Section III presents several practical design examples in 28nmCMOS and 45nm SOI to validate this new ESD simulationtechnique, followed by the Conclusion.II. CIRCUIT-LEVEL ESD PROTECTION SIMULATIONCircuit designers rely on CAD tools, e.g., SPICE, to designICs following a common flow: schematic, pre-simulation,layout, post-simulation, verification, extraction, postsimulation and tape-out. The goal of this new circuit-level ESDprotection circuit design method is to provide a SPICE-basedcircuit design flow allowing ordinary IC designers to conductESD-function-based full-chip ESD protection designsimulation and analysis to verify ESD protection performanceat full chip level before tape-out. Fig. 1 depicts the design flowof the new ESD circuit simulation method. The design flowstarts from defining the specs for both core circuit and ESDprotection of an IC chip. Typically, for a given IC technology,ESD structures will be designed and optimized, which will befabricated and tested [4-10]. Comprehensive transient ESDcharacterization include transmission line pulse (TLP) forhuman body model (HBM), very-fast TLP (VFTLP) forcharged device model (CDM) and ESD zapping test.0278-0070 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2818707, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) TLP/VFTLP testing reveals all ESD-critical parameters, e.g.,ESD triggering voltage (Vt1) and current (It1), holding voltage(Vh) and current (Ih), discharging resistance (RON), and failurevoltage (Vt2) and current (It2) [1, 2], which define the ESDDesign Window on a chip. Numerical characterization of anESD protection structure or sub-circuit at chip level is requiredto accommodate the ESD Design Window Shrinking Effect foradvanced IC technologies [24]. The transient discharging I-Vcharacteristics for the ESD structures will be studied to extractthe corresponding ESD device behavior models, with the briefmodeling flow depicted in Fig. 1 [25, 26]. The advantage ofESD behavior modeling is that it circumvents the technicalbarrier of no good compact ESD device models for ESD circuitsimulation. An ESD library will be built up consisting of theverified ESD protection structures and their behavior modelsfor a given IC technology. This task is handled by either the ICfoundries or the design service team in a fabless design house.Since the ESD behavior models are extracted from themeasured ESD I-V curves, they are very accurate. An ICdesigner can go through the normal IC design flow to completedesign of the IC core circuit. In the next step, the IC designerwill select suitable ESD devices from the ESD library andintegrated the selected ESD devices into the IC core to completethe whole IC chip (ESD core circuit). It follows that the fullchip (ESD core) can be simulated using SPICE to study theESD protection functions at circuit level. Since ESD current istypical very large, the metal bus resistance in an ESDdischarging path may play a significant role in full-chip ESDprotection design. Hence, the ESD interconnect resistance (busR) should be extracted and included in the chip-level ESDcircuit simulation. At this point, circuit level ESD protectionsimulation can be conducted using SPICE similar to normal ICsimulation except for: 1) using an ESD pulse as the stimulus, 2)following chip-level ESD zapping routines, and 3) analyzingESD protection performance per ESD failure criteria. First, it isobvious that, for ESD circuit simulation, the input signals mustbe transient ESD pulses, i.e., the ESD pulse waveforms definedin ESD testing standards for HBM, CDM, MM, IEC or anyother ESD testing models. The ESD stimuli can also be TLP orVFTLP waveforms. Second, unlike typical IC simulation usinga small sinusoidal signal, chip-level ESD simulation routinesare very complicated and time-consuming according to theindustrial standard ESD zapping test procedures. Briefly, eachpad (I/O, control and supply) must be zapped by a set of ESDpulses with respect to a reference pad, while all other pads on achip have to be handled per an ESD testing standard selected,e.g., all open or all grounded. Meanwhile, each pad must bezapped against a positive supply pad (VDD) and a negativesupply pad (VSS) positively (PD and PS modes) and negatively(ND and NS modes). Each supply pad (VDD) must also bezapped against another supply pad (VSS) positively (DS mode)and negatively (SD mode). Further, each pad must be zappedseveral times for each zapping mode, typically three times.Therefore, full-chip ESD zapping test is extremely tedious,time-consuming and costly, which makes the new chip-levelESD circuit simulation method even more desirable andvaluable. Accordingly, a proper full-chip ESD zapping routinemust be defined and programmed for ESD circuit simulation.Third, full-chip ESD simulation analysis is much morecomplicated than typical SPICE circuit simulation. According3VDDAACBDESD pulse generatorRbus1R4Rc2PU-ESDTriR1INXMP1BActive RCpower clampMN1IsourceR2PD-ESDMN2Rbus2R3FGEGNDFig. 2. Simplified functional diagram for the input buffer IC with fullESD protection for chip-level ESD protection circuit simulation. Thekey ESD metal resistances were extracted from its layout below.Fig. 3. Layout of the ESD-protected input buffer IC where key ESDmetal resistances are extracted for full-chip ESD circuit simulation.Fig. 4. Simplified cross-sections for the STI ESD diodes in this work:(a) N /P-well PD-ESD diode and (b) P /N-well PU-ESD diode.0278-0070 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2818707, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) 4structure. If IESD IMAX holds for all ESD discharging paths, thenthe chip passes the ESD testing; otherwise, it fails the ESDtesting. In practice, a safety margin (10% 20%) needs to bedefined for an IC. The results for the whole-chip ESD circuitsimulation should be analyzed carefully. If an ESD failureoccurs, the IC designer will go back to check and revise theESD protection designs, for example, using an ESD devicefeaturing suitable Vt1, RON or It2. If the chip passes thecomprehensive circuit-level ESD simulation, one can proceedto tape-out the design for fabrication and expect first-Si ESDdesign success. This new chip-level ESD protection circuitsimulation and analysis method were validated by several ICsfabricated in foundry IC technologies as discussed below.III. DESIGN VALIDATION AND DISCUSSIONSThe new circuit-level ESD simulation method was verifiedusing several ICs designed and fabricated in foundry 28nmCMOS and 45nm SOI technologies.A. Input Buffer with Full ESD ProtectionThe first example is an input buffer circuit with full ESDprotection designed in a foundry 28nm CMOS. Fig. 2 shows theblock diagram for the IC featuring ESD protection at the inputand between the power supply buses with its layout shown inFig. 3. The targeted ESD protection is 2KV per HBM model.The 28nm CMOS features VDD 0.9V and typical breakdown ofBVGS 8.52V and BVDS 7.01V, which defines the ESD DesignWindow. The input ESD protection utilizes an N /P-well diodefor power-down ESD protection (PD-ESD) against GND and aP /N-well diode for power-up ESD protection (PU-ESD)against VDD. Both ESD didoes, shown in Fig. 4, feature shallowtrench isolation (STI) to minimize the parasitic capacitance forhigh-speed ICs. An active RC power clamp is used to protectthe power rail. As part of the whole project, these ESDprotection structures were first designed and fabricated, whichwere then characterized by TLP testing that delivers thetransient ESD discharging I-V curves and their ESD-criticalparameters, including the critical Vt1, Vh, RON and It2. Fig. 5Fig. 5. Transient ESD I-V curves measured by TLP for, (a) N /P-welldiode (forward ESD mode), (b) P /N-well diode (forward ESD mode) and(c) P /N-well diode (reverse ESD mode), match well with SPICEsimulation using the extracted ESD behavior models accordingly.to the ESD-critical parameters and the ESD Design Window,chip-level ESD simulation must be analyzed for at least twoESD failure criteria: Criterion-1 is the maximum allowedvoltage (VMAX) at the protected nodes, typically defined by thebreakdown voltage (BV) the nodes, against the simulated ESDclamping voltage (VESD) at the same nodes. If VESD VMAX holdsfor all pads, then the chip passes the ESD testing; otherwise,ESD failure will occur. Criterion-2 is the maximum sustainablecurrent (IMAX) for each ESD discharging path against thesimulated maximum ESD charging current (IESD) in the samepath. Typically, IMAX is same as the It2 of the ESD protectionFig. 6. Transient ESD I-V curves by TLP testing for an example MX metalstack (M3-M7) used for ESD interconnects in this work.0278-0070 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2818707, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) Fig. 7. Simulated transient node voltages for the ESD-protected inputbuffer IC using the new ESD simulation method under an ND mode 2KVHBM ESD zapping to the input pad (B) against VDD (A). Note that allvoltages are referred to node-B.Fig. 8. Simulated branch currents (Left axis) and core circuit transistorvoltages (Right axis) under the ND mode ESD zapping from Input pad (B)to VDD (A).presents the measured ESD discharging I-V curves for the ESDdiodes that were used to extract the ESD device behaviormodels, which are saved in the ESD library for circuit-levelESD simulation. The TLP measurement shows that the ESDthermal failure currents are about It2 1.8A (i.e., HBM 2.7KV)for the PD-ESD diode and It2 2.3A (i.e., HBM 3.5KV) for thePU-ESD diode, respectively. The reverse ESD triggeringvoltage for the PU-ESD diode is about Vt1 -7.98V per TLPtesting. Accuracy of the extracted ESD behavior models iscritical for circuit simulation, which was confirmed by SPICEsimulation for the ESD diodes using the corresponding ESDbehavior models as depicted in Fig. 5. Due to large ESDcurrents, full-chip ESD circuit simulation must include keyESD metal interconnect resistances, which depends entirely onthe IC layout. For this purpose, the metal interconnects for ESDconnections are characterized first by TLP for the metalinterconnects in the back-end-of-line (BEOL) of the 28nmCMOS. Fig. 6 depicts the transient I-V characteristics for onesample metal stack, the MX (M2-M5), by TLP testing. The5TLP-measured sheet-resistance is around R 1Ω/ for MXstack and R 0.3Ω/ for the My stack (M8-M10), both usedfor ESD interconnects in this design. According to the layout(Fig. 3), the extracted ESD metal resistances are: Rbus1 1.5Ωbetween VDD and power clamp anode (using M10, L 183 mand W 36 m), Rbus2 0.3Ω from the power clamp cathode toGND, R1 1Ω between Input pad and cathode of PU-ESD,R2 1Ω between Input and PD-ESD anode, R3 1.15Ω from PDESD cathode to GND and R4 0.6Ω from VDD to PU-ESDanode. These key ESD metal bus resistors are included inschematic test bench as shown in Fig. 2. It is worth noting that,with the focus on ESD circuit simulation flow, we chose to usea simplified linear-fitting approach in estimating metalresistance. A more involving piece-wise linear curve fittingapproach may be used to extract more accurate behavior modelsfor ESD metal interconnects.Comprehensive full-chip ESD circuit simulation using thenew method was conducted for the ESD-protected input bufferIC to study its compliance against the ESD Design Window.The input stimuli for ESD simulation are 2KV HBM ESDpulses with the required ESD zapping routines and polarities asdiscussed previously. The simulated node voltages and branchcurrents under ESD stressing are carefully examined for the IC.Take one ESD zapping case as an example, which applies anegative HBM ESD pulse to the Input pad with respect to V DD(i.e., ND ESD mode where the ESD pulse occurs to node B,while node A is grounded). Fig. 7 depicts the circuit nodetransient voltages under ESD zapping. Fig. 8 presents the ESDdischarging currents and transient voltage for the core circuittransistors by ESD simulation. Per design, the intended mainESD discharging path would be the route-ADEFGB (Red line,conduction through the active ESD power clamp and PD-ESDdiode in forward mode) that is confirmed by ESD circuitsimulation (Figs. 2&8). Fig. 7 clearly shows that VDE 2.5V forthe power clamp, the voltage across the PD-ESD diode remainssmaller than 2.7V, and the voltage from VDD to GND across thecore circuit (VDF) is less than breakdown of BVDS 7.01V ofthe core circuit transistor, which confirms a successful designof the PD-ESD diode and the ESD power clamp. However,Fig. 9. An EMMI image under HBM zapping reveals a hot spot at the PUESD diode, indicating an ESD weak point in the design.0278-0070 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2818707, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) ESDoutOutputI/ODTSCRPowerclampNM2D3D4VSSFig. 10. A functional schematic for the ESD-protected PRBS IC wheregated ESD diodes (D1-D8) protect I/O pins and the power clamp is aDTSCR.ESD simulation also found a transient current of around 40mAin the route-ACB (Marked in Blue, conduction via PU-ESDdiode in reverse mode, Figs. 2&8), which is because the voltageat Node-C exceeds the reverse BV (7.98V) of the PU-ESDdiode (Fig. 7, i.e., the reverse ESD triggering voltage Vt1)during the ESD stressing period. Fig. 8 also confirms thatVDS BVDS 7.01V for MP1 and VGS BVGS 8.52V for MN1 ofthe core circuit during the ESD stressing. This analysis suggeststhat the ESD design works for 2KV HBM zapping, though thePU-ESD diode (reverse mode) seems to be a weak point. This6analysis was confirmed by the Emission microscopy (EMMI)image shown in Fig. 9 where a hot spot was observed at the PUESD diode location under HBM zapping. More analysisindicates that this issue may be associated with the higher-thanexpected ESD metal resistance that led to a total voltage dropreaching to 4V, which may be revised by re-designing the ESDmetal to reduce the total ESD discharging RON. In summary,this example validated the new chip-level ESD circuitsimulation and analysis method and reveals its value of helpingIC designers to analyze full-chip ESD design, to pin-down ESDdesign weak points and to optimize ESD protection design fora whole chip.B. Large IC with Snapback DTSCR ESD ProtectionThe second example is a ESD-protected 7-bit pseudorandombinary sequence (PRBS) generator circuit, including D flip-flopand XOR gate, designed and fabricated in another foundry28nm CMOS with BVDS 5.6V and BVGS 5.2V. The purpose isto validate the new ESD circuit simulation method using alarge-scale IC with ESD protection featuring snapback I-Vbehavior that cannot normally be handled by SPICE simulation.Fig. 10 shows the IC schematic where I/O ESD protectiondevices are diodes and the power clamp is a diode-triggeredsilicon-controlled rectifier (DTSCR) ESD structure. An tNM2D3D8D4DTSCRPowerclampVSS(a)ABESD pulse generatorAD5D6InputI/OBFig. 11. ESD I-V curves by TLP testing (Red dots) agree well with SPICEsimulation (Black line) using the extracted ESD behavior models for: (a)gated diode and (b) TSCRPowerclampVSS(b)Fig. 12. Two exemplary full-chip ESD simulation cases: (a) positive Inputto-VSS HBM zapping, and (b) positive VDD-to-VSS zapping. The arrowedlines indicate the possible ESD discharging paths with the thicknesssuggesting the amount of ESD discharging current.0278-0070 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2818707, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) ESD protection structure is normally very ESD robust becauseof its snapback I-V behavior, low Vh, very high It12 and verylow RON. Unfortunately, the Vt1 of SCR is too high for advancedCMOS. DTSCR utilizes diodes to trigger the SCR, henceachieves very low Vt1. Following the new ESD circuitsimulation method, the diode and DTSCR ESD structures weredesigned, fabricated and characterized by TLP with the ESD IV curves shown in Fig. 11. TLP testing found a very low Vt1 3.19V for DTSCR, good for 28nm CMOS ICs, and Vt1 1.03Vat 10mA for the gated diodes, also suitable for I/O ESDprotection in forward mode since VDD 0.9V in this 28nmCMOS. ESD behavior models were then extracted for the diode7and DTSCR ESD devices, which were verified by SPICEsimulation as shown in Fig. 11.Comprehensive circuit-level ESD simulation was thenconducted for the full chip by the new method using HBM ESDpulses as stimuli. Fig. 12 shows two exemplary ESD circuitsimulation cases. First, Fig. 12a presents a positive Input-to-VSSzapping case (PS mode) where D8 is the intended ESDdischarging path. In addition, two possible unintentional ESDFig. 14. A non-traditional above-Si gNEMS ESD protection structure: (a)gNEMS cross-section and ESD circuit scenario, and (b) ESD dischargingI-V curves by TLP testing and SPICE simulation using its behavior devicemodel match each other well. TLP testing shows Vt1 10V and It2 8.4mAfor the gNEMS ESD device.SPDT RF switchAntennaseries stack BOutput2(band 25 Rx)shunt stack Ashunt stack CControllerFig. 13. Simulated transient ESD discharging behaviors for two ESDzapping cases of Fig. 12: (a) Input-to-VSS, and (b) VDD-to-VSS.series stack DOutput1(band 4 Rx)GrapheneESDprotectionFig. 15. A functional schematic of SPDT RF antenna switch circuit madein 45nm SOI CMOS with a gNEMS ESD protection fabricated by postCMOS processing.0278-0070 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2818707, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) Fig. 16. (a) Simulated ESD current distribution for the SPDT circuit withgNMES ESD protection at the output pin. (b) Simulated output voltage forthe ESD-protected SPDT circuit peaks at above 30V due to poor R ON ofgNMES ESD device.discharging paths, D5 DTSCR and D5 D2 D4, may existduring HBM zapping. Fig. 13a depicts the simulated ESDdischarging currents for each path, which readily shows thatalmost all ESD surge is discharged through input ESD diode(D8) in forward mode as designed, while negligible current seenin any unwanted path. Fig. 12
the limitation of ESD device models and CAD tools. This paper reports a new circuit-level ESD protection design simulation and dynamic checking method using SPICE and ESD device behavior models, which allows comprehensive, quantitative and dynamic verification of ESD protection circuit designs at chip level based
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