Silicon Technology Development Process Integration - PhoxTrot
Addressing future trends in integrated silicon photonics Charles Baudot Silicon Technology Development – Process Integration STMicroelectronics (Crolles 2) SAS - France
Outline Presentation Introduction Silicon Photonics Trends R&D Programs Conclusion Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 2
Silicon Photonics: Rationale What’s the big idea about silicon photonics? What: Why: Cost of production Power consumption efficiency System footprint Alternative market not fully addressed by III-V discrete photonics New markets out of data-communication Opportunities: Integrated photonic circuits on silicon using CMOS foundry facilities Knowhow Throughput Robustness Reliability Among the more explored & mastered areas of science Large volume manufacturability Resist to a wide variety of perturbations Long lifecycle when operated within specifications Constraints: Process flow Fabrication flow must be compatible with existing technologies Contamination Strict regulations about: material contamination, health hazards, safety hazards Some materials not allowed (III-V, Fe, ) Some materials in restricted zones (FEOL / BEOL : Cu, Au, ) Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 3
Optical Communication Trend Fiber optics data communication evolution Optical link network keeps on getting denser. So far, the market still addresses the professional market. Projections tend towards intra processor core optical communication. Ultimately, we may converge towards a model where: Logic Electrical charges Communication Photons Storage ions Communication at which ever scale is technically potentially feasible. It won’t happen without silicon photonics Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 4
Datacom & More Than Datacom New opportunities in silicon photonics Silicon photonics cannot rely on data communication professional market only. For the industry to develop: - More applications - Huge volumes - More actors - Bigger competition - Lower prices - More innovation However, the applications, even though dissimilar , should make use of almost the same technology. Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 5
Silicon Roadmap Silicon Photonics: A roadmap in the roadmap More than Moore : Diversification MEMS 65nm Information Processing Silicon Photonics More than Datacom : Diversification Sensors Detectors 10Gbps Datacom Baseline CMOS: CPU, Memory, Logic 90nm 45nm Power Non-digital content System-in-Package (SiP) 130nm More Moore : Miniaturization Imaging Datacenter, FTTx, Analog/ RF Information Collection 40Gbps 100Gbps 200Gbps 400Gbps 1Tbps Information Transport 32nm 22nm Connecting Objects Information Storage Internet Of Things 14nm Digital content System-on-Chip (SoC) Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D Mixing up future silicon photonics systems will potentially lead to even better innovation: Typically, a trend in automation is to have robots substituting to humans. Digital logic photonics communication photonics sensor neuronal network nervous network. Rapid detection, rapid dispatch, rapid analysis of information. Applications: Autonomous cars, airplanes, trains, 6
FP7 Project 2013 - 2017 R&D Programs: PARTNERS CEA - LETI IMEC STMICROELECTRONICS STD CROLLES STMICROELECTRONICS MPD AGRATE TNO MENTOR GRAPHICS PHOENIX III-V LABS UNIVERSITY COLLEGE CORK, Tyndall POLYTEC THALES UNIVERSITE PARIS-SUD AIFOTEC FIBEROPTICS NXP SEMICONDUCTORS SI2 Funding: Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D
Project Description PLAT4M - FP7 Project Project full title: " Photonic Libraries And Technology for Manufacturing “ Project Description: PLAT4M's objective is to bring existing silicon photonics research platform to a maturity level which enables seamless transition to industry, suitable for different applications fields and manufacturing volume levels. CEA-LETI IMEC STMicroelectronics SYLPHIDE 200mm MPW ISIPP25G 200mm MPW DAPHNE 300mm R&D Platform Tyndall National Institute Assembly & Packaging Solution Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 8
Technology Setup Building up a new technology Derivative technologies (diversification) are usually launched using existing processes DAPHNE (Datacom Adv. Photonics Nanoscale Env.) is a technology meant for R&D. Both the process and device library evolves. The current and predicted production volumes are the main arguments that usually decide about the amount to be invested in innovation. Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 9
Fabrication Flow Process building blocks compatible with a CMOS foundry Process: The fabrication flow is divided in building blocks so that process development work is done in parallel. The integration activity ensures that the blocks are compatible with each other. Device: While passive devices are all fabricated in a single block, actives devices involve the whole flow. Different technologies coexist within the same foundry. Tools are qualified to be shared among those technologies. Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 10
Silicon Patterning Photonics Integrated circuits Target: Etch silicon so as to define photonic devices & circuits Challenge: Auto-alignment between all devices at chip level Partial etching of silicon with good uniformity The inset shows the waveguide after the whole process Non-Manhattan architectures 350nm strip IL: 3.5 dB/cm 320nm deep-rib 50nm slab IL: 3.7 dB/cm Huge disparity in targeted lateral dimensions & morphologies 400nm mid-rib 160nm slab IL: 1.4 dB/cm Multi-level patterning of silicon is a more than CMOS process building block developed for silicon photonics Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 11
Silicon Patterning Multi-level silicon patterning development to address device requisites Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 12
Germanium Integration 13 High Speed Photodetector New material integration is a challenge in a CMOS foundry. Besides contamination issues, process feasibility must be established. Mono-crystalline germanium includes: - Selective epitaxial growth of Ge using a Si seed masked by SiO2. - Si/Ge lattice mismatch. (10 X 15) µm pure monocrystal Ge obtained by selective epitaxial growth using a patterned silicon seed masked by silicon dioxide - Thermal budget of Ge Interface between germanium and silicon layers showing a good Ge crystal quality Right part of Ge pin photodiode with 3 interconnect metal layers - Chemical compatibility (Ge oxidizes easily. GeOx is soluble in water) - Same implantation strategy as silicon. - Same BEOL devices. Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D of Si
Photonic Integrated Circuit Schematics of a typical PIC Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 14
System Integration 3D integration of EIC & PIC Copper posts and copper pillars are grown on the metal pads. Bonding is done by die-towafer flip chip of the EIC on the PIC. Copper pillars allow direct connection between the middle of the two dies (No routing to die edge). Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 15
Test Vehicle: 100GBase-LR4 Demo Integrated Multiplexed Transmitter 100GBase-LR4 system. transceiver WDM device designed and simulated: Array Waveguide Grating. Stand-alone device shows a loss of 1.2 dB / channel Device integrated in system. Fabrication On-going. Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 16
IRT Project 2012 - 2018 PARTNERS CEA - LETI STMICROELECTRONICS STD CROLLES MENTOR GRAPHICS SAMTEC CNRS R&D Programs: Funding: Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D
Project Description IRT – Nanoelec Project Project full title: " Institut pour la Recherche Technologique “ Project Description: Bring together in a single organization all the tools and know-how to develop silicon photonics solutions that can address a wide variety of applications. New equipment New Process CEA 200mm & 300mm ST 300mm New Material New Devices New Applications Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 18
Silicon Photonics & III-V Integration 19 Does it make sense? 3D Integration of LaMP module at packaging Level Integration of III-V laser coupled to silicon waveguide at wafer level DATACOM It is not clear yet whether an integrated laser at wafer level will correspond to all needs in optical data communication. System providers militate in favors of different approaches. Main parameters DATACOM: OR for - Cost - Footprint Central optical carriers distributed at higher system level DIVERSIFICATION - Power consumption - Reliability - Robustness Lab On Chip System On Chip Bio-Chemical Detection In alternative markets, the constraints are different. Moreover, the need of an integrated source is very likely. Whatever the application, it is very probable that an integrated source will be coveted in future silicon photonics Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D
Source Integration Integrated III-V Laser Typically 3µm thick III-V bonded to SOI waveguide. Close proximity ( 100nm) needed between III-V and Si 500nm waveguide. Surface preparation prior to bonding based on CMP, preventing topography on Si photonics wafer. Topographical problem: similar heights ( 3µm) of laser and 4 level metal stack. Planar surfaces needed (CMP) for III-V/Si bonding and 4 level Cu back-end. The idea : use flat back-side of Si waveguide for laser integration. Si device interconnects on one side, III-V/Si laser on other side. Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 20
Source Integration Integrated III-V Laser Distributed Bragg Reflector hybrid III-V/Si laser cavity emitting at 1310nm Active region : optical mode confined in the III-V waveguide Mirror: DBRs in the Si on both side of the III-V Or any other more complex silicon photonic sub-system: modulator, Mux, Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 21
Source Integration Integrated III-V Laser Light transferred by adaptation of effective index using the super-mode theory*: Variation of the SOI waveguide rib’s width (Wrib) along the propagation direction. Over 97% of the light is transferred to the singlemode waveguide * X. Sun, H.-C. Liu, and A. Yariv, “Adiabaticity criterion and the shortest adiabatic mode transformer in a coupled waveguide system,” Opt. Lett. 34, 280-282 (2009) Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 22
Source Integration Integrated III-V Laser SOI wafer level III-V bonding strategy: Preliminary tests done by wafer-to-wafer bonding Ongoing developments to bond locally patches of III-V material Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 23
H2020 Project 2015 - 2018 PARTNERS CEA - LETI STMICROELECTRONICS STD CROLLES UNIVERSITE PARIS-SUD, IEF STMICROELECTRONICS MPD AGRATE UNIVERSITY OF PAVIA VARIO-OPTICS SEAGATE SYSTEMS (UK) LTD. IUNIVERSITY OF SOUTHAMPTON, ORC UNIVERSITY OF ST ANDREWS FINISAR R&D Programs: Funding: Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D
Project Description COSMICC-H2020 Project Project full title: " CmOs Solutions for Mid-board Integrated transceivers with breakthrough Connectivity at ultra-low Cost “ Project Description: COSMICC consortium will achieve mid-board optical transceivers in the [2Tbit/s, 2pJ/bit, 0.2 /Gbit/s cost]-range. Low Power Electronic Driver (EIC) Efficient 50Gbps NRZ Modulation CWDM4 Multiplexing 24 Fibers I/O 12 X 4 X 50 2400Gbps Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 25
Project Description COSMICC-H2020 Project Project Organization: Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 26
Capacitive Modulators Capacitive structures substituting junctions Vertical Interface Interfacial Oxide n-doped poly-silicon BOX Vertical Integration Horizontal Interface P-doped silicon n-doped poly-silicon Interfacial Oxide P-doped silicon BOX 1.6pF/mm ([3;10]nm range) capacitance oxide oxide thickness 1.2Vpp voltage swing ([0.61.8]V) with a DC bias to put swing around flat-band voltage and use accumulation charges 1.52pJ/bit at 56Gb/s Horizontal Integration 1.1pF/mm ([5;15]nm range) capacitance oxide oxide thickness 0.9Vpp voltage swing ([0.91.8]V) with a DC bias to put swing around flat-band voltage and use accumulation charges 0.37 pJ/bit at 56Gb/s Push-pull MZI with 30 phase shift on both branches: Active Length 1mm Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 27
Summary & Conclusions New feature in CMOS: wafer size did not evolve for more than one and a half decade. Traditionally, old tools were used for diversification (Ex: MEMS). It is not the case for silicon photonics. Silicon photonics shares the same 300mm fab tools as other high-end technologies. Strict regulations about tool contamination or deviation. Process evolution, new material introduction and device integration are all technically possible but not under any conditions. Silicon photonics is a promising market and strategic efforts must be done to cover a wide variety of applications Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 28
R&D Network FP7 Project 2013 - 2017 PARTNERS CEA - LETI IMEC STMICROELECTRONICS STD CROLLES STMICROELECTRONICS MPD AGRATE TNO MENTOR GRAPHICS PHOENIX III-V LABS UNIVERSITY COLLEGE CORK, Tyndall POLYTEC THALES UNIVERSITE PARIS-SUD AIFOTEC FIBEROPTICS NXP SEMICONDUCTORS SI2 H2020 Project 2015 - 2018 PARTNERS CEA - LETI STMICROELECTRONICS STD CROLLES UNIVERSITE PARIS-SUD, IEF STMICROELECTRONICS MPD AGRATE UNIVERSITY OF PAVIA VARIO-OPTICS SEAGATE SYSTEMS (UK) LTD. IUNIVERSITY OF SOUTHAMPTON, ORC UNIVERSITY OF ST ANDREWS FINISAR IRT Project 2012 - 2018 PARTNERS CEA - LETI STMICROELECTRONICS STD CROLLES MENTOR GRAPHICS SAMTEC CNRS Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D 29
Dr. Charles Baudot STMicroelectronics Silicon Photonics R&D Datacom & More Than Datacom 5 New opportunities in silicon photonics Silicon photonics cannot rely on data communication professional market only. For the industry to develop: - More applications - Huge volumes - More actors - Bigger competition - Lower prices - More innovation
The CMOS Process - photolithography (1) Silicon Wafer Silicon Wafer SiO 2 1μm Silicon Wafer photoresist (a) Bare silicon wafer (b) Grow Oxide layer (c) Spin on photoresist Lecture 3 - 4 The CMOS Process - photolithography (2) Silicon Wafer (d) Expose resist to UV light through a MASK Silicon Wafer (e) Remove unexposed resist Silicon Wafer
Silicon has been the dominant semiconductor material since the middle 1960s. Today, probably 95% ofall semiconductors are fabricated in silicon, yet the first transistor was a germanium device. Until 1960 most design engineers preferred germanium to silicon for computer logic circuits, when, suddenly, germanium was out, and silicon was in. What caused this abrupt shift to silicon? An answer to .
A remind of the basic properties of silicon will be of great importance to understand well the silicon nanocrystals properties. 2 PHYSICAL PROPERTIES OF SILICON Silicon is, on Earth, the most abundant element after oxygen; weestimates that the Earth's surface is composed about 26% of silicon. [10] This
Intel's Silicon Photonics Research Innovating with lowInnovating with low-cost silicon to create new optical devicescost silicon to create new optical devices 1st Continuous Wave Silicon Raman Laser (Feb '05) Hybrid Silicon Laser (Sept. '06) Silicon Modulators 1GHz ( Feb '04) 10 Gb/s (Apr '05) 40 Gb/s (July '07) 8-channel integrated
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name of Photonic Integrated Circuits (PICs). Silicon Photonics is a form of PIC that uses silicon substrates and silicon waveguides for the platform. . A key enabler in the silicon photonic revolution has been the development of technologies compatible . [11] L. Chrostowski and M. Hochberg, "Silicon Photonics Design: From Devices to Systems .
Silicon MSDS Section 1: Chemical Product and Company Identification P roduct Name: Silicon C atalog Codes: SLS4102, SLS3313 C AS#: 7440-21-3 R TECS: CW0400000 TSCA: TSCA 8(b) inventory: Silicon C I#: Not applicable. S ynonym: C hemical Name: Silicon Chemical Formula: Si Section 2: Composit
transferred from France or newly created in French: Battle (Sx; La Batailge), Boulge (Sf; Bulges), Bray (Bk; Braia), Cantlop (Sa; Cantelop), Capel St. Andrew (Sf; Capeles), Meshaw (D; Mauessart), Montacute (So; Montagud), Montgomery (Montgomeryshire; Montgomeri/Montgumeri), and a lost Bolebec (DB fol. 254r; PN Sa 1: xii). My analysis of LVVRE confirms its likely membership of this category .
