PCIe-5775 Specifications - National Instruments
SPECIFICATIONSPCIe-577512-Bit, 6.4 GS/s, 2-Channel PCI FlexRIO Digitizer DeviceThis document lists the specifications for the PCIe-5775. Specifications are subject to changewithout notice. For the most recent device specifications, refer to ni.com/support.Note These specifications are typical at 25 C unless otherwise noted.ContentsDefinitions.1Digital I/O. 2Digital I/O Single-Ended Channels.2Digital I/O High-Speed Serial MGT. 3Reconfigurable FPGA.4Onboard DRAM.4Analog Input. 5General Characteristics. 5Typical Specifications. 5REF/CLK IN. 10General Characteristics. 10Bus Interface. 12Maximum Power Requirements.12Physical. 13Environment.13Operating Environment.13Storage Environment.13DefinitionsWarranted specifications describe the performance of a model under stated operatingconditions and are covered by the model warranty.Characteristics describe values that are relevant to the use of the model under stated operatingconditions but are not covered by the model warranty. Typical specifications describe the performance met by a majority of models. Nominal specifications describe an attribute that is based on design, conformance testing,or supplemental testing.
Specifications are Typical unless otherwise noted.Digital I/OConnectorMolex Nano-Pitch I/O 5.0 V Power 5%, 50 mA maximum, nominalTable 1. Digital I/O Signal CharacteristicsSignalTypeDirectionMGT Tx 0.3 1Xilinx UltraScale GTHOutputMGT Rx 0.3 1Xilinx UltraScale GTHInputDIO 0.7 Single-endedBidirectional5.0 VDCOutputGNDGround—Digital I/O Single-Ended ChannelsNumber of channels8Signal typeSingle-endedVoltage families3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 VInput impedance100 kΩ, nominalOutput impedance50 Ω, nominalDirection controlPer channelMinimum required direction changelatency200 nsMaximum output toggle rate60 MHz with 100 μA load, nominal12 Multi-gigabit transceiver (MGT) signals are available on devices with KU040 and KU060 FPGAsonly.ni.com PCIe-5775 Specifications
Table 2. Digital I/O Single-Ended DC Signal Characteristics2Voltage FamilyVILVIHVOLVOH(100µA load) (100µA load)Maximum DC DriveStrength3.3 V0.8 V2.0 V0.2 V3.0 V24 mA2.5 V0.7 V1.6 V0.2 V2.2 V18 mA1.8 V0.62 V 1.29 V0.2 V1.5 V16 mA1.5 V0.51 V 1.07 V0.2 V1.2 V12 mA1.2 V0.42 V 0.87 V0.2 V0.9 V6 mADigital I/O High-Speed Serial MGT3Note MGTs are available on devices with KU040 and KU060 FPGAs only.Data rate500 Mbps to 16.375 Gbps, nominalNumber of Tx channels4Number of Rx channels4I/O AC coupling capacitor100 nFMGT TX ChannelsMinimum differential output voltage4170 mV pk-pk into 100 Ω, nominalI/O couplingAC-coupled with 100 nF capacitorMGT RX ChannelsDifferential input voltage range 6.6 Gb/s150 mV pk-pk to 2000 mV pk-pk, nominal 6.6 Gb/s150 mV pk-pk to 1250 mV pk-pk, nominalDifferential input resistance100 Ω, nominalI/O couplingDC-coupled, requires external capacitor234Voltage levels are guaranteed by design through the digital buffer specifications.For detailed FPGA and High-Speed Serial Link specifications, refer to Xilinx documentation.800 mV pk-pk when transmitter output swing is set to the maximum setting.PCIe-5775 Specifications National Instruments 3
Reconfigurable FPGAPCIe-5775 modules are available with multiple FPGA options. The following table lists theFPGA specifications for the PCIe-5775 FPGA options.Table 3. Reconfigurable FPGA 48 slices(25 18 multiplier)1,7001,9202,760Embedded Block RAM19.0 Mb21.1 Mb38.0 MbData Clock Domain200 MHz, 16 samples per cycle per channel (dual channel mode),32 samples per cycle (single channel mode)Timebase referencesourcesOnboard 100 MHz oscillatorData transfersDMA, interrupts,programmed I/ODMA, interrupts, programmed I/O,multi-gigabit transceiversNumber of DMAchannels60Note The Reconfigurable FPGA Options table depicts the total number of FPGAresources available on the part. The number of resources available to the user isslightly lower, as some FPGA resources are consumed by board-interfacing IP forPCI Express, device configuration, and various board I/O. For more information,contact NI support.Onboard DRAMMemory size4 GB (2 banks of 2 GB)DRAM clock rate1064 MHzPhysical bus width32 bitLabVIEW FPGA DRAM clock rate267 MHzLabVIEW FPGA DRAM bus width256 bit per bankMaximum theoretical data rate17 GB/s (8.5 GB/s per bank)4 ni.com PCIe-5775 Specifications
Analog InputGeneral CharacteristicsNumber of channels2, single-ended, simultaneously sampledConnector typeSMAInput impedance50 ΩInput couplingACSample ClockInternal Sample Clock3.2 GHzExternal Sample Clock2.8 GHz to 3.2 GHzSample RateDual channel mode3.2 GS/s per channelSingle channel mode6.4 GS/sAnalog-to-digital converter (ADC)InputADC12DJ3200, 12-bit resolutionlatency5239 nsTypical SpecificationsFull-scale input range1.25 V pk-pk (5.92 dBm) at 10 MHzAC gain accuracy 0.11 dB at 10 MHzDC offset 2.19 mVBandwidth (-3 dB)6500 kHz to 6 GHzTable 4. Single-Tone Spectral Performance, Dual Channel ModeInput Frequency99.9 MHz399 MHz999 MHz1.999 GHz2.499 GHzSNR7 (dBFS)56.055.654.752.951.6SINAD7 (dBFS)55.555.054.051.850.8SFDR (dBc)-64.9-63.4-62.7-59.9-58.6ENOB8 (bits)8.98.88.78.38.15678SMA input to LabVIEW diagramNormalized to 10 MHz.Measured with a -1 dBFS signal and corrected to full-scale. 3.2 kHz resolution bandwidth.Calculated from SINAD and corrected to full scale.PCIe-5775 Specifications National Instruments 5
Table 5. Single-Tone Spectral Performance, Single Channel Mode9Input Frequency99.9 MHz399 MHz999 MHz1.999 GHz2.499 GHzSNR7 (dBFS)54.654.252.449.748.9SINAD7 (dBFS)54.453.952.149.448.6SFDR (dBc)-61.7-60.4-56.1-51.7-51.1ENOB8 (bits)8.78.78.47.97.8Table 6. Noise Spectral Density10nVHzdBmHzdBFSHzDual channel14.4-143.8-149.2Single channel9.8-147.2-152.6ModeNote Noise spectral density is verified using a 50 Ω terminator connected to theinput.9106 Measured using channel AI0. Spectral performance may be degraded using channel AI1.Excludes fixed interleaving spur (Fs/2 spur).ni.com PCIe-5775 Specifications
Figure 1. Single Tone Spectrum (Dual Channel Mode, 99.9 MHz, -1 dBFS,3.2 kHz RBW), MeasuredFigure 2. Single Tone Spectrum (Dual Channel Mode, 1.999 GHz, -1 dBFS,3.2 kHz RBW), MeasuredPCIe-5775 Specifications National Instruments 7
Figure 3. Single Tone Spectrum (Single Channel Mode, 99.9 MHz, -1 dBFS,3.2 kHz RBW), MeasuredFigure 4. Single Tone Spectrum (Single Channel Mode, 1.999 GHz, -1 dBFS,3.2 kHz RBW), MeasuredChannel-to-channel crosstalk, measured8 99.9 MHz-92.5 dB399 MHz-85.5 dB999 MHz-76.5 dBni.com PCIe-5775 Specifications
1.999 GHz-68.8 dB2.499 GHz-67.4 dBFigure 5. Analog Input Frequency Response, MeasuredPCIe-5775 Specifications National Instruments 9
Figure 6. Input Return Loss, MeasuredREF/CLK INGeneral CharacteristicsConnector typeSMAInput impedance50 ΩInput couplingACInput voltage range0.35 V pk-pk to 3.5 V pk-pk, nominalAbsolute maximum voltage 12 V DC, 4 V pk-pk ACDuty cycle45% to 55%Sample Clock jitter111210 Analog input86.8 fsrms, measured11Analog output198.8 fsrms, measured12Integrated from 3.2 kHz to 20 MHz. Includes the effects of the converter aperture uncertainty andthe clock circuitry jitter. Excludes trigger jitter.Integrated from 1 kHz to 30 MHz. Includes the effects of the converter aperture uncertainty,converter PLL circuitry, and the clock circuitry jitter. Excludes trigger jitter.ni.com PCIe-5775 Specifications
Table 7. Clock Configuration OptionsClock ConfigurationExternal ClockFrequencyDescriptionInternal BaseboardReference Clock1310 MHzThe internal Sample Clock locks tothe 10 MHz Reference Clockprovided from the FPGA baseboard.External Reference Clock(REF/CLK IN)10 MHz14External Sample Clock(REF/CLK IN)2.8 GHz to 3.2 GHzThe internal Sample Clock locks to anexternal Reference Clock, which isprovided through the REF/CLK INfront panel connector.An external Sample Clock can beprovided through the REF/CLK INfront panel connector.Figure 7. Analog Input Phase Noise with 800 MHz Input Tone, Measured1314Default clock configuration.The external Reference Clock must be accurate to 25 ppm.PCIe-5775 Specifications National Instruments 11
Figure 8. Analog Output Phase Noise with 1 GHz Output Tone, MeasuredBus InterfaceCard edge form factorPCI Express Gen-3 x8Slot compatibilityx8 and x16 PCI Express slotsMaximum Power RequirementsNote Power requirements are dependent on the contents of the LabVIEW FPGAVI used in your application. 3.3 V4.5 A 12 V5AMaximum total power75 W12 ni.com PCIe-5775 Specifications
PhysicalDimensions (including I/O bracket, notincluding connectors)12.6 cm 26.3 cm 4 cm (5.0 in. 10.4 in. 1.6 in.)Weight990 g (35 oz)PCI Express mechanical form factorStandard height, three-quarter length, doubleslotIntegrated air mover (fan)YesMaximum rear panel exhaust airflow84 m3/h (50 CFM) (without any chassisimpedance)EnvironmentMaximum altitude2,000 m (800 mbar) (at 25 C ambienttemperature)Pollution Degree2Indoor use only.Operating EnvironmentOperating temperature, local150 C to 45 COperating humidity10% to 90% RH, noncondensingStorage EnvironmentAmbient temperature range-20 C to 70 CRelative humidity range5% to 95% RH, noncondensing15For PCI Express adapter cards with integrated air movers, NI defines the local operational ambientenvironment to be at the fan inlet. For cards without integrated air movers, NI defines the localoperational ambient environment to be 25 mm (1 in.) upstream of the leading edge of the card.PCIe-5775 Specifications National Instruments 13
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PCIe-5775 modules are available with multiple FPGA options. The following table lists the FPGA specifications for the PCIe-5775 FPGA options. Table 3. Reconfigurable FPGA Options KU035 KU040 KU060 LUTs 203,128 242,200 331,680 DSP48 slices (25 18 multiplier) 1,7
PowerVM Enterprise Edition N/A N/A N/A Max logical partitions/micro-partitions N/A N/A N/A System unit PCIe Gen3 slots a 3 PCIe x8 1 PCIe x16 2 PCIe x8 3 PCIe x16 2 PCIe x8 3 PCIe x16 Max PCIe
PowerVM Enterprise Edition Optional Optional Max logical partitions/micro-partitions 160 480 System unit PCIe Gen3 full high slots a 5 PCIe x8 2 PCIe x16 7 PCIe x8 4 PCIe x16 PCIe expansion I/O drawer 0, but SO
PowerVM Enterprise Edition Optional Optional Max logical partitions/micro-partitions 160 480 System unit PCIe Gen3 full high slots a 5 PCIe x8 2 PCIe x16 7 PCIe x8 4 PCIe x16 PCIe expansion I/O drawer 0, but SO
Jun 30, 2016 · To connect through a PCIe Connector: 1. Make sure the PCIe card is installed in your host computer. See the documentation supplied with your host computer for information on installing a PCIe card. The PCIe card should be installed in a Gen 3 x4 PCIe slot in the system, or a Gen 2 x4 PCIe
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PCIe Switches- Beyond DMA MCTP message-based possible attacks Message spoofing: Possible by spoofing source/ destination endpoint ID of MCTP messages. Software send BMC privilege level platform management commands : Exploiting PCIe packet injector or other issues in PCIe EP devices Messages can also be sent from PCIe switches
DMA block Control registers PCIe block FPGA based DAQ system PCIe M e a s u r e m e n t d a t a AXI4 Stream The IP-core used as a DMA engine and PCIe block was the Xilinx DMA for PCIe also known as XDMA. The block supports 64-bit addressing at the PCIe side, so it could be used with huge (above 4GB) sets of DMA buffers.
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