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Intel Open Source HD Graphics, Intel Iris Graphics, andIntel Iris Pro GraphicsProgrammer's Reference ManualFor the 2015 - 2016 Intel Core Processors, Celeron Processors,and Pentium Processors based on the "Skylake" PlatformVolume 3: GPU OverviewMay 2016, Revision 1.0
GPU OverviewCreative Commons LicenseYou are free to Share - to copy, distribute, display, and perform the work under the followingconditions: Attribution. You must attribute the work in the manner specified by the author or licensor (butnot in any way that suggests that they endorse you or your use of the work). No Derivative Works. You may not alter, transform, or build upon this work.Notices and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NOLICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTSIS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALEFOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANYEXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDINGLIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, ORINFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.A "Mission Critical Application" is any application in which failure of the Intel Product could result,directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTSFOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITSSUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEESOF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLEATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY,PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION,WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE,OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.Intel may make changes to specifications and product descriptions at any time, without notice. Designersmust not rely on the absence or characteristics of any features or instructions marked "reserved" or"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever forconflicts or incompatibilities arising from future changes to them. The information here is subject tochange without notice. Do not finalize a design with this information.The products described in this document may contain design defects or errors known as errata whichmay cause the product to deviate from published specifications. Current characterized errata areavailable on request.Implementations of the I2C bus/protocol may require licenses from various entities, including PhilipsElectronics N.V. and North American Philips Corporation.Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.* Other names and brands may be claimed as the property of others.Copyright 2016, Intel Corporation. All rights reserved.iiDoc Ref # IHD-OS-SKL-Vol3-05.16
GPU OverviewTable of ContentsIntroduction . 2Graphics Processing Unit (GPU) . 2GPU Overview . 3Command Stream (CS) Unit . 43D Pipeline . 4Media Pipeline . 4Thread Dispatching . 4Execution Units (EUs) . 4Shared Functions . 5Fixed and Shared Function IDs . 6Register Address Maps . 7Graphics Register Address Map . 7Memory and IO Space Registers . 7VGA and Extended VGA Register Map . 7VGA and Extended VGA I/O and Memory Register Map . 8Indirect VGA and Extended VGA Register Indices . 9Memory Object Overview .12Hardware Status Page .13Memory Access Indirection .13Instruction Ring Buffers .15Instruction Batch Buffers .15Logical Contexts .16BSD Logical Render Context Address (LRCA) .16Overall Context Layout .16Register/State Context .17Ring Buffer .18Ring Context .18The Per-Process Hardware Status .19Video Engine Power Context.20Copy Engine Logical Context Data .22Context Layout .22Doc Ref # IHD-OS-SKL-Vol3-05.16iii
GPU OverviewRegister/State Context .22Ring Buffer .23Ring Context .24The Per-Process Hardware Status Page .24Blitter Engine Power Context .25Video Enhancement Logical Context Data .27Context Layout .27Ring Context .27Register/State Context .28Video Enhancement Engine Power Context .29Memory Data Formats .31Unsigned Normalized (UNORM).31Gamma Conversion (SRGB) .31Signed Normalized (SNORM).31Unsigned Integer (UINT/USCALED) .32Signed Integer (SINT/SSCALED) .32Floating Point (FLOAT) .3264-bit Floating Point .3232-bit Floating Point .3316-bit Floating Point .3311-bit Floating Point .3410-bit Floating Point .35Shared Exponent .35Memory Compression .36Media Memory Compression .36ivDoc Ref # IHD-OS-SKL-Vol3-05.16
GPU OverviewIntroductionThe integrated graphics component, specifically called the Graphics Processing Unit, or GPU, resides onthe same chip die as the Central Processing Unit, or CPU, and communicates with the CPU via the onchip bus, with internal memory and with output device(s). As Intel GPUs have evolved, they now occupy asignificant percentage of space on the chip, and provide customers with high performance and lowpower graphics processing, eliminating the need to purchase a separate video card for most users.This Programmer’s Reference Manual (PRM) provides detailed narrative and referential informationrequired by graphics device driver engineers and graphics API-level programmers to take advantage ofthe sophisticated architecture and programmability of the GPU.Graphics Processing Unit (GPU)The Graphics Processing Unit is controlled by the CPU through a direct interface of memory-mapped IOregisters, and indirectly by parsing commands that the CPU has placed in memory. The Display interfaceand Blitter (block image transferrer) are controlled primarily by direct CPU register addresses, while the3D and Media pipelines and the parallel Video Codec Engine (VCE) are controlled primarily throughinstruction lists in memory.The subsystem contains an array of cores, or execution units, with a number of “shared functions”, whichreceive and process messages at the request of programs running on the cores. The shared functionsperform critical tasks, such as sampling textures and updating the render target (usually the framebuffer). The cores themselves are described by an instruction set architecture, or ISA.Block Diagram of the GPU2Doc Ref # IHD-OS-SKL-Vol3-05.16
GPU OverviewGPU OverviewThe subsystem consists of an array of execution units (EUs, sometimes referred to as an array of cores)along with a set of shared functions outside the EUs that the EUs leverage for I/O and for complexcomputations. Programmers access the subsystem via the 3D or Media pipelines.EUs are general-purpose programmable cores that support a rich instruction set that has been optimizedto support various 3D API shader languages as well as media functions (primarily video) processing.Shared functions are hardware units which serve to provide specialized supplemental functionality for theEUs. A shared function is implemented where the demand for a given specialized function is insufficientto justify the costs on a per-EU basis. Instead a single instantiation of that specialized function isimplemented as a stand-alone entity outside the EUs and shared among the EUs.Invocation of the shared functionality is performed via a communication mechanism called a message. Amessage is a small self-contained packet of information created by a kernel and directed to a specificshared function. For SNB, the message is defined by a range of MRF registers that hold messageoperands, a destination shared function ID, a function-specific encoding of the desired operation, and adestination GRF register to which any writeback response is to be directed. Messages are dispatched tothe shared function under software control via the send instruction. This instruction identifies thecontents of the message and the GRF register locations to direct any response.The message construction and delivery mechanisms are general in their definition and capable ofsupporting a wide variety of shared functions.Doc Ref # IHD-OS-SKL-Vol3-05.163
GPU OverviewCommand Stream (CS) UnitThe Command Stream (CS) unit manages the use of the 3D and Media pipelines; it performs switchingbetween pipelines and forwarding command streams to the currently active pipeline. It managesallocation of the URB and helps support the Constant URB Entry (CURBE) function.3D PipelineThe 3D Pipeline provides specialized 3D primitive processing functions. These functions are provided bya pipeline of “fixed function” stages (units) and GEN threads spawned by these units. See 3D PipelineOverview.Media PipelineThe Media pipeline provides both specialized media-related processing functions and the ability toperform more general (“generic”) functionality. These Media-specific functions are provided by a VideoFront End (VFE) unit. A Thread Spawner (TS) unit is utilized to spawn GEN threads requested by the VFEunit, or as required when the pipeline is used for general processing. See Media Pipeline Overview.Thread DispatchingWhen the 3D and Media pipelines send requests for thread initiation to the Subsystem, the threadDispatcher receives the requests. The dispatcher performs such tasks as arbitrating between concurrentrequests, assigning requested threads to hardware threads on EUs, allocating register space in each EUamong multiple threads, and initializing a thread’s registers with data from the fixed functions and fromthe URB. This operation is largely transparent to software.Execution Units (EUs)The Execution Units (EUs) are the programmable shader units of the Gen Architecture. Each is a standalone programmable computational unit used for execution of 3D shaders and media/gpgpu kernels.Internally each is capable of multi-issue SIMD execution, and their hardware multi-threaded operationprovides a very high-efficiency execution environment in the face of long data latencies typicallyassociated with memory accesses. Each hardware thread within an EU has a dedicated large-capacityhigh-bandwidth register file (GRF) and associated independent thread-state. Execution is multi-issue perclock to pipelines capable of integer, single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and other miscellaneous operations.Communication to support units (shared functions) for operations such as texture sampling orscatter/gather load/stores is via ‘messages’ programmatically constructed and ‘sent’ to those functions,with dependency hardware causing the issuing thread to sleep until the requested data has beenreturned.EU instance count varies by product generation, as well as by SKU within a given generation, and theircapabilities have evolved over the many generation of the Gen Architecture. Please see “DeviceAttributes” in the “Configuration” chapter for specific rates and capacities associated with ExecutionUnits.4Doc Ref # IHD-OS-SKL-Vol3-05.16
GPU OverviewShared FunctionsShared functions are hardware units that provide specialized supplemental functionality for the EUs. Ashared function is implemented where the demand for a given specialized function is insufficient tojustify the costs on a per-EU basis. Instead a single instantiation of that specialized function isimplemented as a stand-alone entity outside the EUs and shared among the EUs.Invocation of the shared functionality is performed via a communication mechanism called a message. Amessage is a small self-contained packet of information created by a kernel and directed to a specificshared function.Programming NoteContext:Communication mechanism in shared functionsThe message is defined by a range of Message Register File (MRF) registers that hold message operands, adestination shared function ID, a function-specific encoding of the desired operation, and a destination GeneralRegister File (GRF) register to which any writeback response is directed.Messages are dispatched to the shared function under software control via the send instruction. Thisinstruction identifies the contents of the message and the GRF register locations to direct any response.The message construction and delivery mechanisms are general in their definition and capable ofsupporting a wide variety of shared functions.Doc Ref # IHD-OS-SKL-Vol3-05.165
GPU OverviewFixed and Shared Function IDsThe following table lists the assignments (encodings) of the Shared Function and Fixed Function IDs usedwithin the GPE. A Shared Function is a valid target of a message initiated via a send instruction. A FixedFunction is an identifiable unit of the 3D or Media pipeline. Note that the Thread Spawner is both aShared Function and Fixed Function.Function IDsID[3:0]SFIDShared FunctionFFIDFixed Function0x0SFID NULLNullFFID NULLNull0x1Reserved---Reserved---0x2SFID SAMPLERSamplerReserved---0x3SFID GATEWAYMessage GatewayReserved---0x4SFID DP DC2Data Cache Data Port2FFID HSHull Shader0x5SFID DP RCRender Cache Data PortFFID DSDomain Shader0x6SFID URBURBReserved---0x7SFID SPAWNERThread SpawnerFFID SPAWNERThread Spawner0x8SFID VMEVideo Motion EstimationFFID VFEVideo Front End0x9SFID DP DCROData Cache Read Only Data PortFFID VSVertex Shader0xASFID DP DC0Data Cache Data Port0FFID CSCommand Stream0xBSFID PIPixel InterpolatorFFID VFVertex Fetch0xCSFID DP DC1Data Cache Data Port1FFID GSGeometry Shader0xDSFID CRECheck & Refinement EngineFFID VFEVideo Front End0xEReserved---FFID SFStrip/Fan Unit0xFReserved---FFID WMWindower/Masker UnitProgramming NoteContext:Shared Function IDSFID DP DC1 is an extension of SFID DP DC0 to allow for for more messages types. They act as a single logicalentity.Programming NoteContext:Shared Function IDSFID DP DC1 , SFID DP DC2, and SFID P DC3 are extensions of SFID DP DC0 to allow for more messages types.They act as a single logical entity.6Doc Ref # IHD-OS-SKL-Vol3-05.16
GPU OverviewRegister Address MapsGraphics Register Address MapThis chapter provides address maps of the graphics controllers I/O and memory-mapped registers.Individual register bit field descriptions are provided in the following chapters. PCI configuration addressmaps and register bit descriptions are provided in the following chapter.Memory and IO Space RegistersThese are graphics MMIO ranges used for SKL. Note that this is only a subset of the complete definitionof the MMIO address space.Range Start (Hex)Range End (Hex)Unit Owning the Range0000200000002FFFRender/Generic Media Engine0000400000004FFFRender/Generic Media Graphics Memory Arbiter00012000000123FFMFX Control Engine (Video Command Streamer)0001240000012FFFMedia Units (VIN Unit)0001400000014FFFMFX Memory Arbiter0002200000022FFFBlitter Engine0002400000024FFFBlitter Memory Arbiter0010000000107FFFFence Registers001400000017FFFFMCHBAR (SA)Programming NoteContext:Memory and IO space registers, graphics MMIO ranges8800h-88FFh is a reserved range for GT. IA accesses to this region have no impact.VGA and Extended VGA Register MapFor I/O locations, the value in the address column represents the register I/O address. For memorymapped locations, this address is an offset from the base address programmed in the MMADR register.Doc Ref # IHD-OS-SKL-Vol3-05.167
GPU OverviewVGA and Extended VGA I/O and Memory Register MapAddressRegister Name (Read)Register Name (Write)2D Registers3B0h–3B3hReservedReserved3B4hVGA CRTC Index (CRX)(monochrome)VGA CRTC Index (CRX) (monochrome)3B5hVGA CRTC Data (monochrome)VGA CRTC Data (monochrome)3B6h–3B9hReservedReserved3BahVGA Status Register (ST01)VGA Feature Control Register (FCR)3BBh–3BFhReservedReserved3C0hVGA Attribute Controller Index(ARX)VGA Attribute Controller Index (ARX)/VGA Attribute Controller Data (alternating writes select ARX orwrite ARxx Data)3C1hVGA Attribute Controller Data(read ARxx data)Reserved3C2hVGA Feature Read Register (ST00)VGA Miscellaneous Output Register (MSR)3C3hReservedReserved3C4hVGA Sequencer Index (SRX)VGA Sequencer Index (SRX)3C5hVGA Sequencer Data (SRxx)VGA Sequencer Data (SRxx)3C6hVGA Color Palette Mask (DACMASK) VGA Color Palette Mask (DACMASK)3C7hVGA Color Palette State (DACSTATE) VGA Color Palette Read Mode Index (DACRX)3C8hVGA Color Palette Write ModeIndex (DACWX)VGA Color Palette Write Mode Index (DACWX)3C9hVGA Color Palette Data (DACDATA)VGA Color Palette Data (DACDATA)3CAhVGA Feature Control Register (FCR)Reserved3CBhReservedReserved3CChVGA Miscellaneous Output Register(MSR)Reserved3CDhReservedReserved3CEhVGA Graphics Controller Index(GRX)VGA Graphics Controller Index (GRX)3CFhVGA Graphics Controller Data(GRxx)VGA Graphics Controller Data (GRxx)3D0h–3D1hReservedReserved2D Registers3D4hVGA CRTC Index (CRX)VGA CRTC Index (CRX)3D5hVGA CRTC Data (CRxx)VGA CRTC Data (CRxx)System Configuration Registers8Doc Ref # IHD-OS-SKL-Vol3-05.16
GPU OverviewAddressRegister Name (Read)Register Name (Write)3D6hGFX/2D Configurations ExtensionsIndex (XRX)GFX/2D Configurations Extensions Index (XRX)3D7hGFX/2D Configurations ExtensionsData (XRxx)GFX/2D Configurations Extensions Data (XRxx)2D Registers3D8h–3D9hReservedReserved3DAhVGA Status Register (ST01)VGA Feature Control Register (FCR)3DBh–3DFhReservedReservedIndirect VGA and Extended VGA Register IndicesThe registers listed in this section are indirectly accessed by programming an index value into theappropriate SRX, GRX, ARX, or CRX register. The index and data register address locations are listed inthe previous section. Additional details concerning the indirect access mechanism are provided in theVGA and Extended VGA Register Description Chapter (see SRxx, GRxx, ARxx or CRxx sections).2D Sequence Registers (3C4h / 3C5h)Index SymDescription00hSR00 Sequencer Reset01hSR01 Clocking Mode02hSR02 Plane / Map Mask03hSR03 Character Font04hSR04 Memory Mode07hSR07 Horizontal Character Counter Reset2D Graphics Controller Registers (3CEh / 3CFh)Index SymRegister Name00hGR00 Set / Reset01hGR01 Enable Set / Reset02hGR02 Color Compare03hGR03 Data Rotate04hGR04 Read Plane Select05hGR05 Graphics Mode06hGR06 Miscellaneous07hGR07 Color Don’t Care08hGR08 Bit Mask10hGR10 Address Mapping11hGR11 Page SelectorDoc Ref # IHD-OS-SKL-Vol3-05.169
GPU OverviewIndex Sym18hRegister NameGR18 Software Flags2D Attribute Controller Registers (3C0h / 3C1h)Index SymRegister Name00hAR00 Palette Register 001hAR01 Palette Register 102hAR02 Palette Register 203hAR03 Palette Register 304hAR04 Palette Register 405hAR05 Palette Register 506hAR06 Palette Register 607hAR07 Palette Register 708hAR08 Palette Register 809hAR09 Palette Register 90AhAR0A Palette Register A0BhAR0B Palette Register B0ChAR0C Palette Register C0DhAR0D Palette Register D0EhAR0E Palette Register E0FhAR0F Palette Register F10hAR10 Mode Control11hAR11 Overscan Color12hAR12 Memory Plane Enable13hAR13 Horizontal Pixel Panning14hAR14 Color Select2D CRT Controller Registers (3B4h / 3D4h / 3B5h / 3D5h)Index SymRegister Name00hCR00 Horizontal Total01hCR01 Horizontal Display Enable End02hCR02 Horizontal Blanking Start03hCR03 Horizontal Blanking End04hCR04 Horizontal Sync Start05hCR05 Horizontal Sync End06hCR06 Vertical Total07hCR07 Overflow10Doc Ref # IHD-OS-SKL-Vol3-05.16
GPU OverviewIndex SymRegister Name08hCR08 Preset Row Scan09hCR09 Maximum Scan Line0AhCR0A Text Cursor Start0BhCR0B Text Cursor End0ChCR0C Start Address High0DhCR0D Start Address Low0EhCR0E Text Cursor Location High0FhCR0F Text Cursor Location Low10hCR10 Vertical Sync Start11hCR11 Vertical Sync End12hCR12 Vertical Display Enable End13hCR13 Offset14hCR14 Underline Location15hCR15 Vertical Blanking Start16hCR16 Vertical Blanking End17hCR17 CRT Mode18hCR18 Line Compare22hCR22 Memory Read Latch DataDoc Ref # IHD-OS-SKL-Vol3-05.1611
GPU OverviewMemory Object OverviewAny memory data accessed by the device is considered part of a memory object of some memory objecttype.The following table lists the various memory objects types and an indication of their role in the system.Memory Object TypeRoleGraphics TranslationTable (GTT)Contains PTEs used to translate "graphics addresses" into physical memory addresses.Hardware Status PageCached page of sysmem used to provide fast driver synchronization.Logical Context BufferMemory areas used to store (save/restore) images of hardware rendering contexts.Logical contexts are referenced via a pointer to the corresponding Logical Context Buffer.Ring BuffersBuffers used to transfer (DMA) instruction data to the device. Primary means ofcontrolling rendering operations.Batch BuffersBuffers of instructions invoked indirectly from Ring Buffers.State DescriptorsContains state information in a prescribed layout format to be read by hardware. Manydifferent state descriptor formats are supported.Vertex BuffersBuffers of 3D vertex data indirectly referenced through "indexed" 3D primitiveinstructions.VGA Buffer(Must be mapped UCon PCI)Graphics memory buffer used to drive the display output while in legacy VGA mode.Display SurfaceMemory buffer used to display images on display devices.Overlay SurfaceMemory buffer used to display overlaid images on display devices.Overlay Register, FilterCoefficientsMemory area used to provide double-buffer for Overlay register and filter coefficientloading.Cursor SurfaceHardware cursor pattern in memory.2D Render SourceSurface used as primary input to 2D rendering operations.2D Render R-M-WDestination2D rendering output surface that is read in order to be combined in the renderingfunction. Destination surfaces that accessed via this Read-Modify-Write mode havesomewhat different restrictions than Write-Only Destination surfaces.2D Render Write-OnlyDestination2D rendering output surface that is written but not read by the 2D rendering function.Destination surfaces that accessed via a Write-Only mode have somewhat differentrestrictions than Read-Modify-Write Destination surfaces.2D MonochromeSource1 bpp surfaces used as inputs to 2D rendering after being converted toforeground/background colors.2D Color Pattern8x8 pixel array used to supply the "pattern" input to 2D rendering functions.DIB"Device Independent Bitmap" surface containing "logical" pixel values that are converted(via LUTs) to physical colors.3D Color BufferSurface receiving color output of 3D rendering operations. May also be accessed via R-MW (aka blending). Also referred to as a Render Target.12Doc Ref # IHD-OS-SKL-Vol3-05.16
GPU OverviewMemory Object TypeRole3D Depth BufferSurface used to hold per-pixel depth and stencil values used in 3D rendering operations.Accessed via RMW.3D Texture MapColor surface (or collection of surfaces) which provide texture data in 3D renderingoperations."Non-3D" TextureSurface read by Texture Samplers, though not in normal 3D rendering operations (forexample, in video color conversion functions).Motion Comp SurfacesThese are the Motion Comp reference pictures.Mo
The integrated graphics component, specifically called the Graphics Processing Unit, or GPU, resides on the same chip die as the Central Processing Unit, or CPU, and communicates with the CPU via the on-ch
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