DDR Basics, Register Configurations & Pitfalls
July, 2009DDR Basics, Register Configurations &PitfallsMazyar Razzaz,Applications EngineerTMFreescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product orservice names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.1
Agenda BasicDDR SDRAMMemory Organization & Operation Read and write timing Power Features & Capabilities Power QUICC DDR ControllersInitialization & Register Configurations Power QUICC DDR ControllersQUICC DDR ControllersPitfalls / Debug TipsFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM2
Basic DDR SDRAMMemory Organization & OperationFreescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product orservice names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM3
Single Transistor Memory CellColumn (bit) lineRow (word) lineG“1” Vcc“0” GndSD“precharged” to Vcc/2CbitCcolVcc/2Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM4
Single Transistor Memory CellColumn (bit) lineRow (word) lineG“1” Vcc“0” GndS“precharged” to Vcc/2CbitStorageCapacitorDCcolVcc/2Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM5
Single Transistor Memory CellAccessTransistorRow (word) lineG“1” Vcc“0” GndSD“precharged” to Vcc/2CbitStorageCapacitorColumn (bit) lineCcolVcc/2Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM6
Single Transistor Memory CellAccessTransistorRow (word) lineG“1” Vcc“0” GndSD“precharged” to Vcc/2CbitStorageCapacitorColumn (bit) lineCcolParasitic LineCapacitanceVcc/2Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM7
Memory ArraysROW ADDRESS DECODERB0B1B2B3B4B5B6B7W0W1W2SENSE AMPS & WRITE DRIVERSCOLUMN ADDRESS DECODERFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM8
Memory ArraysB0B1B2B3B4B5B6B7ROW ADDRESS DECODERW0W1W2SENSE AMPS & WRITE DRIVERSCOLUMN ADDRESS DECODERFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM9
Memory ArraysB0B1B2B3B4B5B6B7ROW ADDRESS DECODERW0W1W2SENSE AMPS & WRITE DRIVERSCOLUMN ADDRESS DECODERFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM10
Internal Memory Banks Multiple Multiple arrays organized into banksbanks per memory deviceDDR1 – 4 banks, 2 bank address (BA) bitsDDR2 & DDR3– 4 or 8 banks, 2 or 3 bank address (BA) bitsCan have one active row in each bank at any given time Concurrency Can be opening or precharging a row in one bank while accessing another bank Maybe referred to as “internal”, “logical” or “sub-” banksBank 0Bank 1Bank 2Bank 3Row 0Row 1Row 2Row 3Row RowBuffersFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM11
Memory AccessBank 0 Arequested row is ACTIVATEDand made accessible throughthe bank’s row buffer.RowRowRowRowRowBank 1Bank 2Bank 30123 RowBuffersand/or WRITE areissued to the active row. READsRowRowRowRowRow0123 RowBuffers Therow is PRECHARGED andis no longer accessible throughthe bank’s row buffer.RowRowRowRowRow0123 RowBuffersFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM12
Example – DDR2 SDRAM InfineonHYB18T256800AF orMicron MT47H32M8 32Mx 8 (8M x 8 x 4 banks) 256 Mb total 13-bit row address 8K rows 10-bit column address 1K bits/row (8K total when you takeinto account the x8 width) 2-bit bank addressFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM13
Example – DDR2 DIMM InfineonHYS72T3200HU orMicron MT9HTF3272A/CSnODTn32M x 8A[12:0]DQ[7:0]BA[1:0]DQS/DQS/RASMDQ[0:7], MDQS0, MDM0MDQ[8:15], MDQS1, MDM1DM/CASMDQ[16:23], MDQS2, MDM2/WE 9each 32M x 8 memorydevices 32M x 72 overall 256 MB total Single “rank” 9 “byte lanes”MDQ[24:31 MDQS3, MDM3CKEMDQ[32:39], MDQS4, MDM4CK/CKMDQ[40:47], MDQS5, MDM5MDQ[48:55], MDQS6, MDM6ODT/CSMDQ[56:31], MDQS7, MDM732M x 8A[12:0]DQ[7:0]BA[1:0]DQS/DQS/RASECC[0:7], MDQS8, MDM8DM/CAS/WECKECK/CKODT/CSFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM14
DDR1/DDR2/DDR3 Basic Command TIVELLHHBA, RowREADLHLHBA, ColWRITELHLLBA, ColPRECHARGELLHLBAPRECHARGE ALLLLHLA[10]REFRESHLLLHXLOAD MODE REGISTERLLLLBank,OpCodeFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM15
DDR2-533 Read Timing ExampleMem ClkTck 3.75 nsREADACTIVETrcd (ACTTORW ) 4 clkREADTccd 2 clkPRECHARGETrtp (RD TO PRE) 2 clkTrp (PRETOACT) 4 clk/CS/RAS/CAS/WEAddressBA, ROWBA, COLBA, COLBACASLAT 4 clkDQSDQFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.D0D1D2D3D0D1D2D3TM16
DDR2-533 Write Timing ExampleMem ClkTck 3.75 nsACTIVEPRECHARGEWRITETrcd (ACTTORW ) 4 clk/CS/RAS/CAS/WEAddressBA, ROWBA, COLBAWR LAT CASL AL -1 3 clkTwr (WRREC) 4 clkDQSDQD0D1D2D3DM0000Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM17
DDR1/DDR2/DDR3 ComparisonFeatureDDR1DDR2DDR3PackageTSOPBGA onlyBGA onlyVoltages2.5V Core, 2.5V I/O1.8V Core, 1.8V I/O1.5V Core, 1.5V I/ODensities64Mb-1Gb256Mb-4Gb256Mb-8GbInternal Banks44 or 88Prefetch (min WRITE burst)248266-400 Mbps400–800 Mbps800–1600 Mbps2, 2.5, 3 Clk3, 4, 5 AL Clk5, 6, 7 AL Clk1READ Latency - 1CAS write LatancySSTL 2SSTL 18SSTL 15TerminationParallel termination toVTT for all signalsOn-die for data group.VTT termination foraddress, command, andcontrolOn-die terminationfor data, address,command, andcontrolData StrobesSingle EndedSingle or DifferentialDifferentialData RateCAS / READ LatencyWRITE LatencyI/O SignalingFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM18
PowerQUICC DDR ControllersFeatures & CapabilitiesFreescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product orservice names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM19
DDR1/DDR2/DDR3 Controller Features & Capabilities Supportsmost JEDEC standard x8, x16, x32 DDR1 & 2 & 3 devices Memory device densities from 64Mb – through 4Gb Data rates up to: 333 Mb/s for DDR1, 800 Mb/s for DDR2 and DDR3 Devices with 12-16 row address bits, 8-11 column address bits, 2-3logical bank address bits Data mask signals for sub-doubleword writes Up to four physical banks (chip selects) Physical bank sizes up to 4GB, total memory up to 16GB percontroller Physical bank interleaving between 2 or 4 chip selects Memory controller interleaving when more than 2 controllers areavailable Unbuffered or registered DIMMsFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM20
DDR1/DDR2/DDR3 Controller Features & Capabilities (cont.) Upto 32 open pagesOpen row table Amount of time rows stay open is programmable Auto-precharge,globally or by chip select Self-refresh Upto 8 posted refreshes Automatic or software controlled memory device initialization ECC: 1-bit error correction, 2-bit error detection, detection of allerrors within a nibble ECC error injection Read-modify-write for sub-doubleword writes when using ECC Automatic data initialization for ECC Dynamic power managementFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM21
DDR2/DDR3 Controller additional Features & Capabilities Partialarray self refresh Address & command parity for Registered DIMM Independent driver impedance setting for data, address/command,and clock Mirrored DIMM supported Automatic CPO (operational) Write-leveling for DDR3 Automatic ZQ calibration for DDR3 Fixed or On-the-fly Burst chop mode for DDR3 Asynchronous RESET for DDR3Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM22
Fly By Routing Topology Introductionof “Fly-by” architectureAddress, command, control & clocks Improved signal integrity enabling higher speeds On module termination Matched tree routing of clk command and ctrlDDR2 DIMMControllerFly by routing of clk, command and ctrlDDR3 DIMMVTTControllerFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM23
Fly By Routing Improved SIDDR2 Matched tree routingDDR3 Fly by routingFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM24
What is write levelingDuring a write cycle, the skew between the clock and strobes areincreased with the fly-by topology. The write leveling will delay the strobe(and the corresponding data lane) for each byte lane toreduce/compensate for this delay.Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM25
Read Adjustment Automatic CAS to preamblecalibration Data strobe to data skewadjustmentAddress,Command& Clock BusFreescaleChipData LanesInstead of JEDEC’s MPR method, Freescale controllers use a proprietary method of readadjust method. Auto CPO will provide the expected arrival time of preamble for each strobe lineof each byte lane during the read cycle to adjust for the delays cased by the fly-by topology.Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM26
Write Adjustment Write leveling used to add delayto each strobe/data line.Address,Command& Clock BusFreescaleChipData LanesWrite leveling sequence during the initialization process will determine theappropriate delays to each strobe/data byte lane and add this delay for every writecycle.Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM27
PowerQUICC DDR ControllersInitialization and Register ConfigurationsFreescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product orservice names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM28
DDR3 Initialization FlowPower-upDRAMsInitializedMode RegisterCommands IssuedDDR3’sConductPrechargeZQCalibrationZQCL Issued (512 clocks)Also DLL lock time is occurringChip selectsenabled andDDR clocksbeginWriteLevelingCKE HIGHReadAdjustAsserted atleast 200usDDRResetNeed atleast 500usfrom resetdeassertionto thecontrollerbeingenabled.Timed loopmay beneeded.DDRCTRLINITStableCLKSControllerStartedMEM EN 1Automatically handledBy the controllerAutomatic CAS-to-Preamble(aka Read Leveling) .Plus Data-to-Strobe adjustmentInitCompleteFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.Ready for User accessesTM29
DDR2 Initialization FlowPower-upDDRCTRLINITChip selectsenabled andDDR clocksbeginStableCLKSCKE HIGHIssued by controllerDRAMsInitializedMode Registers ProgrammedIssued by controllerReadDQStDLLAdjust WaitAdjusttDLL 512 clocksReadInitDQSCalibrationCompleteAdjust200 usControllerStartedPrechargeAllReady for User accessesMEM EN 1Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM30
Register configuration Twogeneral type of registers to be configured in the memorycontroller First register type are set to the DRAM related parameter values,that are provided via SPD or DRAM datasheet Second register type are the Non-SPD values that are set based oncustomer’s application. For example: On-die-termination (ODT) settings for DRAM and controllerDriver impedance setting for DRAM and controllerClock adjust, write data delay, Cast to Preamble Override (CPO)2T or 3T timingBurst type selection (fixed or on-fly burst chop mode)Write-leveling start value (WRLVL START)Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM31
What Can We Adjust to Optimize the Timing? 1)CLK ADJUST 2) WR DATA DELAY 3) CPO 4) 2T EN, 3T EN 5) WRLVL EN 6) Burst chop modeFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM32
CLK ADJUST & WR DATA DELAYInternal ClockMemClk (CLK ADJUST 0)CLK ADJUST 1/2MemClk (CLK ADJUST 1/2)Cmd/Addr BusWRITEWR LAT (CASL AL -1 ) 3DQS (WR DATA DELAY 0)DQ (WR DATA DELAY 0)Tdqss 1/4 cycleWR DATA DELAY 1/2DQS (WR DATA DELAY 1/2)DQ (WR DATA DELAY 1/2)Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM33
Pitfalls / Debug Tips - Clock Adjust Addr/Cmdare always launched from the same location, memory clock isshifted with DDR SDRAM CLK CNTL[CLK ADJUST] Used to meet setup/hold for Addr/Cmd Useeye. a scope to verify that clock is centered inside of the Addr/Cmd validLook at heavily loaded signal (/RAS, /CAS, /WE, Addr, BA)Look at lightly loaded signal (/CS, ODT, CKE)Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM34
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Pitfalls / Debug Tips – Write Data Delay Controlled Used to meet tDQSS timing requirementsIn addition to compensating for CLK ADJUST setting Verify via TIMING CFG 2[WR DATA DELAY]using a scopeMust be measured after DDR SDRAM CLK CNTL[CLK ADJUST] hasbeen optimized Erroneousvalues may cause failures on writes to DRAMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM40
Pitfalls / Debug Tips - CAS to Preamble Set Usevia TIMING CFG 2[CPO]application note AN2583 section 4.2 to calculate Mustbe calculated after DDR SDRAM CLK CNTL[CLK ADJUST]has been optimized Use the center value if more than one valid CPO available.Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM41
2T/3T Timing PutsAddr/Cmd signals on the bus for 2 or 3 clock cycles instead of 1 Does not affect Control signals Whento use?Two dual-rank unbuffered DIMMs 36 loads on Addr/Cmd lines Typicallynot required for:One dual-rank unbuffered DIMM 18 loads on Addr/Cmd lines When not to use?Registered DIMMsFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM42
PowerQUICC DDR ControllersPitfalls / Debug TipsFreescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product orservice names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM43
Pitfalls / Debug Tips - DDR Type POR ConfigurationFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM44
Pitfalls / Debug Tips - ECC and DDR Error Registers ECCshould be enabled if possibleDDR SDRAM CFG[ECC EN] enables ECC DDR SDRAM CFG 2[D INIT] initializes data and ECC in DRAM If ECC cannot be enabled, it may be more difficult to detect DDRgenerated errors ERR DETECTregister should be checked for DDR errorsACE – Automatic calibration error MBE – Multi-bit ECC error SBE – Single-bit ECC error MSE – Memory select error Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM45
Pitfalls / Debug Tips - CAS Latency / Write Latency / Additive Latency Programwrite latency based on DRAM typeDDR1 - Write latency 1 DRAM cycle DDR2 - Write latency (Read latency – 1) DRAM cycles DDR3 - Write latency CWL Programming CAS latency too high can degrade performanceCheck DRAM datasheet based on frequency used and specific DRAMdevice WhenODT is used, other rules must be followed to allow ODT toassert early enoughDDR2: Write latency additive latency 3 cycles DDR3: TIMING CFG 5 [WODT ON], [WODT OFF] WL-1 cycles forfixed or fly-by burst chop Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM46
Pitfalls / Debug Tips - DDR Mode Registers Valuesprogrammed into DDR mode registers must match DDRcontroller configuration registersCAS latency Burst length Write recovery Not a straight decode in Mode RegisterActive powerdown exit time Additive latency Differential DQS enable DLLreset and OCD calibration fields are controlled automatically bythe DDR controllerFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM47
*Pitfalls / Debug Tips - Programming twtr, trrd, and trtp Usecaution when calculating: TIMING CFG 1[WRTORD] (twtr) TIMING CFG 1[ACTTOACT] (trrd) TIMING CFG 2[RD TO PRE] (trtp)DDR2: Minimum value for each parameter is 2 DRAM clocks DDR3: Minimum value for each parameter is 4 DRAM clocks Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM48
Pitfalls / Debug Tips - 200 us Delay 200μs for DDR2 and 512 us for DDR3 must pass between stableclocks and CKE assertion Clocksare stable after DDR SDRAM CLK CNTL[CLK ADJUST] isprogrammed and any chip select has been enabled viaCSn CONFIG[CS n EN] CKEis asserted after DDR SDRAM CFG[MEM EN] is set Softwaremust provide delay between these 2 stepsFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM49
ReferencesFreescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product orservice names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM50
Useful References Books: DRAM Circuit Design: A Tutorial, Brent Keeth and R. Jacob Baker, IEEE Press, 2001 Freescale AppNotes: AN2582 Hardware and Layout Design Considerations for DDR Memory Interfaces AN2910 Hardware and Layout Design Considerations for DDR2 Memory Interfaces AN2583 Programming the PowerQUICC III / PowerQUICC II Pro DDR SDRAM Controller AN3369 PowerQUICC DDR2 SDRAM Controller Register Setting Considerations Micron AppNotes: TN-46-05 General DDR SDRAM Functionality TN-47-02 DDR2 Offers New Features and Functionality TN-41-02 DDR3 ZQ calibration JEDEC Specs:JESD79E Double Data Rate (DDR) SDRAM SpecificationJESD79-2B DDR2 SDRAM SpecificationJESD79-3A DDR3 SDRAM SpecificationFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM51
Q&A Thankyou for attending this presentation. We’ll now take a fewmoments for the audience’s questions and then we’ll begin thequestion and answer session.Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product orservice names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.TM52
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DDR Basics, Register Configurations & Pitfalls July, 2009 Mazyar Razzaz, Applications Engineer. Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc.
DDR Configuration Registers are declared in asm-arm\arch-m2s\ddr.h file. This includes DDR Controller Registers, DDR PHY Configuration Registers, and FIC-64 registers. Refer to asm-arm\arch-m2s\ddr.h file for complete structure of DDR Configuration Registers. Functions DDR initialization function is defined in board\emcraft\m2s-som\board.c file.
DUA Overview FPGA Server DDR QSFP App App LTL DDR access FPGA Connect Host DMA DDR PCIe Gen3 App App LTL DDR access FPGA Connect Host DMA Datacenter networking fabric QSFP FPGA DDR access Connect Host PCIe Gen3 PCIe Gen3 CPU DUA DUA Intra-server networking fabric DUA is an “IP layer” ③ ② ① ④ Efficient Routing Direct resource access .
ZQ calibration is done in both i.MX53 DDR PHY and the DDR device. Control bits ZQ_MODE[1:0] should be set in order to determine the activation events of the local and distant ZQ resistors. 7.2.2 One-Time Forced Hardware ZQ Calibration Both local i.MX53 DDR PHY and the DDR device ZQ calibrations can be performed as a one-time event,
ddr dq0-7 _b ddr phy ca/clk ddr dq0-7 _a ddr dq8-15 _a ddr ecc dq0-7 usb2 host2 host3 vccio6 pcie2.0 sata2 qsgmii_m1 usb3_host1 sata1 qsgmii_m0 usb3_otg0 sata0 tmds 24mhz 4 lane mipi dsi or lvds usb2.0 host2 usb2.0 host3 wifi/bt 802.11 a /b g n ac bt5.0 edp port 2.4/5ghz rgmii1_m0 sdmmc2_m0 uart8_m0 g i g a p hy r j-45 rgmii0 cec hdmi_i2c hpd .
Source: Page 38 of ChipScale Review Sept/Oct 2013, by Dr. Dev Gupta (see pointer above) LP DDR 1 DDR 3L LP DDR 2 LP DDR 3 Wide I/O Mobile Memory Type
Mobile Strategy. 6. Browser Specific Configurations. 6. Apple Safari Browser Configurations. 6. Google Chrome Browser Configurations. 7. Microsoft Edge Chromium-Based Browser Configurations. 8. Microsoft Edge HTML-Based Browser Configurations. 9. Microsoft Internet Explorer \(IE\) Browser Configurations. 9. Mozilla Firefox Browser .
The Memory Interface Generator (MIG) 1.5 tool generates DDRII SRAM, DDR SDRAM, DDR2 SDRAM, QDRII SRAM, and RLDRAM II interfaces for Virtex -4 FPGAs. It also generates DDR and DDR2 SDRAM interfaces for Spartan -3 FPGAs and DDR SDRAM interfaces for Spartan-3E FPGAs.
Service Level Agreement For any other Business Broadband Service, We’ll aim to restore the Service within 24 hours of you reporting the Fault. Where we need a site visit to resolve a Fault, we only do site visits on Working Days during Working Hours (please see definitions at the end of the document). Service Credits are granted at our discretion date by which Exclusions (applicable to all .
