MFRC522 Standard Performance MIFARE And NTAG Frontend

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8. Functional descriptionThe MFRC522 transmission module supports the Read/Write mode forISO/IEC 14443 A/MIFARE using various transfer speeds and modulation protocols.BATTERYMFRC522ISO/IEC 14443 A CARDMICROCONTROLLERcontactless cardreader/writerFig 4.001aak583MFRC522 Read/Write modeThe physical level communication is shown in Figure 5.(1)ISO/IEC 14443 AREADERISO/IEC 14443 A CARD(2)MFRC522001aak584(1) Reader to card 100 % ASK, Miller encoded, transfer speed 106 kBd to 848 kBd.(2) Card to reader subcarrier load modulation, Manchester encoded or BPSK, transfer speed 106 kBdto 848 kBd.Fig 5.ISO/IEC 14443 A/MIFARE Read/Write mode communication diagramThe physical parameters are described in Table 4.Table 4.Communication overview for ISO/IEC 14443 A/MIFARE reader/writerCommunicationdirectionSignal typeReader to card (senddata from theMFRC522 to a card)Card to reader(MFRC522 receivesdata from a card)Transfer speed106 kBd212 kBd424 kBd848 kBdreader sidemodulation100 % ASK100 % ASK100 % ASK100 % ASKbit encodingmodified Millerencodingmodified Millerencodingmodified Millerencodingmodified Millerencodingbit length128 (13.56 s)64 (13.56 s)32 (13.56 s)16 (13.56 s)card sidemodulationsubcarrier loadmodulationsubcarrier loadmodulationsubcarrier loadmodulationsubcarrier loadmodulationsubcarrierfrequency13.56 MHz / 1613.56 MHz / 1613.56 MHz / 1613.56 MHz / 16bit encodingManchesterencodingBPSKBPSKBPSKThe MFRC522’s contactless UART and dedicated external host must manage thecomplete ISO/IEC 14443 A/MIFARE protocol. Figure 6 shows the data coding andframing according to ISO/IEC 14443 A/MIFARE.MFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.8 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontendISO/IEC 14443 A framing at 106 kBdstart8-bit data8-bit dataoddparitystart bit is 18-bit dataoddparityoddparityISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBdstart8-bit dataevenparity8-bit dataoddparitystart bit is 08-bit dataoddparityburst of 32subcarrier clockseven parity at theend of the frame001aak585Fig 6.Data coding and framing according to ISO/IEC 14443 AThe internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 Apart 3 and handles parity generation internally according to the transfer speed. Automaticparity generation can be switched off using the MfRxReg register’s ParityDisable bit.8.1 Digital interfaces8.1.1 Automatic microcontroller interface detectionThe MFRC522 supports direct interfacing of hosts using SPI, I2C-bus or serial UARTinterfaces. The MFRC522 resets its interface and checks the current host interface typeautomatically after performing a power-on or hard reset. The MFRC522 identifies the hostinterface by sensing the logic levels on the control pins after the reset phase. This is doneusing a combination of fixed pin connections. Table 5 shows the different connectionconfigurations.Table 5.PinMFRC522Product data sheetCOMPANY PUBLICConnection protocol for detecting different interface typesInterface typeUART (input)SPI (output)I2C-bus (I/O)SDARXNSSSDAI2C001EA01EAD7TXMISOSCLD6MXMOSIADR 0D5DTRQSCKADR 1D4--ADR 2D3--ADR 3D2--ADR 4D1--ADR 5All information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.9 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8.1.2 Serial Peripheral InterfaceA serial peripheral interface (SPI compatible) is supported to enable high-speedcommunication to the host. The interface can handle data speeds up to 10 Mbit/s. Whencommunicating with a host, the MFRC522 acts as a slave, receiving data from theexternal host for register settings, sending and receiving data relevant for RF interfacecommunication.An interface compatible with SPI enables high-speed serial communication between theMFRC522 and a microcontroller. The implemented interface is in accordance with the SPIstandard.The timing specification is given in Section 14.1 on page 78.MFRC522SCKSCKMOSIMOSIMISOMISONSSNSS001aak586Fig 7.SPI connection to hostThe MFRC522 acts as a slave during SPI communication. The SPI clock signal SCK mustbe generated by the master. Data communication from the master to the slave uses theMOSI line. The MISO line is used to send data from the MFRC522 to the master.Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSIand MISO lines must be stable on the rising edge of the clock and can be changed on thefalling edge. Data is provided by the MFRC522 on the falling clock edge and is stableduring the rising clock edge.8.1.2.1SPI read dataReading data using SPI requires the byte order shown in Table 6 to be used. It is possibleto read out up to n-data bytes.The first byte sent defines both the mode and the address.Table 6.MOSI and MISO byte orderLineByte 0Byte 1Byte 2ToByte nByte n 1MOSIaddress 0address 1address 2.address n00MISOX[1]data 0data 1.data n 1data n[1]X Do not care.Remark: The MSB must be sent first.MFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.10 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8.1.2.2SPI write dataTo write data to the MFRC522 using SPI requires the byte order shown in Table 7. It ispossible to write up to n data bytes by only sending one address byte.The first send byte defines both the mode and the address byte.Table 7.MOSI and MISO byte orderLineByte 0Byte 1Byte 2MOSIaddress 0data 0MISOX[1]X[1][1]ToByte nByte n 1data 1.data n 1data nX[1].X[1]X[1]X Do not care.Remark: The MSB must be sent first.8.1.2.3SPI address byteThe address byte must meet the following format.The MSB of the first byte defines the mode used. To read data from the MFRC522 theMSB is set to logic 1. To write data to the MFRC522 the MSB must be set to logic 0. Bits 6to 1 define the address and the LSB is set to logic 0.Table 8.Address byte 0 register; address MOSI7 (MSB)651 read0 writeaddress43210 (LSB)08.1.3 UART interface8.1.3.1Connection to a hostMFRC522RXTXDTRQMXRXTXDTRQMX001aak587Fig 8.UART connection to microcontrollersRemark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’sRS232LineEn bit.MFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.11 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8.1.3.2Selectable UART transfer speedsThe internal UART interface is compatible with an RS232 serial interface.The default transfer speed is 9.6 kBd. To change the transfer speed, the host controllermust write a value for the new transfer speed to the SerialSpeedReg register. BitsBR T0[2:0] and BR T1[4:0] define the factors for setting the transfer speed in theSerialSpeedReg register.The BR T0[2:0] and BR T1[4:0] settings are described in Table 9. Examples of differenttransfer speeds and the relevant register settings are given in Table 10.Table 9.BR T0 and BR T1 settingsBR TnBit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7BR T0 factor11248163264BR T1 range1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64Table 10.Selectable UART transfer speedsTransfer speed (kBd)DecimalHexadecimalTransfer speed accuracy(%)[1]7.2250FAh 0.259.6235EBh0.3214.4218DAh 0.2519.2203CBh0.3238.4171ABh0.3257.61549Ah 0.25115.21227Ah 0.2512811674h 0.06230.4905Ah 0.25460.8583Ah 0.25921.6281Ch1.451228.82115h0.32[1]SerialSpeedReg valueThe resulting transfer speed error is less than 1.5 % for all described transfer speeds.The selectable transfer speeds shown in Table 10 are calculated according to thefollowing equations:If BR T0[2:0] 0:627.12 10transfer speed ------------------------------- BR T0 1 (1)If BR T0[2:0] 0: 27.12 10 6 transfer speed ----------------------------------- BR T1 33 --------------------------------- 2 BR T0 – 1 (2)Remark: Transfer speeds above 1228.8 kBd are not supported.MFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.12 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8.1.3.3UART framingTable 11.UART framingBitLengthValueStart1-bit0Data8 bitsdataStop1-bit1Remark: The LSB for data and address bytes must be sent first. No parity bit is usedduring transmission.Read data: To read data using the UART interface, the flow shown in Table 12 must beused. The first byte sent defines both the mode and the address.Table 12.Read data byte orderPinByte 0Byte 1RX (pin 24)address-TX (pin 31)-data D5D6D7SOMXDTRQ001aak588(1) Reserved.Fig 9.UART read data timing diagramWrite data: To write data to the MFRC522 using the UART interface, the structure shownin Table 13 must be used.The first byte sent defines both the mode and the address.MFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.13 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontendTable 13.MFRC522Product data sheetCOMPANY PUBLICWrite data byte orderPinByte 0Byte 1RX (pin 24)address 0data 0TX (pin 31)-address 0All information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.14 of 95

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxNXP SemiconductorsMFRC522Product data sheetCOMPANY PUBLICDATAADDRESSRXSAA0A1A2A3A4A5(1)R/W W SODTRQ001aak589(1) Reserved.Fig 10. UART write data timing diagramRemark: The data byte can be sent directly after the address byte on pin RX.Address byte: The address byte has to meet the following format:The MSB of the first byte sets the mode used. To read data from the MFRC522, the MSB is set to logic 1. To write data to theMFRC522 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 14.MFRC522 NXP Semiconductors N.V. 2016. All rights reserved.15 of 95Standard performance MIFARE and NTAG frontendAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139MX

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontendTable 14.Address byte 0 register; address MOSI7 (MSB)651 read0 writereservedaddress43210 (LSB)8.1.4 I2C-bus interfaceAn I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial businterface to the host. The I2C-bus interface is implemented according toNXP Semiconductors’ I2C-bus interface specification, rev. 2.1, January 2000. Theinterface can only act in Slave mode. Therefore the MFRC522 does not implement clockgeneration or access SCLMICROCONTROLLERI2CCONFIGURATIONWIRINGEAADR [5:0]001aak590Fig 11. I2C-bus interfaceThe MFRC522 can act either as a slave receiver or slave transmitter in Standard mode,Fast mode and High-speed mode.SDA is a bidirectional line connected to a positive supply voltage using a current source ora pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. TheMFRC522 has a 3-state output stage to perform the wired-AND function. Data on theI2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDAas defined in the I2C-bus interface specification.See Table 155 on page 79 for timing requirements.MFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.16 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8.1.4.1Data validityData on the SDA line must be stable during the HIGH clock period. The HIGH or LOWstate of the data line must only change when the clock signal on SCL is LOW.SDASCLdata linestable;data validchangeof dataallowedmbc621Fig 12. Bit transfer on the I2C-bus8.1.4.2START and STOP conditionsTo manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditionsare defined. A START condition is defined with a HIGH-to-LOW transition on the SDA line whileSCL is HIGH. A STOP condition is defined with a LOW-to-HIGH transition on the SDA line whileSCL is HIGH.The I2C-bus master always generates the START and STOP conditions. The bus is busyafter the START condition. The bus is free again a certain time after the STOP condition.The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,S is used as a generic term to represent both the START (S) and repeated START (Sr)conditions.SDASDASCLSCLSPSTART conditionSTOP conditionmbc622Fig 13. START and STOP conditions8.1.4.3Byte formatEach byte must be followed by an acknowledge bit. Data is transferred with the MSB first;see Figure 16. The number of transmitted bytes during one data transfer is unrestrictedbut must meet the read/write cycle format.MFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.17 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8.1.4.4AcknowledgeAn acknowledge must be sent at the end of one data byte. The acknowledge-related clockpulse is generated by the master. The transmitter of data, either master or slave, releasesthe SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down theSDA line during the acknowledge clock pulse so that it remains stable LOW during theHIGH period of this clock pulse.The master can then generate either a STOP (P) condition to stop the transfer or arepeated START (Sr) condition to start a new transfer.A master-receiver indicates the end of data to the slave-transmitter by not generating anacknowledge on the last byte that was clocked out by the slave. The slave-transmitterreleases the data line to allow the master to generate a STOP (P) or repeated START (Sr)condition.data outputby transmitternot acknowledgedata outputby receiveracknowledgeSCL frommaster1289Sclock pulse foracknowledgementSTARTconditionmbc602Fig 14. Acknowledge on the I2C-busPSDAacknowledgementsignal from slaveMSBacknowledgementsignal from receiverSrbyte complete,interrupt within slaveclock line held LOW whileinterrupts are servicedSCLSorSr1278912ACK3-89ACKSrorPSTOP orrepeated STARTconditionSTART orrepeated STARTconditionmsc608Fig 15. Data transfer on the I2C-busMFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.18 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8.1.4.57-Bit addressingDuring the I2C-bus address procedure, the first byte after the START condition is used todetermine which slave will be selected by the master.Several address numbers are reserved. During device configuration, the designer mustensure that collisions with these reserved addresses cannot occur. Check the I2C-busspecification for a complete list of reserved addresses.The I2C-bus address specification is dependent on the definition of pin EA. Immediatelyafter releasing pin NRSTPD or after a power-on reset, the device defines the I2C-busaddress according to pin EA.If pin EA is set LOW, the upper 4 bits of the device bus address are reserved byNXP Semiconductors and set to 0101b for all MFRC522 devices. The remaining 3 bits(ADR 0, ADR 1, ADR 2) of the slave address can be freely configured by the customerto prevent collisions with other I2C-bus devices.If pin EA is set HIGH, ADR 0 to ADR 5 can be completely specified at the external pinsaccording to Table 5 on page 9. ADR 6 is always set to logic 0.In both modes, the external address coding is latched immediately after releasing thereset condition. Further changes at the used pins are not taken into consideration.Depending on the external wiring, the I2C-bus address pins can be used for test signaloutputs.MSBLSBbit 6bit 5bit 4bit 3bit 2slave addressbit 1bit 0R/W001aak591Fig 16. First byte following the START procedure8.1.4.6Register write accessTo write data from the host controller using the I2C-bus to a specific register in theMFRC522 the following frame format must be used. The first byte of a frame indicates the device address according to the I2C-bus rules. The second byte indicates the register address followed by up to n-data bytes.In one frame all data bytes are written to the same register address. This enables fastFIFO buffer access. The Read/Write (R/W) bit is set to logic 0.MFRC522Product data sheetCOMPANY PUBLICAll information provided in this document is subject to legal disclaimers.Rev. 3.9 — 27 April 2016112139 NXP Semiconductors N.V. 2016. All rights reserved.19 of 95

MFRC522NXP SemiconductorsStandard performance MIFARE and NTAG frontend8.1.4.7Register read accessTo read out data from a specific register address in the MFRC522, the host controller mustuse the following procedure: Firstly, a write access to the specific register address must be performed as indicatedin the frame that follows The first byte of a frame indicates the device address according to the I2C-bus rules The second byte indicates the register address

Product data sheet COMPANY PUBLIC Rev. 3.9 — 27 April 2016 112139 3 of 95 NXP Semiconductors MFRC522 Standard performance MIFARE and NTAG frontend [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [2]