Zynq Migration Guide: Zynq-7000 SoC To Zynq UltraScale .

2y ago
26 Views
3 Downloads
2.80 MB
156 Pages
Last View : 7d ago
Last Download : 4m ago
Upload by : River Barajas
Transcription

Zynq Migration GuideZynq-7000 SoC to ZynqUltraScale MPSoC DevicesUG1213 (v3.0) November 22, 2019

Revision HistoryThe following table shows the revision history for this document.DateVersionRevision11/22/20193.0Updated for Vitis software platform flows.11/30/20162.0Updated content in About this Guide.09/21/20161.0Initial Xilinx release.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback2

Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Chapter 1: IntroductionAbout this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Pre-Requisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Document Audience and Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Zynq Device Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Hardware Differences in Zynq Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Migration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Chapter 2: Processing UnitsProgrammer Models for Zynq Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Programming Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reset System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .System Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232834373941Chapter 3: Migrating SoftwareIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Migrating Software from Zynq-7000 SoC APU to Zynq UltraScale MPSoC APU/RPU . . . . . . . . . . 43Chapter 4: PeripheralsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UART Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SPI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gigabit Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Multiplexed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback4747515662677684933

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Chapter 5: Boot and ConfigurationBooting Option Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Boot Image Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Chapter 6: LibrariesIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Standalone BSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Appendix A: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Third-Party Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback1531531531541551551564

Chapter 1IntroductionAbout this GuideThe Zynq UltraScale MPSoC device is the successor to the Zynq -7000 SoC device. Itprovides 64-bit processor scalability while combining real-time control with soft and hardengines for graphics, video, waveform, and packet processing, to name a few.Integrating an Arm -based heterogeneous system for advanced analytics and on-chipprogrammable logic for compute task acceleration creates unlimited possibilities forapplications.This document facilitates the migration of designs from a Zynq-7000 SoC device to a ZynqUltraScale MPSoC device.The Zynq UltraScale MPSoC family has different products, based upon the followingsystem features: Application processing unit (APU): Dual or Quad-core Arm Cortex-A53 MPCore CPU frequency up to 1.5 GHzReal-time processing unit (RPU): Dual-core Arm Cortex-R5F MPCore CPU frequency up to 600 MHzGraphics processing unit (GPU): Arm Mali -400 MP2 GPU frequency up to 667 MHzZynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback5

Chapter 1: Introduction Video codec unit (VCU): Simultaneous Encode and Decode through separate cores H.264 high profile level 5.2 (4Kx2K-60) H.265 (HEVC) main, main10 profile, level 5.1, high Tier, up to 4Kx2K-60 rate 8-bit and 10-bit encoding 4:2:0 and 4:2:2 chroma samplingFor more details, see the Zynq UltraScale MPSoC Product Page [Ref 3] and the ProductAdvantages [Ref 4].Pre-RequisitesThis document assumes that you have the following qualifications: Familiarity with the Zynq-7000 SoC device Experienced with application development for a Zynq-7000 SoC device Experienced with embedded software developmentDocument Audience and ScopeThe purpose of this guide is to enable software developers and system architects to befamiliar with: Hardware features and differences between a Zynq-7000 SoC device and a ZynqUltraScale MPSoC device Porting the software application from Zynq-7000 SoC device to a Zynq UltraScale MPSoC device Interfacing peripheral configuration differences between Zynq-7000 SoC device and aZynq UltraScale MPSoC device Booting differences between the Zynq-7000 SoC device and a Zynq UltraScale MPSoCdeviceZynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback6

Chapter 1: IntroductionZynq Device ComparisonThe Zynq-7000 SoC device, built on 28 nm processing technology from TSMC, combines anindustry-standard Arm dual-core Cortex -A9 MPCore processing system with Xilinx28 nm programmable logic. This processor-centric architecture delivers a comprehensiveprocessing platform that offers developers ASIC levels of performance and powerconsumption, the ease of programmability of a microprocessor and the flexibility of a FPGA.The Zynq UltraScale MPSoC device is built on 16FinFET processing technology fromTSMC in the Arm-based multiprocessor cores. Building on the industry success of theZynq-7000 SoC device family, the new Zynq UltraScale MPSoC device architecture extendsXilinx SoC devices to enable true heterogeneous multi-processing with the right enginesfor the right tasks for smarter systems.This chapter gives the overview of the procedure involved in the migration process byhighlighting the hardware differences between the Zynq-7000 SoC device and the ZynqUltraScale MPSoC device.Hardware Differences in Zynq DevicesThe Zynq family offers the flexibility and scalability of an FPGA, while providingperformance, power, and ease of use typically associated with ASIC and ASSP chips. Boththe Zynq devices combine the Arm - based processing system (PS) with Xilinxprogrammable logic (PL). In the Zynq UltraScale MPSoC device, the Xilinx memory protection unit (XMPU)provides memory partitioning and TrustZone (TZ) protection for memory and FPDslaves. The XMPU can be configured to isolate a master or a given set of masters to aprogrammable set of address ranges. In the Zynq UltraScale MPSoC device, the Xilinx peripheral protection unit (XPPU)provides LPD peripheral isolation and inter-processor interrupt (IPI) protection. TheXPPU can be configured to permit one or more masters to access an LPD peripheralwithout knowing the address aperture of the peripheral.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback7

Chapter 1: IntroductionFor more information about XPMU and XPPU, and role of IPIs, see this link to the “PMUInterconnect” sub-section in the “Platform Management Unit” chapter of the ZynqUltraScale MPSoC Technical Reference Manual (UG1085).The following figure shows the top-level block diagram of PS in the Zynq devices.X-Ref Target - Figure 1-1 ]RU 47%49(YEP GSVI %VQ 'SVXI\ % IRIVEP 'SRRIGXMZMX] MK) 97& '%2 9%68 74- 574- 236 2%2( 7( I11'1IQSV]((6 3'17]WXIQ *YRGXMSRW(1% 8MQIV ;(8 6IWIXW 'PSGOMRK (IFYK ]RU 9PXVE7GEPI 147S' 47 %495YEH GSVI %VQ 'SVXI\ % (YEP GSVI MR ' HIZMGIW649(YEP GSVI %VQ 'SVXI\ 6 * 49%VQ 1EPM 14 1IQSV]((6 ERH 3'1 [MXL )''4PEXJSVQ QEREKIQIRX 9RMX'SRJMKYVEXMSR ERH 7IGYVMX] 9RMX IRIVEP 'SRRIGXMZMX] MK) 97& '%2 9%68 74- 574- 236 2%2( 7( I11'7]WXIQ *YRGXMSRW(1% 8MQIV ;(8 6IWIXW 'PSGOMRK (IFYK,MKL 7TIIH 'SRRIGXMZMX](MWTPE] 4SVX Z E 97& 7%8% 4'-I 47 86Figure 1-1:Top-Level PS Diagram for the Zynq DevicesThe PS of the Zynq-7000 SoC device comprises: An application processing unit (APU) Memory interfaces System control Central interconnect I/O peripheralsThe PS of Zynq UltraScale MPSoC device combines a heterogeneous processing systemcomprising the following: Application processing unit (APU) Real-time processing unit (RPU)Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback8

Chapter 1: Introduction Graphics processing unit (GPU) with memory interfaces System control Central interconnect I/O peripheralsProcessing System DifferencesThe Zynq UltraScale MPSoC devices also provides the following units to enhance therun-time security of a software. Xilinx Memory Protection Unit (XMPU) Xilinx Peripheral Protection Unit (XPPU) System Memory Management Unit (SMMU)The following table summarizes the PS architectural differences between the Zynq devices.Table 1-1:Processor System Block ComparisonPS Block NameApplication Processing UnitReal-time Processing UnitZynq-7000 SoC Dual core Arm Cortex-A932-bit processor,Zynq UltraScale MPSoC Includes acceleratorcoherency port. Dual and Quad coreCortex-A53 64-bit processors.Supports four exceptionlayers. Arm Instruction set (Armv7a) Arm v7-R instruction set. Includes acceleratorcoherency port and AXIcoherency extension. Dynamic branch prediction. Redundant CPU logic for faultdetection. AXI interface to PL for lowlatency applications.Graphic Processing Unit One geometry processor. Two pixel processors- OpenGL ES 1.1 and 2.0support. OpenVG 1.1 Advanced anti-aliasingsupport.InterconnectMax I/O PinsZynq Migration GuideUG1213 (v3.0) November 22, 2019 Arm AMBA 3.0 interconnect Arm AMBA 4.0 interconnect. Switches based on ArmNIC-301 Switches based on ArmNIC-400. 128 214www.xilinx.comSend Feedback9

Chapter 1: IntroductionTable 1-1:Processor System Block Comparison (Cont’d)PS Block NameZynq-7000 SoCConfiguration Security UnitZynq UltraScale MPSoC Triple redundant processorfor controlling boot flow.- Supports secure andnon-secure boot. Includes a crypto engine thatcontains AES-GCM supports SHA-3 and RSAstandards.Power DomainsHas power domains:Has power domains: PS power domain Full-Power Domain (FPD) PL power domain Low-Power Domain (LPD) Battery Power Domain PL Power DomainPlatform Management Unit(PMU) Triple redundant processors.- Does system initializationduring boot. Power gating and retentionstates management. Sleep state management.InterruptsTimers APU handles the interruptsusing GIC pl390. APU handles the interruptsusing GIC400. GIC dispatches the interruptsto the individual CPU RPU uses GIC390. Has a 24-bit WDT Has two SWDT; one each forRPU and APU. Two 16-bit TTC Each Cortex-A9 processor hasits own private 32-bit timerand 32-bit WDT Both processors share aglobal 64-bit timer.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.com GIC takes all the interruptsand generates interrupts forthe PMU. Two 32-bit TTC for each RPUand APU. System has a Generic 64-bitcounter.Send Feedback10

Chapter 1: IntroductionTable 1-1:Processor System Block Comparison (Cont’d)PS Block NameDMA ControllerZynq-7000 SoCZynq UltraScale MPSoC Supports simple andscatter-gather mode. Has two instances of DMAcontroller: provides eight concurrentDMA channel threads Supports multi-channel dataFIFO FPD-DMA LPD-DMA Programmable number ofoutstanding transfers. Support for simple andscatter-gather mode. Support for read-only andwrite-only DMA mode. Descriptor pre-fetching, perchannel flow controlinterface.DDR Memory Controller Supports DDR2, DDR3,DDR3L, and LPDDR2. Configurable 16-bit or 32-bitdata bus. ECC support for 16-bit mode. Support for DDR3, DDR3L,DDR4, LPDDR4, up to tworanks. Dynamic scheduling tooptimize bandwidth andlatency. ECC support in 32-bit and64-bit mode Software programmablequality of service.NAND Memory Controller Complies with ONFI 1.0. Supports asynchronousmemory operating mode. Complies with ONFI 3.1specification. Supports reset logical unitnumber. ODT configuration, on-dietermination.SPI Controller Full duplex operation. Full duplex operation. Supports multi-master I/Omode. Multi-master environmentsupport Selectable master clockreference. Programmable master modeclock frequency. programmable transmissionformat.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback11

Chapter 1: IntroductionTable 1-1:Processor System Block Comparison (Cont’d)PS Block NameQuad-SPI ControllerZynq-7000 SoC Consists of a Legacy linearQuad-SPI controller.Zynq UltraScale MPSoC Consists of a Legacy linearQuad-SPI controller and anew generic Quad-SPIcontroller. Supports command queuing. Supports 4/8 bit interface. 44-bit address support on AXIin DMA mode transfer.CAN Controller Complies with ISO 11898 -1. Complies with ISO 11898 -1. CAN 2.0A, and CAN 2.0Bstandards. CAN 2.0A, and CAN 2.0Bstandards. Supports both standard(11-bit identifier) andextended (29-bit identifier)frames Supports both standard(11-bit identifier) andextended (29-bit identifier)frames. Programmable baud rategenerator. Programmable baud rategenerator. 6/7/8 data bits modemcontrol signals. 6/7/8 data bits modemcontrol signals.I2C Controller I2C bus specification version2.0 supported. I2C bus specification version2.0 supported.SD/SDIO Controller Compatible with the standardSD Host ControllerSpecification, version 2.0 PartA2. Compatible with the SD hostcontroller standardspecification version 3.00.General-purpose I/O Up to 54 GPIO signals fordevice pins routed throughthe MIO. 78 GPIO signals for devicepins.UART Controller 192 GPIO signals between thePS and PL using the EMIO.USB Controller Has two USB 2.0 controllers 288 GPIO signals betweenPS-PL interface throughEMIO. Has two USB 3.0 controllersand is backward compatiblewith USB 2.0. Provides simultaneousoperation of the USB 2.0 andUSB 3.0 interfaces only inHost mode.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback12

Chapter 1: IntroductionTable 1-1:Processor System Block Comparison (Cont’d)PS Block NameZynq-7000 SoCPS PCI ExpressZynq UltraScale MPSoC PCI Express (Specification 2.1)as part of PS.- Interlaken 100G Ethernet Block System MonitorGigabit transceiver interfaceGigabit Ethernet controller Compliant with PCIe 2.1 Compliant with PCIe 2.1 Low power gigabit transceiveris capable of up to 12.5 Gb/sline rates with flip-chippackages and up to 6.6Gb/swith bare-die flip-chippackages. USB 3.0 Compatible with the IEEE802.3-2008 standard capableof operating in either half orfull duplex mode at all three(10/100/1000 Mb/s) speeds. IEEE Std 802.3-2008compatible To access pins using MIO,each controller uses an RGMIIinterface, and access to the PLthrough the EMIO providesthe GMII interface. DisplayPort 1.2a SGMII SATA 3.1 PHY protocols. Full and half-duplex modes ofoperation RGMII/SGMII interfacesupport Jumbo frame support Automatic discard frameswith errors Programmable inter-packetgap Full-duplex flow control. The controller has a built-inDMA engine for transferringEthernet packets frommemory.SATA host controller Interface Compliant with the SATA 3.1specification. Supports 1.5G, 3G, and 6G linerates.- Compliant with the advancedhost controller interfaceversion 1.3. The controller has anembedded DMA thatfacilitates memory transfers.DisplayPort interface- Source only controller with anembedded DMA block thatsupports 1G or 2G transceiverlanes. Supports real time video andaudio input from the PL.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback13

Chapter 1: IntroductionProgrammable Logic DifferencesIn both Zynq-7000 SoC and Zynq UltraScale MPSoC devices, the PL can be on a separatepower domain from PS, enabling your design to save power by completely shutting downthe PL when the PL is not in use. The following table lists the PL differences between theZynq devices.Table 1-2:Programmable Logic ComparisonProgrammable Logic FeaturesZynq-7000 SoCZynq UltraScale MPSoCFPGA Uses Xilinx 7 series(Artix -7/Kintex -7) 28 nmtechnology. Uses UltraScale 16 nmtechnology (Kintex/Virtex UltraScale ).Block RAM Dual Port 36 Kb blocksconfigurable as dual 18 Kb, upto 72 bits wide. True dual port 36 Kb blocksconfigurable as dual 18 Kb, upto 72 bits wide Max memory is 26.5 Mb. Max memory is 70.6 Mb.250668Maximum I/O PinsUltraRAM 288 Kb dual port.- 72-bit wide error checking andcorrection.Maximum Logic Cells444K1143KDSP Slices 25 18 two's complementmultiplier 27 18 bit two’s complementmultiplier A 48-bit accumulator A 48-bit accumulator Optional pipelining, Optional pipelining Optional ALU Optional ALU Dedicated buses for cascading Dedicated buses for cascadingMaximum Memory (Mb)26.570.6PL PCI ExpressPCI Express (specification 2.1) asa block in PL PCI Express (specification 2.1)as part of the PS PCIe 4.0 Interlaken 100G Ethernet block System monitor block Video Coder/Encoded blockPL Gigabit transceiverCompliant with PCIe 2.1 Compliant with: PCIe 2.1 USB 3.0 DisplayPort 1.2a SGMII and SATA protocolsFor more information regarding resource counts, see the Xilinx Silicon Devices [Ref 2]website.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback14

Chapter 1: IntroductionSystem Address MapThis section provides a quick reference for comparing the system level address map ofZynq-7000 SoC device and the Zynq UltraScale MPSoC device. The Zynq-7000 SoC device uses 32-bit Arm Cortex-A9 processors. The Zynq UltraScale MPSoC device uses 64-bit Arm Cortex-A53 processors, allowingthe software to access a much larger address map compared to Zynq-7000 SoC device.IMPORTANT: Though the Zynq UltraScale MPSoC device supports 64-bit addressing, the lower 4GBaddress map provides apertures for all the peripherals to be able to work in 32-bit mode.The following table shows the comprehensive comparison of system level address map ofthe Zynq-7000 SoC and Zynq UltraScale MPSoC devices.Table 1-3:System-Level Address MapAddress RangeZynq-7000 SoCZynq UltraScale MPSoC0000 0000 to 0000 FFFFOCMDDR0001 0000 to 0002 FFFDDDRDDR0002 FFFE to 0003 FFFFReservedDDR0004 0000 to 0005 FFFFDDRDDR0006 0000 to 0007 FFFFReservedDDR0008 0000 to 000B FFFFDDRDDR000C 0000 to 000F FFFFReservedDDR0010 0000 to 3FFF FFFFDDRDDR4000 0000 to 7FFF FFFFPLDDR8000 0000 to 9FFF FFFFPLLPD-PL InterfaceA000 0000 to AFFF FFFFPLFPD-PL (HPM0) InterfaceB000 0000 to BFFF FFFFPLFPD-PL (HPM1) InterfaceC000 0000 to DFFF FFFFReservedQuad-SPIE000 0000 to E02F FFFFIOPLower PCIeE030 0000 to E0FF FFFFReservedLower PCIeE100 0000 to E5FF FFFFSMCLower PCIeE600 0000 to EFFF FFFFReservedLower PCIeF000 0000 to F7FF FFFFReservedReservedF800 0000 to F800 0BFFSLCRPeripheral Register MapF800 1000 to F880 FFFFPSPeripheral Register MapZynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback15

Chapter 1: IntroductionTable 1-3:System-Level Address Map (Cont’d)Address RangeZynq-7000 SoCZynq UltraScale MPSoCF890 0000 to F8F0 2FFFCPUPeripheral Register MapF8F0 3000 to FBFF FFFFReservedPeripheral Register MapFC00 0000 to FDFF FFFFQuad-SPIPeripheral Register MapFE00 0000 to FFCF FFFFReservedPeripheral Register MapFFD0 0000 to FFFB FFFFReservedPeripheral Register MapFFFC 0000 to FFCF FFFFOCMOCMFFD0 0000 to FFFD FFFFOCMCSU/PMU/TCM/OCMFFFE 0000 to FFFF FFFFReservedCSU/PMU/TCM/OCM1 0000 0000 to 3 FFFF FFFF-Reserved4 0000 0000 to 4 FFFF FFFF-PL5 0000 0000 to 6 FFFF FFFF-PCIe7 0000 0000 to F FFFF FFFF-DDR10 0000 0000 to 7F FFFF FFFF-PL80 0000 0000 to BF FFFF FFFF-PCIeC0 0000 0000 to FF FFFF FFFF-Reserved100 0000 0000 to FFF FFFF FFFF-PLPS I/O Peripheral RegistersThe following table shows the comparison of Zynq-7000 SoC and Zynq UltraScale MPSoCdevices register base addresses of all the I/O peripherals that are placed within the first 4GBspace of the Zynq UltraScale MPSoC device.Table 1-4:PS I/O Peripheral comparisonPeripheralsBase Address in Zynq-7000 SoCBase Address in ZynqUltraScale MPSoCUART Controllers 0, 10xE000 0000, 0xE000 10000xFF00 0000, 0xFF01 0000USB Controllers 0, 10xE000 2000, 0xE000 30000xFF9D 0000, 0xFF9E 0000I2C Controllers 0, 10xE000 4000, 0xE000 50000xFF02 0000, 0xFF03 0000SPI Controllers 0, 10xE000 6000, 0xE000 70000xFF04 0000, 0xFF05 0000CAN Controllers 0, 10xE000 8000, 0xE000 90000xFF06 0000, 0xFF07 0000GPIO Controller0xE000 A0000xFF0A 0000Ethernet Controllers 0, 1, 2, 30xE000 B000, 0xE000 C00, NA, NA0xFF0B 0000, 0xFF0C 0000,0xFF0D 0000, 0xFF0E 0000Quad-SPI Controller0xE000 D0000xFF0F 0000Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback16

Chapter 1: IntroductionTable 1-4:PS I/O Peripheral comparison (Cont’d)PeripheralsBase Address in Zynq-7000 SoCBase Address in ZynqUltraScale MPSoCStatic Memory Controller(SMC)0xE000 E0000xFF10 0000SDIO Controllers 0, 10xE010 0000, 0xE010 10000xFF16 0000, 0xFF17 0000SLCR RegistersThe following table compares the SLCR register base addresses of the Zynq-7000 SoCdevice and the Zynq UltraScale MPSoC device.Table 1-5:SLCR Register ComparisonDescriptionZynq-7000 SoC Base AddressSLCR write protection lock andsecurity0xF800 0000Clock control and statusReset control and statusAPU control0xF800 01000xF800 02000xF800 0300TrustZone controlZynq UltraScale MPSoC BaseAddress0xFD610000 (FPD)0xFF410000 (LPD)0xFD1A0000 (FPD)0xFF5E0000 (LPD)0xFD1A0000 (FPD)0xFF5E0000 (LPD)0xFD5C 00000xFD69 00000xF800 0400(FPD Trustzone Control)0xFF4B 0000(FPD Trustzone Control)CoreSight SoC debug control0xFEC10000(CORESIGHT A53 DBG 0)0xFED10000(CORESIGHT A53 DBG 1)0xF800 05000xFEE10000(CORESIGHT A53 DBG 2)0xFEF10000(CORESIGHT A53 DBG 3)0xFEBF0000 (CORESIGHT R5 DBG 0)0xFEBF2000 (CORESIGHT R5 DBG 1)DDR DRAM controller0xF800 06000xFD070000MIO pin configuration0xF800 07000xFF18 0000On-chip memory (OCM)control0xF800 0A00Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.com0xFF960000Send Feedback17

Chapter 1: IntroductionMiscellaneous PS RegistersThe following table lists the corresponding addresses in the Zynq device PS registers.Table 1-6:PS Register ComparisonDescriptionTriple Timer CounterZynq-7000 SoC Base AddressZynq UltraScale MPSoCBase Address(TTC 0, TTC 1, TTC 2, TTC 3)0xF800 1000, 0xF800 2000, NA,NA0xFF11 0000, 0xFF12 0000,0xFF13 0000, 0xFF14 0000System Watchdog Timer (SWDT)0xF800 50000xFF15 0000AXI HP 0 high performance AXIinterface0xF800 80000xFD38 0000AXI HP 1 high performance AXIinterface0xF800 90000xFD39 0000AXI HP 2 high performance AXIinterface0xF800 A0000xFD3A 0000AXI HP 3 high performance AXIinterface0xF800 B0000xFD3B 0000Development ToolsTo maximize system performance and enable accelerated and predictable design cycles,Xilinx provides a comprehensive set of tools for hardware and software development for theZynq-7000 SoC and Zynq UltraScale MPSoC devices.Software Development Tools Vitis Software Development Platform: This tool supports Zynq-7000 SoC devices andalso supports Zynq UltraScale MPSoC devices with additional features. The Vitissoftware development platform provides an environment for creating softwareplatforms and applications targeted for Xilinx embedded processors. It works withhardware designs created with Vivado tools and is based on the Eclipse open sourcestandard. PetaLinux Tools: This tool supports Zynq-7000 SoC devices and also supports ZynqUltraScale MPSoC devices with additional features. The PetaLinux tools offerseverything necessary to customize, build, and deploy embedded Linux solutions onXilinx processing systems. Tailored to accelerate design productivity for ZynqUltraScale MPSoC-like devices, the solution works with the Xilinx hardware designtools to facilitate the development of Linux systems for the Zynq UltraScale MPSoCdevice. See the PetaLinux Product Page [Ref 1] for more information about PetaLinux.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback18

Chapter 1: Introduction Embedded Energy Management Framework: The embedded energy managementinterface (EEMI) and the power management framework (PMF) provides APIs that aretargeted for Xilinx Zynq UltraScale MPSoC devices. This framework enables softwarerunning on different processing units (PUs) on the same device to communicate powercontrol messages through a power management controller.This controller responds to power management requests such as putting devices in tosleep mode, or removing power from an element completely.Processor Units, such as the APU, RPU, and GPU use the API for Xilpm, a Xilinx library,while the power management unit (PMU) runs the PMU firmware application (PMUFW)that contains the necessary API to successfully interact with the power control signalsfrom the processor units (PUs) and to receive and direct various power commands onhardware elements into different power states. QEMU: The quick emulator (QEMU) for Zynq UltraScale MPSoC devices provides asystem-emulation-model that runs on an Intel-compatible Linux host system.See the Zynq UltraScale MPSoC QEMU User Guide (UG1169) [Ref 12] for moreinformation about QEMU. Third-Party Tools: Many third-party tools, such as like Arm DS-5 Development Studioand Lauterbach tools, support the software development for Zynq UltraScale MPSoCdevices.Hardware Development Tools Vivado Design Suite: The Vivado Design Suite offers a new approach for ultra-highproductivity with next generation C/C and IP-based design with the new HLxeditions including HL System Edition, HL Design Edition, and HL WebPACK Edition.Migration FlowThis section explains the steps for migrating an application from a Zynq-7000 SoC device toa Zynq UltraScale MPSoC device with a flow diagram. The following figure shows the flowdiagram illustrating the steps of the migration.Zynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.comSend Feedback19

Chapter 1: IntroductionX-Ref Target - Figure 1-2Start1. Install the requireddevelopment tools2. Configure the requiredprocessors3. Configure PS/PLPeripherals4. Migrate the PL Design5. Migrate the softwareapplication to the desiredprocessor6. Generate the Boot Files7. Validate on HardwareFigure 1-2:Migration Flow1. Install the required development tools: Because the Zynq UltraScale MPSoC deviceaddresses a wide range of applications, Xilinx provides many development tools toreduce the application development cycle and thus reducing the productZynq Migration GuideUG1213 (v3.0) November 22, 2019www.xilinx.

Zynq Migration Guide 6 UG1213 (v3.0) November 22, 2019 www.xilinx.com Chapter 1:Introduction Video codec unit (VCU): Simultaneous Encode and Decode through separate cores H.264 high profile level 5.2 (4Kx2K-60) H.265 (HEVC) main, main10 profile, level 5.1, high Tier, up to 4Kx2K-60 rate 8-bit and 10-bit encoding 4:2:0 and 4:2:2 chroma sampling

Related Documents:

Zynq-7000 SoC Data Sheet: Overview DS190 (v1.11.1) July 2, 2018 www.xilinx.com Product Specification 5 Zynq-7000 Family Description The Zynq-7000 family offers the flexibility and scalability of an F

UG471, 7 Series FPGAs SelectIO Resources User Guide). The PS I/Os are described in UG585, Zynq-7000 All Programmable SoC Technical Reference Manual. Table 1-5 provides definitions for all pin types. UG865 (v1.6) March 1, 2016 (2) Flip-chip. Zynq-7000 AP SoC Packaging Guide www.xilinx.com

For more informatio n, refer to the V CCAUX_IO section of the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the Zynq-7000 SoC Technical Reference Manual (UG585). 10. See Table 12 for TMDS_33 specifications. Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics

the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 8]. The PS I/Os are described in the Zynq-7000 All Programmable SoC Technical Reference Manual (UG585) [Ref 1]. Table 1-5 provides definitions for all pin types. Zynq-7000 AP SoCs flip-chip assembly materials are manufactured using ultra-low alpha

Data Migration Planning Analysis, Solution Design and Development Mock Migration Pilot Migration Released Data Migration Active Data and User Migration Inactive Data Migration Post Migration Activities Small Bang The details for each step include: Data Migration Planing - Develop the migration strategy and approach, and define the scope,

Migration overview In the context of Migration Manager, migration is the process of promoting . A migration group can be either internal or user-defined. Internal migration groups are included with the product and are linked to other logically related migration groups called dependencies. You cannot modify internal migration

A New Migration Testing Strategy Pre-Migration Testing The concept of pre-migration testing is not often covered during migration planning. The professionals involved in migration planning are not much aware of comprehensive pre-migration testing and the value it can add to a migration and particularly those migrations that are considered complex.

Tourism and Hospitality Terms published in 1996 according to which Cultural tourism: General term referring to leisure trav el motivated by one or more aspects of the culture of a particular area. ('Dictionary of Travel, Tour ism and Hospitality Terms', 1996). One of the most diverse and specific definitions from the 1990s is provided by ICOMOS (International Scientific Committee on Cultural .