EE 109 Unit 13 –MIPS Instruction Set
12EE 109 Unit 13 – MIPSInstruction SetArchitecting a vocabulary for the HWINSTRUCTION SET OVERVIEW3Instruction Set Architecture (ISA) Defines the of the processorand memory system Instruction set is the the HW canunderstand and the SW is composed with 2 approaches– instruction set computer Large, rich vocabulary More work per instruction but slower HW– instruction set computer Small, basic, but sufficient vocabulary Less work per instruction but faster HW4Components of an ISA1. and Address Size– 8-, 16-, 32-, 64-bit2. Which instructions does the processor support– SUBtract instruc.vs.NEGate ADD instrucs.3. of instructions– How is the operation and operands represented with 1’sand 0’s4. accessible to the instructions– Faster than accessing data from memory5. Addressing Modes– How instructions can specify location of data operands
5General Instruction Format IssuesHistoric Progression of Data Size & RegistersProcessorYearTrans.CountData 5/’89275K/1.18M328Pentium19933.1M32 8Pentium 4200042M32 128Core 2 Duo2006291M64 1286-core Core i720112.27B64 128MIPS1999var.32326 Instructions must specify three things:–– Source operands Usually 2 source operands (e.g. X Y)– Example: ADD 8, 9, 10 ( 8 9 10 where Register) Binary (machine-code) representation broken intofields of bits for each partOpCodeSrc. 1Src. 2Dest.Shift th. 9 10 8UnusedAdd7Historical Instruction Formats Different instruction sets specify these differently– 3 operand instruction set (MIPS, PPC, ARM) Similar to example on previous page Format: ADD DST, SRC1, SRC2 (DST SRC1 SRC2)– 2 operand instructions (Intel / Motorola 68K) Second operand doubles as source and destination Format: ADD SRC1, S2/D(S2/D SRC1 S2/D)– 1 operand instructions (Old Intel FP, Low-End Embedded) Implicit operand to every instruction usually known as theAccumulator (or ACC) register Format: ADD SRC1(ACC ACC SRC1)8Historical Instruction Format Examples Consider the pros and cons of each format when performing the set ofoperations– F X Y–Z– G A B Simple embedded computers often use single operand format– Smaller data size (8-bit or 16-bit machines) means limited instruc. size Modern, high performance processors use 2- and 3-operand formatsSingle-OperandLOADXADDYSUBZSTORE FLOADAADDBSTORE G( ) Smaller size to encode eachinstruction(-) Higher instruction count toload and store ACC mpromise of two extremesThree-OperandADDSUBADDF,X,YF,F,ZG,A,B( ) More natural program style( ) Smaller instruction count(-) Larger size to encode eachinstruction
910MIPS Instruction Format operand format– Most ALU instructions use 3 registers astheir operands– All operations are performed on entire 32bits (no size distinction)– Example: ADD t0, t1, t2Which Instructions In this class we'll focus on assembly to do the followingtasks (shown with the corresponding MIPS assemblymnemonics)Load/Store ArchitectureProc.Mem.– Load variables (data) from memory (or I/O) [LW,LH,LB]– Perform arithmetic, logical, and shift instructions in the CPU[ADD,SUB,AND,OR,SLL,SRL,SRA]– Store variables (data) back to memory after computation iscomplete [SW, SH, SB]– Compare data [SLT]– "Branch" to other code (to implement if and loops)[BEQ,BNE,J]– Call subroutines/functions [JAL, JR]1.) Load operands to proc. registers architecture– Load (read) data values from memory into aregister– Perform operations on registers– Store (write) data values back to memory– Different load/store instructions fordifferent operand sizes (i.e. byte, half, word)Proc.Mem.2.) Proc. Performs operation usingregister valuesProc.Mem.3.) Store results back to memory1112MIPS ISA Styleinternal / external data size–– Registers and ALU are 32-bits wideMemory bus is logically 32-bits wide (though may be physicallywider)Registers– MIPS INSTRUCTION OVERVIEW– General Purpose Registers (GPR’s)For integer and address valuesA few are used for specific tasks/values32 Floating point registersFixed size instructions–––All instructions encoded as a single -bit wordThree operand instruction format (dest, src1, src2)Load/store architecture (all data operands must be in registers andthus loaded from and stored to memory explicitly)
13MIPS GPR’s14MIPS Programmer-Visible RegistersAssembler NameReg. NumberDescription zero 0Constant 0 value at 1Assembler temporary v0- v1 2- 3Procedure return values or expressionevaluation a0- a3 4- 7Arguments/parameters t0- t7 8- 15Temporaries s0- s7 16- 23Saved Temporaries t8- t9 24- 25Temporaries k0- k1 26- 27Reserved for OS kernel gp 28Global Pointer (Global and staticvariables/data) sp 29Stack Pointer fp 30Frame Pointer ra 31Return address for current procedure General Purpose Registers(GPR’s)GPR’s 0 - 31– Hold data operands oraddresses (pointers) to datastored in memory Special Purpose Registers– : (32-bits) Holds the address of the nextinstruction to be fetched frommemory & executed32-bitsPC:– HI: Hi-Half Reg. (32-bits) For MUL, holds 32 MSB’s ofresult. For DIV, holds 32-bitremainderRecall multiplying two 32-bitnumbers yields a 64-bit resultHI:– LO: Lo-Half Reg. (32-bits)LO: For MUL, holds 32 LSB’s ofresult. For DIV, holds 32-bitquotientMIPS CoreSpecial Purpose RegistersAvoid using the yellow (highlighted) registers for anything other than its stated use1516MIPS Programmer-Visible Registers MIPS puts registers meant to storerelated data into logically separateareas of the processor known as aGPR’s f0 - f31 0 - 31– Special instructions are requiredto access these registers Coprocessor 0 Registers– Status Register Holds various control bits forprocessor modes, handlinginterrupts, etc.– Cause Register32-bitsPC: Holds information about exception(error) conditionsStatus: Coprocessor 1 Registers– Floating-point registers– Can be used for single or doubleprecision (i.e. at least 64-bitswides)64-bits or moreCoprocessor 1 –Floating-point Regs.HI:LO:Cause:Coprocessor 0 –Status & Control RegsMIPS CoreSpecial Purpose RegistersInstruction Format 32-bit Fixed Size Instructions broken into 3 types (R-, I-, and J-)based on which bits – Arithmetic/Logicinstructions– 3 register operandsor shift amount – Use for data transfer,branches, etc.– 2 registers 16-bit const.6-bits-Typeopcodeadd 5, 7, 8 0000006-bits-Typeopcodelw 18, -4( 3) 1000116-bits-Typeopcodej 0x0400018 0000105-bits5-bits5-bitsrs (src1) rt (src2) rd 0010000016-bitsrs (src1) rt (src/dst)000115-bitsshamt10010immediate1111 1111 1111 110026-bitsJump address0000 0100 0000 0000 0000 0001 10 – 26-bit jump address– We'll cover this laterEach type uses portions of the instruction to "code" certain aspects ofthe instruction. But they all start with an opcode that helps determinewhich type will be used.
1718R-Type Instructions Format6-bits5-bitsopcode5-bits5-bitsrs (src1) rt (src2) rd (dest)5-bits6-bitsshamtfunction– rs, rt, rd are 5-bit fields for register numbers– shamt shift amount and is used for shift instructionsindicating # of places to shift bits– opcode and func identify actual operation (e.g. ADD, SUB)Performing Arithmetic, Logic, and Shift OperationsIMPORTANT R-TYPE INSTRUCTIONS Example:– ADD 5, 24, 00000Arith. Inst. 24 17 5unusedADD1920Logical OperationsR-Type Arithmetic/Logic InstructionsC operatorAssemblyNotes ADD Rd, Rs, Rtd destination, s src1, t src2-SUB Rd, Rs, RtOrder: R[s] – R[t]. SUBU for unsigned*MULT Rs, RtMULTU Rs, RtResult in HI/LO. Use mfhi and mfloinstruction to move results*MUL Rd, Rs, RtIf multiply won’t overflow 32-bit result/DIV Rs, RtDIVU Rs, RtR[s] / R[t].Remainder in HI, quotient in LO Should already be familiar with (sick of) these! Logic operations are usually performed on a pair of bitsX1X2ANDX1X2ORX1X2XORX1NOT0000000000110&AND Rd, Rs, Rt010011011 OR Rd, Rs, Rt100101101 XOR Rd, Rs, Rt ( )NOR Rd, Rs, RtCan be used for bitwise-NOT ( )111111110 SLL Rd, Rs, shamtSLLV Rd, Rs, RtShifts R[s] left by shamt (shiftamount) or R[t] bits (signed)SRA Rd, Rs, shamtSRAV Rd, Rs, RtShifts R[s] right by shamt or R[t] bitsreplicating sign bit to maintain sign (unsigned)SRL Rd, Rs, shamtSRLV Rd, Rs, RtShifts R[s] left by shamt or R[t] bitsshifting in 0’sSLT Rd, Rs, RtSLTU Rd, Rs, RtOrder: R[s] – R[t]. Sets R[d] 1 if R[s] R[t], 0 otherwise , , , AND – Output istrue if both inputsare true0 AND x 01 AND x xx AND x xOR – Output is trueif any input is true0 OR x x1 OR x 1x OR x xXOR – Output istrue if exactly oneinput is true0 XOR x x1 XOR x NOT xx XOR x 0NOT – Outputis inverse ofinput
2122Logical OperationsLogical Operations Logic operations on numbers means performing theoperation on each pair of bits Logic operations on numbers means performing theoperation on each pair of bitsInitial Conditions: 1 0xF0, 2 0x3C1 AND 2, 1, 2R[2] 0x302 OR 2, 1, 2R[2] 0xFCInitial Conditions: 1 0xF0, 2 0x3C0xF0AND 0x3C0x301111 0000AND 0011 11000011 0000 F0OR 3C FC1111 0000OR 0011 11001111 11004 NOR 2, 1, 20xF0NOR 0x3C0x03R[2] 0x03Bitwise NOT operation can be performed by NOR’ingregister with itselfNOR 2, 1, 13 XOR 2, 1, 20xF0XOR 0x3C0xCCR[2] 0xCC1111 0000NOR 0011 11000000 00111111 0000XOR 0011 11001100 11000xF0NOR 0xF00x0FR[2] 0x0F1111 0000NOR 1111 00000000 11112324Shift OperationsLogical Shift vs. Arithmetic Shift Shifts data bits either left or right Arithmetic Shift Logical Shift– Bits shifted out and dropped on one side– Usually (but not always) 0’s are shifted in on the other side– Use for unsigned or nonnumeric data– Will always shift inwhether it be a left or rightshift In addition to just moving bits around, shifting is a fast way tomultiply or divide a number by (see next slides) 2 kinds of shifts If negative number staysnegative by shifting in If positive stays positive byshifting in– Logical shifts (used for numbers)– Arithmetic shifts (used for numbers)Left Shift by 2 bits:Right Shift by 2 bits:0 0 0 0 1 1 0 0Original Data0 0 0 0 0 0 1 1Shifted by 2 bits0 0 0 0 1 0 1 0Original Data0’s shifted in 0’s shifted in 0 00 0– Use for signed data– Left shift will shift in– Right shift will( the sign bit)rather than shift in 0’sLeft shiftLeft shiftRight shiftRight shift0 0 1 0 1 0 0 0Shifted by 2 bits
2526Logical ShiftArithmetic Shift Use for operations on signed data Arithmetic Right Shift – replicate MSB 0’s shifted in Only use for operations on unsigned data– Right shift by n-bits Dividing by 2n2n– Right shift by n-bits Dividing by– Left shift by n-bits Multiplying by 2n Arithmetic Left Shift – shifts in 0’s– Left shift by n-bits Multiplying by 2n0xFFFFFFFC1 1 . 1 1 0 0 -40x0000000C0 . 0 1 1 0 0 12Arithmetic Left Shift by 2 bits:Arithmetic Right Shift by 2 bits:MSB replicated and shifted in Logical Right Shift by 2 bits:Logical Left Shift by 3 bits:0’s shifted in 0’s shifted in . 30x000000030’s shifted in 1 1 1 . 1 1 1 -1 960x000000601 . 1 0 0 0 00x0xNotice if we shifted in 0’s (like alogical right shift) our result wouldbe a positive number and thedivision wouldn’t workNotice there is no difference betweenan arithmetic and logical left shift.We always shift in 0’s. -162728MIPS Logical Shift Instructions MIPS Arithmetic Shift Instruction SRL instruction – Shift Right LogicalSLL instruction – Shift Left LogicalFormat:– SRA rd, rt, shamt– SRAV rd, rt, rs– SxL rd, rt, shamt– SxLV rd, rt, rs Notes: Examples– SRL 5, 12, 7// Shifts data in reg. 12 right by 7 places– SLLV 5, 12, 20 // If 20 5, shift data in 12 left by 5 placesNotes:– shamt limited to a 5-bit value (0-31)– SRAV shifts data in rt by number of places specified in rs– shamt limited to a 5-bit value (0-31)– SxLV shifts data in rt by number of places specified in rs SRA instruction – Shift Right ArithmeticNo arithmetic left shift (use SLL for arithmetic left shift)Format:Examples– SRA 5, 12, 7– SRAV 5, 12, 11000011Arith. Inst. unused 12 57SRL 12 57SRA00000010100100010010100000000100Arith. Inst. unused00000010100100010010100000000111Arith. Inst. 20 12 5unusedSLLVArith. Inst. 20 12 5unusedSRAV
2930I-Type InstructionsImmediate Operands I-Type (Immediate) Format6-bitsopcode5-bits5-bits Most ALU instructions also have an immediate form to be used when oneoperand is a constant value Syntax: ADDI Rs, Rt, imm16-bitsrs (src1) rt (src/dst)immediate– Because immediates are limited to 16-bits, they must be extended to a full 32bits when used the by the processor– instructions always sign-extend to a full 32-bits even forunsigned instructions (addiu)– instructions always zero-extend to a full 32-bits– rs, rt are 5-bit fields for register numbers– I Immediate is a 16-bit constant– opcode identifies actual operation Fill me in Example:opcodersrt– ADDI 5, 24, 1– LW 5, -8( 3)0010001100000101ADDI 24 50101110001100101LW is explained in the next sectionbut is an example of an instructionusing the I-type formatLW 3 5 Examples:– ADDI– ORIimmediate1-8 4, 5, -1 10, 14, -4// R[4] R[5] 0xFFFFFFFF// R[10] R[14] : SUBI is unnecessarysince we can use ADDI witha negative immediate value3132Set If Less-Than SLT rd, rs, rt– Compares rs value with rt value andstores Boolean (1 true, 0 false) valueinto rd– C code equivalent:– rd can only be 0x0000001 or0x00000000 after execution– Assumes signed integer comparison SLTI rd, rs, immediate– Same as above but now 2nd source is aconstantInitial Conditions: 1 0xffffffff, 2 0x00000000 3 0x000000ffSLT 4, 1, 2 4 0x0000000SLT 4, 3, 3 4 0x0000000SLT 4, 3, 1 4 0x0000000SLTI 4, 2, 35 4 0x0000000SLTI 4, 3, -7 4 0x0000000Loading (Reading) and Storing (Writing) Data From and To MemoryDATA TRANSFER AND MEMORYACCESS INSTRUCTIONS
3334Physical Memory OrganizationMIPS Supported Data Sizes Physical view of memory as large 2-D array of bytes (8K rows by 1KBcolumns) per chip (and several chips) Address is broken into fields of bits that are used to identify where in thearray the desired 32-bit word isIntegerFloating Point 3 Sizes Defined 3 Sizes Defined– Byte (B)– Processor always accesses memory chunks the size of the data bus, selectingonly the desired bytes as specified by the x000000– Double (D) 16-bits 2 bytes 32 32-bits 4 bytes– Halfword (H)Assume eachunit is a word.– Single (S) 8-bits 64-bits 8 bytes (For a 32-bit data bus, adouble would be accessedfrom memory in 2 reads)– Word (W) 32-bits 4 bytesPhysical View of Memory0x0404 e Address Breakdown35MIPS Memory Organization We can logically picturememory in the units (sizes) thatwe actually access them Most processors areint x,y 5;z 8;x y z;AProc.32– Still with separate addresses foreach byteMem.D32Memory & Data Size – Every byte (8-bits) has a unique address– 32-bit address bus 4 GB address space However, 32-bit logical data busallows us to access ofdata at a time Logical view of memoryarranged in rows of 4-bytesRecall variables livein memory & need tobe loaded into theprocessor to be used36F80x000002130x0000015A0x000000Little-endian memory can be thought of as right justifiedAlways provide the LS-Byte address of the desired dataSize is explicitly defined by the instruction usedMemory Access Rules– Halfword or Word access must start on an address that is a multiple ofthat data size (i.e. half multiple of 2, word multiple of 4)Registers:LB150Half AD33290x0000047CF8135A0x000000Logical Word-Oriented View31N 1NN 2N 1NHalfword operations access the2-bytes starting at the specified address0WordN 2Byte operations only access the byteat the specified addressN 3LH0x0000088EN 3Used to load a 1byte var. (char)Logical Byte-Oriented View of Mem.31Memory(Assume start address N)ByteLWUsed to load a 4byte variable (int)N 3N 2N 1NWord operations access the4-bytes starting at the specified address
3738Memory Read Instructions (Signed)MemoryGPR731Sign Extend0ByteIf address 0x02Reg. 0x3115Sign ExtendMemory Read Instructions (Unsigned)0HalfIf address 0x00Reg. 0x310WordIf address 0x00Reg. 0xLB (Load Byte)Provide address ofdesired byteLH (Load Half)Provide address ofstarting byteLW (Load Word)Provide address ofstarting byteGPR 5A137C 5A13Zero If address 0x01Reg. 0x3115Zero Extend0HalfIf address 0x00Reg. 0x 5A13000004F87C000000310WordIf address 0x00Reg. 0xLBU (Load Byte)Provide address ofdesired byte 5A13LHU (Load Half)Provide address ofstarting byte5A13LW (Load Word)Provide address ofstarting byte5A13000004F87CF87CF87C 000000000004 00000000000400000039Memory Write InstructionsMIPS Memory Alignment LimitationsMemoryGPR3170ByteReg. 0x12345678SB (Store Byte)Provide address ofdesired byte 000004000000if address 0x0231150HalfReg. 0x12345678SH (Store Half)Provide address ofstarting byte 40000004000000 Bytes can start at any address Halfwords must start on aneven address Words must start on anaddress that is a multiple of 4 Examples:– Word @ A18C –if address 0x02EA– Halfword @ FFE6 –310WordReg. 0x12345678SW (Store Word)Provide address ofstarting byte 000004000000– Word @ A18E –if address 0x00– Halfword @ FFE5 –C1294B00FFE4 52BDCF497CF8135A00A18CAddr
41Load Format (LW,LH,LB)More LOAD Examples Syntax: LW rt, offset( rs)––––42 Examples rt Destination registeroffset( rs) Address of desired dataOperation: rt Mem[ offset rs ]offset limited to 16-bit signed number– LB 2,0x45( 3)– LH 2,-6( 4)– LHU 2, -2( 4) Examples// 2 // 2 // 2 – LW 2, 0x40( 3) // 2 – LBU 2, -1( 4)// 2 – LH 2, 0xFFFC( 4) // 2 2old val.F8BE97CD0x002048 2old val.F8BE97CD0x002048 300002000134982FE0x002044 ory 4 4AddressAddress43Store Format (SW,SH,SB) SW rt, offset( rs)––––Loading an Immediate If immediate (constant) rt Source registeroffset( rs) Address to store dataOperation: Mem[ offset rs ] rtoffset limited to 16-bit signed number– Use or instruction with register– Examples ADDI 2, 0, 1 ORI 2, 0, 0xF110 Examples// 2 0 1 1 (Loads const. 1 into 2)// 2 0 0xF110 0xF110 (Loads 0xF110) If immediate more than 16-bits– SW 2, 0x40( 3)– SB 2, -5( 4)– SH 2, 0xFFFE( 4) 2123489AB0x002048 dress 444– Immediates limited to 16-bits so we must load constant witha 2 instruction sequence using the specialinstruction– To load 2 with 0x12345678 2 2
4546Translating HLL to Assembly HLL variables are simply locations in memory– A variable name really translates to an address inC assemblyoperatorAssemblyNotesint x,y,z; x y z;LUI 8, 0x1000ORI 8, 8, 0x0004Assume x @ 0x10000004& y @ 0x10000008& z @ 0x1000000C"Be the Compiler"TRANSLATING HIGH-LEVEL CODEchar a[100]; a[1]--;47Translating HLL to AssemblyC operatorAssemblyNotesint dat[4],x; x dat[0];x dat[1];LUI 8, 0x1000ORI 8, 8, 0x0010LW 9, 0( 8)Assume dat @ 0x10000010& x @ 0x10000020unsigned int y;short z;y y / 4;z z 3;LUI 8, 0x1000ORI 8, 8, 0x0010LW 9, 0( 8)SW 9, 0( 8)LH 9, 4( 8)SH 9, 4( 8)Assume y @ 0x10000010 &z @ 0x10000014Assume array ‘a’ starts @0x1000000C
EE 109 Unit 13 –MIPS Instruction Set 2 INSTRUCTION SET OVERVIEW Architecting a vocabulary for the HW 3 Instruction Set Architecture (ISA) Defines the _ of the processor and memory system Instruction set is the _ the HW can understand and the SW is composed with 2 approaches
bits, gọi là MIPS-64. MIPS xem xét trong môn học này là MIPS làm việc với các thanh ghi chỉ 32 bit, gọi là MIPS-32. ÞTrong phạm vi môn học này, MIPS dùng chung sẽ hiểu là MIPS-32 Tóm lại, chỉ có 3 loại toán hạng trong một lệnh của MIPS 1. Toán hạng thanh ghi (Register Operands) 2.
Table 1: How 2020 MIPS Final Scores Relate to 2022 MIPS Payment Adjustments Final Score Points MIPS Payment Adjustment 0.00 – 11.25 points Negative (-) MIPS payment adjustment of -9% 11.26 – 44.99 points Negative (-) MIPS payment adjustment, between 0% and -9%, on a linear sliding scale 45.00 points (Performance threshold 45.00 points)
Performance on EEMBC benchmarks aggregate for Consumer, Telecom, Office, Network, based on ARM1136J-S (Freescale i.MX31), ARM1026EJ-S, Tensilica Diamond 570T, T1050 and T1030, MIPS 20K, NECVR5000). MIPS M4K, MIPS 4Ke, MIPS 4Ks, MIPS 24K, ARM 968E-S, ARM 966E-S, ARM926EJ-S, ARM7TDMI-S scaled by ratio of Dhrystone MIPS within architecture family.
ACOs in MIPS receive advantages by being scored under the MIPS APM Scoring Standard, which gives ACOs favorable treatment for their commitment to value-base care. Based on the low bar set for 2019 reporting in MIPS, ACOs should easily avoid penalties under MIPS and will be eligible for MIPS bonuses and exceptional performance bonuses.
Chapter 1: Getting started with mips Remarks This section provides an overview of what mips is, and why a developer might want to use it. It should also mention any large subjects within mips, and link out to the related topics. Since the Documentation for mips is new, you may need to create initial versions of those related topics. Examples
MIPS R3000 ISA† MIPS R3000 is a 32-bit architecture Registers are 32-bits wide Arithmetic logical unit (ALU) accepts 32-bit inputs, generates 32-bit outputs All instruction types are 32-bits long MIPS R3000 has: 32 general-purpose registers (for use by integer
CSE 30321 - Lecture 07 - Introduction to the MIPS ISA 1 Lecture 07 Introduction to the MIPS ISA University of Notre Dame CSE 30321 - Lecture 07 - Introduction to the MIPS ISA Shortcomings of the simple processor – Only 16 bits f
Introduction to MIPS architecture MIPS Assembly Language – Arithmetic: » add, sub, addi, addu, addiu, subu – Data movement : » lw, sw, lbu, sb, lui, ori – Program Control: » Branch, jump, stacks and procedure calls – MIPS programming examples Comp 212 Computer Org & ArchComp 212 Compute
