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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 20141277Placement for Binary-Weighted Capacitive Array inSAR ADC Using Multiple Weighting MethodsYongfu Li, Student Member, IEEE, Zhe Zhang, Student Member, IEEE, Dingjuan Chua, Student Member, IEEE,and Yong Lian, Fellow, IEEEAbstract—The overall accuracy and linearity of a alog-to-digitalconverter are primarily determined by its digital-to-analogconverter’s (DAC’s) matching characteristics. As the resolutionof the DAC increases, it is harder to achieve accurate capacitanceratios in the layout, which are affected by systematic and randommismatches. An ideal placement for the DAC array should try tominimize the systematic mismatches, followed by the random mismatch. This paper proposes a placement strategy, which incorporates a matrix-adjustment method for the DAC, and differentplacement techniques and weighting methods for the placementsof active and dummy unit capacitors. The resulting placementaddresses both systematic and random mismatches. We considerthe following four systematic mismatches such as the first-orderprocess gradients, the second-order lithographic errors, theproximity effects, the wiring complexity, and the asymmetricalfringing parasitics. The experimental results show that theplacement strategy achieves smaller capacitance ratio mismatchand shorter computational runtime than those of existing works.Index Terms—Analog placement, analog–digital-converter,capacitance mismatch ratio, capacitive array, commoncentroid, digital–analog-converter, spatial correlation coefficient,successive-approximation-register.I. I alog-to-digital converters (ADCs) are by far the mostpopular architecture for data-acquisition applications andan example of a conventional N-bit SAR ADC architectureis shown in Fig. 1. It consists of a sample-and-hold, acomparator, a N-bit capacitive digital-to-analog converter(DAC) array and a SAR control logic, where N is theresolution of the ADC. The ADC survey in [1] has shownthat the Walden figure-of-merit (FOM) for state-of-the-artSAR ADCs is at least 10 better than other ADCs architectures and it is proven empirically that the SAR ADCsare the most energy-efficient ADCs over a broad range ofresolutions [2], [3].SManuscript received December 18, 2013; revised March 11, 2014; acceptedApril 17, 2014. Date of current version August 18, 2014. This work wassupported in part by the National Research Foundation Competitive ResearchProgramme under NRF-CRP8-2011-01 and in part by the National Universityof Singapore under Grant R-263-000-A02-731. This paper was recommendedby Associate Editor X. Li.The authors are with the Department of Electrical and ComputerEngineering, National University of Singapore, Singapore 119260(e-mail: liyongfu@nus.edu.sg; zhezhang@nus.edu.sg; elechuad@nus.edu.sg;eleliany@nus.edu.sg).Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCAD.2014.2323217Fig. 1.Block diagram of an N-bit SAR ADC.The overall accuracy and linearity of a matching limited SAR ADC are primarily determined by its capacitiveDAC array matching characteristics. As the resolution of theDAC increases, it is harder to achieve accurate capacitanceratios in the layout, which are affected by the systematic andrandom mismatches. The systematic mismatch is caused byidentical devices with asymmetrical environments, while therandom mismatch is caused by statistical fluctuations in processing conditions or material properties [4], [5]. There aretwo popular mismatch evaluation models to quantify the random mismatch and the first-order systematic mismatch. First,the 2-D spatial correlation model helps to quantify the degreeof dispersiveness in the layout [6]. A higher degree of dispersiveness indicates that there is a smaller random mismatchin the layout. Second, the 2-D oxide gradient model helpsto estimate the oxide-gradient-induced mismatch (first-ordersystematic mismatch) in the capacitive array [7], [8].Numerous placement methods have been reported to dealwith arbitrary shapes and devices in the layout. The heuristicsearch approach aims to maximize the degree of dispersiveness in the layout but the placement might not have acommon-centroid arrangement and thus resulting a systematicmismatch [9]. Pairs representation techniques are introducedto handle symmetry, common-centroid, and general placementsimultaneously but they do not yield the optimal placement forthe binary-weighted capacitive arrays [10]–[14]. The simulatedannealing-based (SA-based) approach aims to increase thedegree of dispersiveness and minimize oxide-gradient-inducedc 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.0278-0070 See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

1278IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014mismatch simultaneously but the resulting placement increasesthe complexity of the wiring [15], [16].Besides the first-order systematic mismatch, no previous studies take into account of the following systematic mismatchesfor the placement of the binary-weighted capacitive array, suchas the second-order lithographic errors, the proximity effects,the symmetry and the complexity of the wiring, and the farrange fringing fields effects. For example, in the nanometerCMOS technologies, the interconnect parasitic capacitanceshave reached the order of femtofarads while the capacitanceof unit capacitors in the DAC has reduced to the scale of afew femtofarads for state-of-the-art SAR ADCs [17]–[21]. Anyasymmetry in the wiring scheme can easily cause more problems than are solved [5], [22]. Beside the placement constraints,many existing methods face exponential increase in the computational runtime. For example, a 10-bit capacitive array inA32 32 matrix has approximately 3 10604 number of combinations. The number of combinations for the binary-weightedcapacitive arrays, grows astronomically beyond 10-bit and thusit is harder to achieve the optimization goal within acceptablecomputational runtime.To deal with all these challenges in the binary-weightedcapacitive array, this paper presents a placement strategy,which incorporates a matrix-adjustment method for the DAC,different placement techniques and weighting methods forthe placements of active and dummy unit capacitors. Thisapproach addresses both systematic and random mismatchesand reduces the computational runtime significantly. The following systematic mismatches are considered during theplacement: 1) the first-order process gradient effects; 2) thesecond-order lithographic errors and the proximity effects;3) the symmetry and the complexity of the wiring; and 4) thefar range fringing fields effects.The first-order process gradient effects are minimizedthrough the matrix-adjustment method to achieve a more symmetrical structure for any binary-weighted capacitive array. Inorder to alleviate the second-order lithographic errors and theproximity effects, the capacitive array is surrounded by thedummy unit capacitors to act as adjacent structures. The placement of the remaining dummy capacitors is dealt with by thespatial weighting method. This method helps to maximize theoverall spatial correlation coefficient for the binary-weightedDAC capacitive array. The placement of DAC unit capacitorsis dealt with by the diagonal weighting method. This methodallows a dispersive placement of the DAC while maintainingsymmetrical and common-centroid arrangement. The placement resembles a star-like placement and thus increases thedegree of dispersiveness and simplifies the wiring complexity compared to existing works. Unequal far-range fringingfields between capacitors happen when the unit capacitorsare placed in the different surroundings. This effect is amplified significantly when the physical dimensions of the unitcapacitor and the minimum spacing between unit capacitorsdecrease in advanced CMOS technologies. This effect is minimized through the homogenization method, which addressesthe existing trade-offs in [23]. The experimental results showthat the placement obtained using the proposed placementstrategy achieves a smaller oxide-gradient-induced mismatchFig. 2.N-bit binary-weighted capacitive DAC array.and shorter computational runtime than those of existingworks.The rest of this paper is organized as follows. Section IIdefines the terminology used in this paper and discusses the twoexisting evaluation models, namely the oxide gradient model [6]and the 2-D correlation model [8]. Section III discusses ourproposed placement strategy. Finally, experimental results arepresented in Section IV and conclusions are given in Section V.II. T ERMINOLOGY AND R EVIEW OF E VALUATION M ODELSA. Terms and Definitions for SAR Capacitive DAC ArraysIn a conventional N-bit binary-weighted capacitive array,as shown in Fig. 2, there are N 1 capacitors denoted byC {C0 , C1 , C2 , ., Cj , ., CN } with a ratio of C0 : C1 : C2 :C3 :.: Cj :.: CN be b : b : 2b : 4b : . : 2j 1 b : . : 2N 1 b, where0 j N and b Z . For the layout implementations, CtypeAin [24] and [25] and CtypeB in [26] and [27] are known tobe the most common architectures adopted when realizing theN-bit capacitive array, where CtypeA {C0A , C1A , C2A , ., CNA } 1 : 1 : 2 : 4 : . : 2N 1 and CtypeB {C0B , C1B , C2B , ., CNB } 2 : 2 : 4 : 8 : . : 2N . CtypeB is often chosen in implementationsbecause every element in CtypeB is made up of even numberof unit capacitors and thus, helps to further improve the symmetry of the layout. Ctotal is the total number of unit capacitorsin C and it is placed in a AL W matrix. The size of AL W isdenoted by S, where {S L W : L, W Z }. Let al,w denotethe entry in the l-th row and w-th column, where 0 l Land 0 w W. Each entry in AL W can be placed witheither one unit capacitor from C or one dummy unit capacitor, Cdummy . The total number of dummy unit capacitors inAL W is denoted as CD , where CD S Ctotal .To have a fair comparison with other previous works asthose in [6], [8], [9], [15], and [16], two mismatch evaluation models are adopted in this paper [6], [8]. The followingsubsection reviews these two models in the context of CtypeAarchitecture and the parameters of the models are defined.B. Random Mismatch—2-D Spatial Correlation ModelThe spatial correlation model of any two unit capacitorsCum and Cun , in the CtypeA is defined as ρm,nρm,n ρuD(m,n)(1)where ρu is the correlation coefficient between any two unitcapacitors and the distance D(m, n) between Cum and Cun is (2)Dm,n (xm xn )2 (ym yn )2 LD

LI et al.: PLACEMENT FOR BINARY-WEIGHTED CAPACITIVE ARRAY IN SAR ADC USING MULTIPLE WEIGHTING METHODS1279Fig. 3. Experimental setup for the geometry of unit capacitors and mismatchparameters.where (xm , ym ) and (xn , yn ) are coordinates of Cum and Cun ,respectively, and LD is dependent on the process and size of thedevices. To simplify (1) and (2), we assume LD 1 to observethe relationship between correlation and random mismatch. Wealso assume that all unit capacitances have the same variancesand the correlation coefficient between any two unit capacitorsρu is 0.9, as shown in Fig. 3. Therefore, the variance of anycapacitor in CtypeA , CiA , which consists of 2i unit capacitors,where 0 i N 1 can be simplified toi 12i2 2i AVar(Cu ) 2Cov(Cia , Cib )Var Ci a 1Fig. 4. Flow chart illustrating the various techniques used in the proposedplacement strategy.a 1 b a 1 Var(Cu ) (2 2ii 12 i2 ρa,b )(3)L a 1 b a 1where Var(Cu ) is the variances of the unit capacitor andCov(Cia , Cib ) is the covariance of Cia and Cib .Similarly, given any two capacitors in CtypeA , CiA and CjA ,which consist of 2i and 2j unit capacitors, respectively, where0 i, j N 1, the correlation coefficient of CiA and CjA is thesummation of the correlation coefficients of all the capacitorpairs in CiA and CjA . It can be simplified to Cov CiA , CjAρi,j Var CiA Var CjA2i2jρa,ba 1 b 1 2i 22i 12ia 1 b a 1 ρa,b2j 22j 12j ρa,ba 1 b a 1(4) where Cov CiA , CjA is the covariance of CiA and CjA . Var CiA and Var CjA are variances of capacitors CiA and CjA , respectively.For a N-bit capacitive array, the total correlation coefficient,L, is the summation of the correlation coefficients of all thecapacitor pairsN N 1 ρi,j .(5)i 1 j i 1It was reported that a higher total correlation coefficient, L,leads to a lower variation in the capacitive array or a highermatching capacitance ratio [6]. This model provides an insightto the degree of randomness and dispersion in the capacitivearray.C. First-Order Process Mismatch—Oxide Gradient ModelAfter the placement of CtypeA , the effective capacitor ratiobecomes C0A : C1A : C2A : C3A : . . . : CjA : . . . : CNA . LetA , CA , CA , . . . , CA } denote the set of 2j 1 unit capac{Cj1j2j3j2j 1itors belonging to CjA . The total capacitance of CjA is thesummation of the capacitance of the unit capacitors in CjA .Assume that the capacitive array is affected by a linear oxidegradient γ in the direction specified by an angle θ , as shownin Fig. 3. Due to the oxide gradient, different unit capacitorslocated at the different locations experience different oxidethicknesses and therefore the effective capacitance of any unitcapacitor ist0(6)CjiA Cutiwhere Cu is the unit capacitance, t0 is the oxide thickness atthe origin 0 and ti is the equivalent oxide thickness at location(xi , yi )(7)ti t0 γ (xi cos θ yi sin θ ).

1280Fig. 5.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014Experimental placements for 3-bit CtypeA in A2 4 and A3 4 . (a) Layout I. (b) Layout II. (c) Layout III. (d) Layout IV. (e) Layout V.The ratio mismatch is then calculated for all the pairs ofcapacitor in CtypeA . The capacitance ratio mismatch, M inCtypeA is defined as CA A jA CjA C CM max k A k 100%CjCkA A A Cj Ck max A A 1 100%Ck Cj(8)where 0 j, k N 1 . Since the gradient angle cannot bepredicted, the mismatch is estimated through 0 θ 180 and the maximum mismatch value is obtained.This model provides an insight to the degree of symmetryand coincidence which is very important for binary-weightedcapacitive array in nanometer CMOS technologies [7]. Asmaller capacitance mismatch ratio, M, yields a smaller systematic mismatch in the capacitive array. To have a faircomparison with other works, we assume that the oxide thickness t0 is 40 nm, the oxide gradient γ is 10 parts per millionand the width and length of a unit capacitor, Cu is 25 μm (W)by 25 μm (H) with a spacing of 9.1 μm (Sx ) by 2.6 μm (Sy ),respectively, as shown in Fig. 3.III. P LACEMENT S TRATEGYThe proposed placement strategy first adjusts the matrixsize based on the parameters listed in Fig. 3 and the typeof binary-weighted capacitive array under consideration, e.g.,CtypeA or CtypeB . As it will be explained in Section III-A,the matrix size has a great influence on the final placementresult and the degree of symmetry (first-order process gradienteffects). Our next step is to prioritize of the placement of thedummy capacitors and the capacitive array, respectively. Thiseliminates the second-order lithographic errors and the proximity effects and maximizes the degree of dispersiveness thatcan be achieved by the capacitive array. In order to simplify therouting in the common-centroid layout, the diagonal weightingis proposed for the placement of the capacitive array and thusallowing us to use a simple rectangular and diagonal wiringmethod to connect the capacitors together. Finally, the homogenizing algorithm is applied to the matrix and this allows abetter distribution of parasitic capacitances amongst the capacitive array. The flow chart, as shown in Fig. 4, provides thedetails of our proposed placement strategy.A. Matrix-Adjustment MethodBased on the oxide gradient model and the spatial correlation model, we investigate all the different possible layoutsfor the 3-to-5-bit CtypeA and CtypeB capacitive arrays in different matrix sizes. Five different examples of a 3-bit CtypeAlayout are presented in Fig. 5, for the discussion of our matrixadjustment method. Fig. 5(a) shows a layout (Layout I) inA2 4 with partial symmetry about the origin where C0A andC1A are placed diagonally. Fig. 5(b) and (c) shows layouts(Layout II and III) in A2 4 with partial symmetry about they-axis and the x-axis, respectively, where C0A and C1A are placedon adjacent sides. This adjacent side placement of C0A and C1Aresulted in decreased M and L, as shown in the table in Fig. 5.Fig. 5(d) and (e) show layouts (Layout IV and V) in A3 4 withsymmetry about the x-axis and partial symmetry about the origin, respectively. By changing the matrix to A3 4 , there arefurther improvements in M and L. The results were calculatedbased on the input parameters listed in Section II except that

LI et al.: PLACEMENT FOR BINARY-WEIGHTED CAPACITIVE ARRAY IN SAR ADC USING MULTIPLE WEIGHTING METHODS1281Fig. 7.Illustrations of entry weight definitions. (a) Distance weight.(b) Spatial correlation weight. (c) Diagonal weight.Fig. 6. Experimental placements for 3-bits CtypeB capacitive arrays in A6 6and A7 6 . (a) Layout V in A6 6 . (b) Layout V in A7 6 .Sx and Sy are 9.1 μm as this allows equal spacing betweenunit capacitors. The plots of capacitance ratio mismatch variation with respect to the gradient angle for these placements,as shown in Fig. 5, provide us with insightful details aboutthe symmetrical property of the layout. Based on all the layouts investigated in this experiment, the following observationswere made.1) CtypeA contains an odd-numbered unit capacitor in C0Aand C1A and thus, it is harder to achieve minimal M inAodd odd or Aeven even . Aodd even or Aeven odd providesa better symmetry for CtypeA capacitive arrays.2) Adjacent side placements for the odd-numbered capacitors yield a smaller M. Thus, it is preferred that C0Aand C1A are placed on adjacent sides and they should beplaced near the center of a matrix.3) The diagonal placements of capacitor pairs, from C2 toCN , yield a higher L than adjacent side placements.4) CtypeA achieves better symmetry when it has a symmetrical mismatch variation.The same evaluation method is applied to CtypeB andFig. 6 shows an example of two different layouts of a 3-bitCtypeB in A6 6 and A7 6 . The diagonal placements of theeven-numbered capacitor pairs and the matrix-adjustment toAeven even in the CtypeB has reduced M and improved L.Therefore, we propose to adjust the size of the matrix, AL Waccording to the types of capacitive array. The modificationto the matrix size does not have a significant impact on theoverall area.B. Dummy Capacitors Placement Using Spatial WeightingMethodAfter the matrix has been adjusted to achieve minimal M,the next priority is the placement for the dummy unit capacitors. Although the dummy unit capacitors do not inducemismatches, their location affects the matching of the capacitive array. To minimize these mismatches, it is important toconsider the placement for the dummy unit capacitors. CD iscomputed based on the matrix size and the capacitive array.These dummy unit capacitors are first added into the perimeter of the capacitive array to act as adjacent structures andtherefore minimizes the second-order lithographic errors. Twoweighting methods are evaluated to determine the best choicefor prioritizing the location for the remaining dummy unitcapacitors in AL W .The distance weighting method was first used for the matrixto pair-sequence transformation [8], [16]. The distanc

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 9, SEPTEMBER 2014 1277 Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods Yongfu Li, Student Member, IEEE, Zhe Zhang, Student Member, IEEE, Dingjuan Chua, Student Member, IEEE, and Yong Lian, Fellow, IEEE Abstract—The overall accuracy and linearity of a matching .

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