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VOL. 12, NO. 15, AUGUST 2017ISSN 1819-6608ARPN Journal of Engineering and Applied Sciences 2006-2017 Asian Research Publishing Network (ARPN). All rights reserved.www.arpnjournals.comANALYSIS OF VARIOUS PULSE WIDTH MODULATIONS (PWM) FORMULTI-LEVEL INVERTER WITH REVERSING VOLTAGE TOPOLOGYP. N. S. Chandana, S. Augusti Lindiya, K. Vijayarekha, D. Uma and M. BharathiDepartment of Electrical Engineering, SASTRA University, IndiaE-Mail: chandanapulipaka@yahoo.inABSTRACTMulti-level inverter technology is used to obtain a high output power from medium voltage sources like batteriesand solar panel. Reduced harmonic distortion in the output voltage and lower EMI (Electro Magnetic Interference) are themain advantages of multi-level inverter. However, there are some disadvantages such as increased number of componentsas level is increased, complicated PWM control method and voltage balancing problem at neutral point. Reversing voltagetopology overcomes the disadvantages of the conventional multi-level inverter. The new topology uses reduced quantity oftotal switches at higher levels which leads to the reduction in switching losses, lesser carrier signals for PWM control,improves power quality and reduces the harmonics at the output voltage. The new converter topology is implemented for5-level and 9-level using Sinusoidal Pulse Width Modulation (SPWM) techniques. Phase disposition SPWM, Phaseopposition disposition SPWM, Alternate phase opposition disposition SPWM and Variable frequency SPWM techniquesare applied to generate the gate pulses for the switches in the 9-level inverter and the THD (%) is compared. Thesimulation results are presented and discussed.Keywords: reversing voltage multilevel inverter, sinusoidal pulse width modulation (SPWM), phase disposition sinusoidal pulse widthmodulation (PDSPWM),Phase opposition disposition Sinusoidal pulse width modulation (PODSPWM), alternate phase dispositionsinusoidal pulse width modulation (APDSPWM), variable frequency sinusoidal pulse width modulation (VFSPWM), total harmonicdistortion (THD).1. INTRODUCTIONThe conventional voltage source inverter (VSI)generates a two level output voltage with levels / -Vdc/2and zero, where Vdc is the dc link voltage. The variousPWM strategies [1] are applied to high frequency switchesto obtain the quality output voltage or current waveformwith reduced ripple content. In high-power mediumvoltage applications, the VSI have limitations such asswitching losses at high frequency and voltage/powerratings.The multilevel inverter consists of powersemiconductors and capacitors voltage sources. The outputvoltage of the inverter will be stepped waveform whichwill be nearly equal to sinusoidal waveform. The highervoltage steps leads to reduced dv/dt stress on the load,lesser harmonic content and higher power qualitywaveforms [2]. The multilevel inverter requires largenumber of semiconductor switches which leads tocomplexity in the pulse generation, driver circuit andmechanical layout. The individual voltage sources orseries capacitors produce a voltage balance problem.However, to solve the voltage balancing problem, anothermultilevel converter is required [3] [4].The commonly used multilevel inverters arediode clamped, flying capacitor and cascaded H-bridgeinverters [5]. In the diode clamped multilevel inverter, thediodes are switched to get the different voltage level.Therefore, it requires large number of diodes. In the flyingcapacitor multilevel inverter, the capacitors are chargedand the capacitor voltages can be added or subtracted toobtain the required levels of the output voltage. Therefore,it requires more number of capacitors. In cascaded Hbridge inverters components like diodes and capacitors arenot used. The H-bridge inverter requires minimal numberof devices at the cost of higher number of dc-powersupplies.The Reversing Voltage topology uses less number ofswitches at higher levels as compared to availableinverters. This topology requires less carrier signals anddoes not need balancing of the voltage [6] [7].The new topology [6] [7] is implemented for 5level and 9-level with PWM techniques. The first sectiondescribes the reversing voltage topology schematic. Thepulses are generated by Phase disposition SPWM, Phaseopposition disposition SPWM, Alternate phase oppositiondisposition SPWM and Variable frequency SPWMtechniques for 9-level inverter. The final section shows thesimulation results.2. REVERSING VOLTAGE TOPOLOGYThe reversing voltage multilevel inverter has twoparts i.e. level generator and polarity generator (Fullbridge converter). The level generator produces thepositive sign stepped waveform. The polarity of thegenerated stepped waveform can be altered using thepolarity generator which is a full bridge converter.Thepolarity generator produces the positive and negativehalf stepped waveform. The level generator requires highfrequency switches and polarity generator uses lowfrequency switches. The inverter uses both high and lowfrequency switches to reduce the voltage stress on thepower devices.A. Operation of five-level inverter using reversingvoltage topologyThe schematic of single-phase five level inverter is shownin the fig. The inverter consists of 2 DC sources and 8switches. The switches S1, S2, S3 and S4 are level generator4560

VOL. 12, NO. 15, AUGUST 2017ISSN 1819-6608ARPN Journal of Engineering and Applied Sciences 2006-2017 Asian Research Publishing Network (ARPN). All rights reserved.www.arpnjournals.comswitches. By switching the above switches in sequence thestepped waveform is generated. The full bridge switchesS6, S7, S8 and S9 are used as a polarity generator. Thepositive and negative polarity of the output voltage isobtained by triggering these switches in sequence.Therefore, the semiconductor switches are reduced whencompared to the conventional multilevel inverter.Figure-2. Schematic of single-phase nine level inverter.Figure-1. Schematic of single-phase five level inverter.The switching modes to get the different voltagesteps is When S1 and S4 is turned ON, the voltage level 2Vdcis generated at the output When S1 and S3 is turned ON, the voltage level V dc isgenerated at the output When S2 and S3 is turned ON, the voltage level zerois generated at the outputThe switching modes to get the positive andnegative polarity is When S5 and S8 is turned ON, the positive half cycleof the output waveform is generated When S7 and S6 is turned ON, the negative half cycleof the output waveform is generatedTable-1. Switching states for reversing voltage nine levelinverter.Outputvoltage0Vdc2VdcThe switching modes to get the different voltagesteps are When S1 and S6 is turned ON, the voltage level 4Vdcis generated at the output When S2, S7 and S6 is turned ON, the voltage level3Vdc is generated at the output When S2, S3, S8 and S6 is turned ON, the voltage level2Vdc is generated at the output When S2, S3, S4 and S6 is turned ON, the voltage levelVdc is generated at the output When S2, S3, S4 and S5 is turned ON, the voltage levelzero is generated at the outputBy switching S1, S2, S3, S4, S5, S6, S7 and S8 thenine-level stepped waveform is obtained. The Full bridgeconverter consists of four switches S9, S10, S11 and S12. When S9 and S12 is turned ON, the positive half cycleof the output waveform is generated When S10 and S11 is turned ON, the negative halfcycle of the output waveform is generatedTable-2. Switching states for reversing voltage nine levelinverter.S1S2S3S40110010102, 3, 4, 51001Vdc2, 3, 4, 62Vdc2, 3, 6, 83Vdc2, 7, 64Vdc1, 6B. Operation of nine-level inverter using reversingvoltage topologyThe schematic of single-phase nine level inverteris shown in the fig. The nine-level inverter requires 12switches and 4 DC sources to generate the outputwaveform. It is sufficient to produce pulses only forpositive half cycles of the output voltage. The negativehalf cycle is automatically generated by switching the fullbridge converter. It requires less high frequency switches.DC Voltage levelSwitching operation3. SIMULATION RESULTSIn this section, the simulation results for ninelevel inverter using Reversing Voltage topology aredemonstrated by MATLAB R2009a software module. Thedesign parameters for single phase nine-level inverter is:4561

VOL. 12, NO. 15, AUGUST 2017ISSN 1819-6608ARPN Journal of Engineering and Applied Sciences 2006-2017 Asian Research Publishing Network (ARPN). All rights reserved.www.arpnjournals.com Each dc source voltage is 100 V and total voltage is400 VFrequency of carrier signal is 5 KHzFull bridge converter switches are switched at 50 HzLoad R 100 ΩIn conventional inverter, N-1 number of carriersis used, where N is the number of voltage levels. So, eightcarrier waveforms are required to design a nine level.However, nine-level inverter using the new topology willrequire (N-1)/2 carriers, i.e. only fourcarriers. The fourcarrier waveforms are compared with the positive halfcycle of the sinusoidal waveform to generate the requiredgate pulses. This topology requires only half the carrierswhen compared to the traditional multilevel inverter. Itrequire simpler controller as the generation of the controlsignals are easy.compared with the positive cycle of the sinusoidalwaveform whenever the sinusoidal waveform intersectsthe carrier signal a pulse is generated. The four pulses aregenerated. The remaining pulses are produced byconnecting NOT operator to the obtained four pulses. Theeight gate pulses are given to the level generator switchesFigure-6. Phase disposition SPWM modulationwaveform.The pulses to the full generator switches aregiven from the pulse generator. The output voltage willhave nine levels.Figure-3. Circuit diagram of single-phase fivelevel inverter.Figure-7. FFT Plot for output voltage PDSPWM.The FFT plot is shown in Figure-7. The THD (%)of the output voltage is 16.27% when Phase dispositionSPWM is implemented to the level generator switches.Figure-4. Output voltage waveform of single-phasefive level inverter.Figure-5. Circuit diagram of single-phase Nine levelinverter.A. Phase disposition SPWMIn this technique, each carrier waveform will bein phase with each other. The carrier waveforms areB. Phase opposition disposition SPWMIn this technique, all carrier waveforms abovereference will be in phase and 180 degree out of phasewith those below reference. The FFT analysis for theoutput voltage is taken.Figure-8. Phase opposition disposition SPWMmodulation waveform.4562

VOL. 12, NO. 15, AUGUST 2017ISSN 1819-6608ARPN Journal of Engineering and Applied Sciences 2006-2017 Asian Research Publishing Network (ARPN). All rights reserved.www.arpnjournals.com Frequency of third and fourth carrier waveforms is 10KHzThe frequency of the carrier signal will differfrom each other. The pulses are generated when thepositive sinusoidal waveform coincides with the carrierwaveform. The obtained pulses and the pulses from theNOT operator are given to the level generator switches.The FFT analysis for the output voltage is taken.Figure-9. FFT Plot for output voltage PODSPWM.The FFT plot is shown in fig. The THD (%) ofthe output voltage is 16.84% when Phase oppositiondisposition SPWM is implemented to the level generatorswitches.A. Alternate phase opposition disposition SPWMIn this technique, each carrier waveform will bein out of phase with its neighbour carrier by 180 degree.The FFT analysis for the output voltage is taken.Figure-12. Variable frequency SPWMmodulation waveform.Figure-10. Alternate phase opposition disposition SPWMmodulation waveform.Figure-13. FFT Plot for output voltage VFSPWM.The FFT plot is shown in fig. The THD (%) ofthe output voltage is 14.30% when Variable frequencySPWM is implemented to the level generator switches.Figure-11. FFT Plot for output voltage APODSPWM.The FFT plot is shown in fig. The THD (%) ofthe output voltage is 16.45% when Alternate phaseopposition disposition SPWM is implemented to the levelgenerator switches.B. Variable frequency SPWMin this technique, the time duration of the one ormore waveforms will vary. Frequency of first carrier waveform is 2 KHzFrequency of second carrier waveform is 4 KHzFigure-14. Output voltage waveform of single-phasefive level inverter.The output voltage waveform of the inverter forevery PWM technique will be same. The THD in % istabulated in the table. When compared to the other PWMtechniques, the variable frequency PWM technique willgive less THD (%) when compared to the othertechniques.4563

VOL. 12, NO. 15, AUGUST 2017ISSN 1819-6608ARPN Journal of Engineering and Applied Sciences 2006-2017 Asian Research Publishing Network (ARPN). All rights reserved.www.arpnjournals.comTable-3. THD values for different PWM techniques.Different types of PWM for9-level inverterPhase disposition PWMTHD(%)16.27Phase opposition disposition PWMAlternate phase opposition dispositionPWMVariable Frequency PWM16.8416.4514.30Reversing Voltage Topology. International Journal ofAdvanced Research in Electrical, Electronics andInstrumentation Engineering. 03(12): 14077-14081.[7] E. Najafi, A.H.M. Yatim and A.S. Samosir. 2008. Anew topology-reversing voltage (RV) for multi-levelinverters. 2nd International conference on power andenergy (PECon 08), pp. 604-608, Malaysia.CONCLUSIONSIn this project, Reversing Voltage is applied toimprove multilevel performance with the aid ofcompensating the disadvantages in conventional multilevelinverters. This strategy improves output voltage, reducesutilizing a number of semiconductor switches and voltageimbalance. This project makes use of carrier based SPWMscheme using Phase Disposition, Phase oppositiondisposition, Alternate phase opposition disposition andvariable frequency process and would manage outputvoltage and frequency and minimize the harmonic. Asingle phase 5-level and 9-level inverter with reversingvoltage strategy is developed. The above mentionedSPWM techniques are applied to the 9-level inverter andobserved the harmonic content. The variable frequencySPWM technique gives the less THD value 14.30% whencompared to the other SPWM techniques.REFERENCE[1] Jose Rodriguez, Jih-Sheng Lai and Fang Zheng Peng.2002. Multilevel Inverters: A survey of topologies,controls and applications. IEEE Trans. Ind.Electronics. 49(4): 724-738.[2] Jang-Hwan Kim; Seung-Ki Sul; Enjeti P.N. 2005. Acarrier based PWM method with optimal switchingsequence for a multi-level four-leg VSI. IEEEindustry application conference. 1: 99-105.[3] Corzine K. A. and Majeethia S. K. 2000. Analysis ofa novel four-level DC/DC boost converter. IEEETrans. Ind. Appl. 36, 1342.[4] Rojas R., Ohnishi T. and Suzuki T. 1995. PWMcontrol method for a four-level inverter, in Proc.Electric Power Applications, IEE. p. 390.[5] Jose Rodriguez, Leopoldo G. Frequelo, Samir Kouro,Jose I. Leon, Ramon C. Portillo, Ma Angeles MartinPrats and Marcelo Perez. 2009. Multilevel ations. IEEE Proceedings. 97(11): 1786-1817.[6] Bindu P. Hima and S. Mallikarjunaiah. 2014.Multilevel Inverter for Induction Motor Drives Using4564

5-level and 9-level using Sinusoidal Pulse Width Modulation (SPWM) techniques. Phase disposition SPWM, Phase opposition disposition SPWM, Alternate phase opposition disposition SPWM and Variable frequency SPWM techniques are applied to generate the gate pulses for the switches

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