3-Phase Brushless DC Motor Pre-Driver
A49313-Phase Brushless DC Motor Pre-DriverFeatures and BenefitsDescription Drives 6 N-channel MOSFETs Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Hall element inputs PWM current limiting Dead time protection FG outputs Standby mode Lock detect protection Overvoltage protectionThe A4931 is a complete 3-phase brushless DC motor pre-driver.The device is capable of driving a wide range of N-channelpower MOSFETs and can support motor supply voltages up to30 V. Commutation logic is determined by three Hall-elementinputs spaced at 120 .Other features include fixed off-time pulse width modulation(PWM) current control for limiting inrush current, locked-rotorprotection with adjustable delay, thermal shutdown, overvoltagemonitor, and synchronous rectification. Internal synchronousrectification reduces power dissipation by turning on theappropriate MOSFETs during current decay, thus shortingthe body diode with the low RDS(on) MOSFET. Overvoltageprotection disables synchronous rectification when the motorpumps the supply voltage beyond the overvoltage thresholdduring current recirculation.Package: 28-contact QFN (ET package)The A4931 offers enable, direction, and brake inputs that cancontrol current using either phase or enable chopping. Logicoutputs FG1 and FG2 can be used to accurately measure motorrotation. Output signals toggle state during Hall transitions,providing an accurate speed output to a microcontroller orspeed control circuit.Approximate Scale 1:1Operating temperature range is –20 C to 105 C. The A4931is supplied in a 5 mm 5 mm, 28-terminal QFN package withexposed thermal pad. This small footprint package is lead (Pb)free with 100% matte tin leadframe plating.Typical Application0.1 μF0.1 μF0.1 μF 2 kΩVINCLD HBIASCP1CP2 VCP ENABLEDIRGHBSBGLBGHCSCGLCSENSEGND HA HA– HB HB– HC HC–4931-DS, Rev. 60.1 μF
A49313-Phase Brushless DC Motor Pre-DriverSelection GuidePart NumberA4931METTR-TPackingPackage1500 pieces per reel5 mm x 5 mm, 0.90 mm nominal height QFNAbsolute Maximum RatingsCharacteristicLoad Supply VoltageSymbolNotesVBBMotor Phase OutputSXtw 500 nsHall InputVHxDCLogic Input Voltage RangeVINUnits38V–3V–0.3 to 7V–0.3 to 7VOperating Ambient TemperatureTA–20 to 105ºCMaximum Junction TemperatureTJ(max)150ºCTstg–40 to 150ºCRatingUnits32ºC/W2ºC/WStorage TemperatureRange MRatingThermal CharacteristicsCharacteristicSymbolPackage Thermal Resistance, JunctionRθJAto AmbientPackage Thermal Resistance, JunctionRθJPto Exposed Pad*For additional information, refer to the Allegro website.Test Conditions*4-layer PCB based on JEDEC standardAllegro MicroSystems, LLC115 Northeast CutoffWorcester, Massachusetts 01615-0036 U.S.A.1.508.853.5000; www.allegromicro.com2
A49313-Phase Brushless DC Motor Pre-DriverFunctional Block Diagram0.1 μFCLDLockDetectCP1CP20.1 μFFG1VCPCHARGE PUMP0.1 μFHBIAS2 kΩHA HALLHA-HB HALLVINEnable0.1 BGLBGATEDRIVEHC temLogicDIRRSENSE200 mVENABLEVINGNDTerminal ListNumberName1HA 2HA -3456DescriptionNumberNameDescriptionHall input A15GLBLow side gate drive BHall input A16GLALow side gate drive AHB Hall input B17GHCHigh side gate drive CHB -Hall input B18SCHC Hall input C19GHBHC-Hall input C20SB7GNDGround21GHA8HBIASHall bias power supply output22SA9CP1Charge pump capacitor terminal23FG110CP2Charge pump capacitor terminal24FG2FG 2 speed control output (ΦA input)11VBBSupply voltage25CLDLocked rotor detect timing capacitor12VCPReservoir capacitor terminal26DIR13SENSESense resistor connection27ENABLELogic input – external PWM control14GLCLow side gate drive C28BRAKEZLogic input – motor brake (active low)High side source connection CHigh side gate drive BHigh side source connection BHigh side gate drive AHigh side source connection AFG 1 speed control output (3 Φ inputs)Logic input – motor directionAllegro MicroSystems, LLC115 Northeast CutoffWorcester, Massachusetts 01615-0036 U.S.A.1.508.853.5000; www.allegromicro.com3
A49313-Phase Brushless DC Motor Pre-DriverELECTRICAL CHARACTERISTICS* Valid at TA 25 C, VBB 24 V, unless noted otherwiseCharacteristicsSupply Voltage RangeMotor Supply CurrentSymbolVBBIBBTest ConditionsMin.Typ.Max.Operating8–VBBOVVfPWM 30 kHz, CLOAD 1000 (1)2––VVIN(0)––0.8VHBIASVHBIASHBIAS Current LimitCharge pump on, outputs disabled, Standby modeUnits0 mA IHBIAS 24 mAControl LogicLogic Input VoltageLogic Input CurrentInput Pin Glitch RejectIIN(1)VIN 2 V–1 1.01μAIIN(0)VIN 0.8 V–1 –1.01μAENB pin350500650nsDIR, BRAKEZ pins70010001300nsTo outputs off2.133.9mstGLITCHENB Standby Pulse Propagation DelaytdENBHBIAS Wake-up Delay, Standby ModetdHBIASCHBIAS 0.1 μF–1525μsHigh-Side Gate Drive OutputVGS(H)Relative to VBB, IGATE 2 mA7––VLow-Side Gate Drive OutputVGS(L)IGATE 2 mA7––VGate DriveGate Drive Current (Sourcing)IGate2030–mAGate Drive Pull Down ResistanceRGateGH GL 4 V102840ΩDead Timetdead70010001300nsCurrent Limit Input ThresholdVREF180200220mVFixed Off-TimetOFF182537μsTJTSD155170185 CProtectionThermal Shutdown TemperatureThermal Shutdown HysteresisTJTSDhysVBB UVLO Enable ThresholdVBBUVVBB UVLO HysteresisVCP UVLOLock Detect DurationVBB Overvoltage ThresholdRising VBB141526 C6.277.85V0.40.751VRelative to VBB4.6–6VtlockC 0.1 μF1.522.5sVBBOVRising VBB303337.5VVIN 0.2 to 3.5 V–101μAVBBUVhysVCPUVHall LogicHall Input CurrentIHALLCommon Mode Input RangeVCMR0.2–3.5VAC Input Voltage RangeVHALL60––mVp-pDifference between Hall inputs at transitions– 10,–10–mVTJ 25 C102030mVTJ –20 C to 125 C52040mV–2–μsHall ThresholdsVthHall Threshold HysteresisVHYSPulse Reject FiltertpulseFGFG Output Saturation VoltageFG Leakage CurrentVFG(sat)IFG 2 mA––0.5VIFGlkgVFG 5 V––1μA*Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary forindividual units, within the specified maximum and minimum limits.For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.Specifications throughout the allowed operating temperature range are guaranteed by design and characterization.Allegro MicroSystems, LLC115 Northeast CutoffWorcester, Massachusetts 01615-0036 U.S.A.1.508.853.5000; www.allegromicro.com4
A49313-Phase Brushless DC Motor Pre-DriverLogic States Table (See timing charts, below) X Don’t Care, Z high impedanceInputsConditionDIR 1(Forward)Resulting Pre-Driver OutputsHAHBHCBRAKEZENBA – HILOMotor OutputGHA GLA GHB GLB GHC GLCHILOLOHILOABCLOHILOZB ––HILOHILOLOLOLOHIHIZLOC –HILOLOLOHILOLOHIZHILOD– –HILOLOHIHILOLOLOLOHIZE– HILOLOHILOLOHILOLOZHIF–– HILOLOLOLOHIHILOZLOHIA – HILOLOHIHILOLOLOLOHIZF–– HILOLOLOHILOLOHIZHILOE– HILOHILOLOLOLOHIHIZLOD– –HILOHILOLOHILOLOHILOZC –HILOLOLOLOHIHILOZLOHIB ––HILOLOHILOLOHILOLOZHIFault* ZBrake*XXXLOXLOHILOHILOHILOLOLODIR 0(Reverse)* DIR Don’t CareDIR 1 FORABCDDIR 0 REVEAFHAHAHBHBHCHCFG1FG1SASASBSBSCSCFEDCBAllegro MicroSystems, LLC115 Northeast CutoffWorcester, Massachusetts 01615-0036 U.S.A.1.508.853.5000; www.allegromicro.com5
A49313-Phase Brushless DC Motor Pre-DriverPower-up and Standby Modes Timing DiagramVBBVBBUVChargePumpHBIASVoltagetdENB 3 msStandby ModeTurn off HallBias SupplyENBOutputs EnabledOutputs DisabledOutputs EnabledPower-up and Standby Modes Timing DiagramVBBVBBUVVBB 7.5 s EnabledOutputs DisabledAllegro MicroSystems, LLC115 Northeast CutoffWorcester, Massachusetts 01615-0036 U.S.A.1.508.853.5000; www.allegromicro.com6
A49313-Phase Brushless DC Motor Pre-DriverFunctional DescriptionCurrent Regulation Load current is regulated by an internalfixed off-time PWM control circuit. When the outputs of the fullbridge are turned on, current increases in the motor winding untilit reaches a value, ITRIP , given by:ITRIP 200 mV / RSENSEpletes, in order to provide the blanking function. The blankingtimer is reset when ENB is chopped or DIR is changed. Withexternal PWM control, a DIR change or an ENB on triggers theblanking function. The duration is fixed at 1.5 μs.Synchronous Rectification When a PWM-off cycle is.When ITRIP is reached, the sense comparator resets the sourceenable latch, turning off the source driver. At this point, loadinductance causes the current to recirculate for the fixed off-timeperiod.Enable Logic The Enable input terminal (ENB pin) allowsexternal PWM. ENB low turns on the selected sink-source pair.ENB high switches off the appropriate drivers and the loadcurrent decays. If ENB is held low, the current will rise until itreaches the level set by the internal current control circuit. Typically PWM frequency is in 20 kHz to 30 kHz range. If the ENBhigh pulse width exceeds 3 ms, the gate outputs are disabled. TheEnable logic is summarized in the following table:ENB Pin SettingOutputsOutputs State0OnDrive1Source ChoppedSlow Decay withSynchronousRectification1 for 3 ms typicalOffDisableFixed Off-Time The A4931 fixed off-time is set to 25 μsnominal.PWM Blank Timer When a source driver turns on, a currentspike occurs due to the reverse recovery currents of the clampdiodes as well as switching transients related to distributedcapacitance in the load. To prevent this current spike from erroneously resetting the source Enable latch, the sense comparator isblanked. The blanking timer runs after the off-time counter com-triggered, either by a chop command on ENB or by an internalfixed off-time cycle, load current recirculates. The A4931 synchronous rectification feature turns on the appropriate MOSFETsduring the current decay, and effectively shorts out the bodydiodes with the low RDS(on) driver. This lowers power dissipationsignificantly and can eliminate the need for external Schottkydiodes.Brake Mode A logic low on the BRAKEZ pin activates Brakemode. A logic high allows normal operation. Braking turns on allthree sink drivers, effectively shorting out the motor-generatedBEMF. The BRAKEZ input overrides the ENB input and also theLock Detect function.It is important to note that the internal PWM current control circuit does not limit the current when braking, because the currentdoes not flow through the sense resistor. The maximum currentcan be approximated by VBEMF / RLOAD. Care should be taken toinsure that the maximum ratings of the A4391 are not exceededin the worse case braking situation, high speed and high inertialload.HBIAS Function This function provides a power supply of7.5 V, current-limited to 30 mA. This reference voltage is used topower the logic sections of the IC and also to power the externalHall elements.Standby Mode To prevent excessive power dissipation dueto the current draw of the external Hall elements, Standby modeturns off the HBIAS output voltage. Standby mode is triggeredAllegro MicroSystems, LLC115 Northeast CutoffWorcester, Massachusetts 01615-0036 U.S.A.1.508.853.5000; www.allegromicro.com7
A49313-Phase Brushless DC Motor Pre-Driverby holding ENB high for longer than 3 ms. Note that Brake modeoverrides Standby mode, so hold the BRAKEZ pin high in orderto enter Standby mode.Lock Detect Function The IC will evaluate a locked rotorCharge Pump The internal charge pump is used to generate a The proper commutation sequence is not being followed. Themotor can be locked in a condition in which it toggles betweentwo specific Hall device states.supply above VBB to drive the high-side MOSFETs. The voltage on the VCP pin is internally monitored, and in case of a faultcondition, the outputs of the device are disabled.Fault Shutdown In the event of a fault due to excessivejunction temperature or due to low voltage on VCP or VBB,the outputs of the device are disabled until the fault condition isremoved. At power-up the UVLO circuit disables the drivers.condition under either of these two different conditions: The FG1 signal is not consistently changing.Both of these fault conditions are allowed to persist for periodof time, tlock. tlock is set by capacitor connected to CLD pin. CLDproduces a triangle waveform (1.67 V peak-to-peak) with frequency linearly related to the capacitor value. tlock is defined as127 cycles of this triangle waveform, or:Overvoltage Protection VBB is monitored to determine iftlock CLD 20 s/μFa hazardous voltage is present due to the motor generator pumping up the supply bus. When the voltage exceeds VBBOV , thesynchronous rectification feature is disabled.After the wait time, tlock , has expired, the outputs are disabled,and the fault is latched. These fault conditions can only be clearedby any one of the following actions:Overtemperature Protection If die temperature exceeds Rising or falling edge on the DIR pinapproximately 170 C, the Thermal Shutdown function will disable the outputs until the internal temperature falls below the15 C hysteresis.Hall State Reporting The FG1 pin is an open drain outputthat changes state at each transition of an external Hall element.The FG2 pin is an open drain output that changes state at eachHAx transition. VBB UVLO threshold exceeded (during power-up cycle) ENB pin held high for tlock / 2The Lock Detect function can be disabled by connecting CLD toGND.When the A4931 is in Brake mode, the Lock Detect counter isdisabled.Allegro MicroSystems, LLC115 Northeast CutoffWorcester, Massachusetts 01615-0036 U.S.A.1.508.853.5000; www.allegromicro.com8
A49313-Phase Brushless DC Motor Pre-DriverET Package, 28-Contact QFN0.305.00 0.151.1528120.50281A5.00 0.153.154.803.1529XDSEATINGPLANE0.08 CC4.80C 0.050.25 –0.07PCB Layout Reference View0.90 0.100.50For Reference Only(reference JEDEC MO-220VHHD-1)Dimensions in millimetersExact case and lead configuration at supplier discretion within limits shown 0.200.55 –0.10A Terminal #1 mark areaB3.1521283.15B Exposed thermal pad (reference only, terminal #1identifier appearance at supplier discretion)C Reference land pattern layout (reference IPC7351QFN50P500X500X100-29V1M);All pads a minimum of 0.20 mm from all adjacent pads; adjust asnecessary to meet application process requirements and PCB layouttolerances; when mounting on a multilayer PCB, thermal vias at theexposed thermal pad land can improve thermal dissipation (referenceEIA/JEDEC Standard JESD51-5)D Coplanarity includes exposed thermal pad and terminalsCopyright 2007-2013, Allegro MicroSystems, LLCAllegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required topermit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify thatthe information being relied upon is current.Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause thefailure of that life support device or system, or to affect the safety or effectiveness of that device or system.The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for itsuse; nor for any infringement of patents or other rights of third parties which may result from its use.For the latest version of this document, visit our website:www.allegromicro.comAllegro MicroSystems, LLC115 Northeast CutoffWorcester, Massachusetts 01615-0036 U.S.A.1.508.853.5000; www.allegromicro.com9
The A4931 is a complete 3-phase brushless DC motor pre-driver . The device is capable of driving a wide range of N-channel power MOSFETs and can support motor supply voltages up to 30 V. Commutation logic is determined by three Hall-element inputs spaced at 120 . Other features include fixed off-time pulse width modulation
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characteristics of motor. Permanent magnet brushless DC motor, design and its dynamic performance analysis is done on ANSYS/RM Expert and then its electromagnetic studies has done on ANSYS/Maxwell 3D.In last motor is analyze by varying the lead angle in control circuit. Keywords- highest running Permanent magnet brushless DC motor, FEM method .
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