Lecture 2 – Scaling Trends Borivoje Nikolić

inst.eecs.berkeley.edu/ ee241bEE241B : Advanced Digital CircuitsLecture 2 – Scaling TrendsBorivoje NikolićApple, Huawei Use TSMC, But Their 7nm SoCs Are Different. Whentalking about the most advanced semiconductor manufacturingprocesses, it seems that most of the SoCs in 2019 can be collectivelyclassified as 7nm. But not all 7nm is equal.EE Times, January 22, 2020.EECS241B L02 TECHNOLOGY1

Announcements Sign up for Piazza if you haven’t alreadyEECS241B L02 TECHNOLOGY2

Assigned Reading R.H. Dennard et al, “Design of ion-implanted MOSFET's with very small physical dimensions” IEEEJournal of Solid-State Circuits, April 1974. Just the scaling principles C.G. Sodini, P.-K. Ko, J.L. Moll, "The effect of high fields on MOS device and circuit performance," IEEETrans. on Electron Devices, vol. 31, no. 10, pp. 1386 - 1393, Oct. 1984. K.-Y. Toh, P.-K. Ko, R.G. Meyer, "An engineering model for short-channel MOS devices" IEEE Journal ofSolid-State Circuits, vol. 23, no. 4, pp. 950-958, Aug. 1988. T. Sakurai, A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverterdelay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584 - 594, April1990.EECS241B L02 TECHNOLOGY3

Outline Scaling issues Technology scaling trends Features of modern technologies Lithography Process technologiesEECS241B L02 TECHNOLOGY4

Trends and Challenges inDigital Integrated CircuitDesignEECS241B L02 TECHNOLOGY5

Putting Scaling in PerspectivePerformance gainsover the past decadeLisa Su, HotChips’19 keynoteEECS241B L02 TECHNOLOGYNikolić, Shao Fall 2019 UCB6

Cost Of Developing New Products These are non-recurring (NRE) costs, need to be amortized over the lifetimeof a product We will attempt to dismantle this EECS241B L02 TECHNOLOGY7

Major Roadblocks1. Managing complexityHow to design a 10 billion (100 billion) transistor chip?And what to use all these transistors for?2. Cost of integrated circuits is increasingIt takes 10M to design a chipMask costs are many M in 16nm technology3. Power as a limiting factorEnd of frequency scalingDealing with power, leakages4. Robustness issuesVariations, SRAM, memory, soft errors, signal integrity5. The interconnect problemEECS241B L02 TECHNOLOGY8

Part 1: TechnologyEECS241B L02 TECHNOLOGY9

1.A Scaling TrendsEECS241B L02 TECHNOLOGY10

Power and Performance Trends What do we do next?EECS241B L02 TECHNOLOGY11

What Should We Do?[Graph from “Advancing Computers without Technology Progress”, Hill,Kozyrakis, et al., DARPA ISAT 2012 ]EECS241B L02 TECHNOLOGY12

1.B Scaling IssuesEECS241B L02 TECHNOLOGY13

Key Points Technology scaling (Moore’s law) is slowing down But logic and memory are continuing to scale, possibly at different pace We anyway can’t power up all transistors we can put on a chip Dennard scaling has ended 10 years ago We cover it for understanding of current issues There are many technology flavors available at the moment We need to know what each one brings to us, so we can choose the right one foryour project(may have to wait until the end of the class to figure out all options)EECS241B L02 TECHNOLOGY14

CMOS Scaling Rules (Dennard)Voltage, V / WIRINGtox/ W/ GATEn sourcen drainL/ p substrate, doping *NAxd/ SCALING:Voltage:V/ Oxide:tox / RESULTS:Higher Density:Wire width: W/ Gate length:L/ Higher Speed:Diffusion: xd / Power/ckt:Substrate: * NA Power Density:EECS241B L02 TECHNOLOGY11Å 2 1/ 2 ConstantR. H. Dennard et al.,IEEE J. Solid State Circuits, (1974).15

Research vs. Production Devices10nm device (Intel), circa 2003L g 10 nm10nm node (Intel), IEDM’2017EECS241B L02 TECHNOLOGY16

CMOS Scaling Two 30nm transistors (research and production) 2000 (research)EECS241B L02 TECHNOLOGY 2010 (production)17

Transistors are Changing From bulk to finFET and FDSOI65/55 nm45/40 inFET22/20nm CS241B L02 TECHNOLOGYST,VLSI’1218

Sub-5nm FinFETGateGateSiliconFinSourceBOXDrainSi fin - Body!X. Huang, et al, IEDM’1999.Lee, VLSI Technology, 2006EECS241B L02 TECHNOLOGY19

Beyond 5nm Gate-all-around transistors/nanowiresEECS241B L02 TECHNOLOGYJ. Keller, EECS Colloquium, UC Berkeley, Sept 2019.20

Physical Gate Scaling1010000Nominal feature size1250nm180nm mGate Length0.10.7X every2 years130nm90nm65nm45nm32nm22nm14nm70nm50nm35nm 30nm1000nm100 20202020Changes in slope at 250nm, 45nmEECS241B L02 TECHNOLOGYSource: Intel, IEDM presentations21

Transistor ScalingShrink by 30%28nmC. Auth, VLSI’12“Contacted gate pitch”Shrink by 30%Gate pitch scales 0.7x every nodeIntel45nm32nm22nm14nm10nmContacted gate pitch160nm112.5nm90nm70nm54nmEECS241B L02 TECHNOLOGY22

Pitch ScalingIntel45nm32nm22nm14nm10nmContacted gate pitch160nm112.5nm90nm70nm54nmShrink0.70.80.780.77 Clearly not 0.7 anymore But (Intel 14nm, Natarajan, IEDM’14) Fin pitch: 42nm (0.7x shrink) Metal 0: 56nm ( - ) Metal 1: 70nm (0.78x) Metal 2: 52nm (0.65x)EECS241B L02 TECHNOLOGYIntel’s metric:CPP x MXP0.78 x 0.65 0.5!CPP & FP matter more23

Various Technology flavors Intel 14nmDifferent foundriesFeatureSamsung 14 nm Intel 14 nm TSMC 16 nmFin pitch (nm)4842481/3 fin pitch161416Gate length (nm)Contacted gate pitch(nm)Minimum metal pitch (nm) 30 24 337870906452646T SRAM cell area (µm2)0.080.0590.074EECS241B L02 TECHNOLOGYSource:Tech InsightsEETimes24

Not All Technologies are 44367FF5740305FF5028CPP Contacted poly pitchMxP Minimum metal pitchFP Fin pitchEECS241B L02 TECHNOLOGYTSMCSamsungFPFPSource:A. Wei, TechInsightsIEDM’17, IEDM’19, WikiChip, SemiWiki’2025

ASAP7 Predictive technology kit used in this class None of the above processes, but closeEECS241B L02 TECHNOLOGY26

Ideal vs. Real Scaling Leakage slows down VTh, VDD scaling10000I DSAT [µA/µm]1000Ideal I DSAT100[x10V]V DD10Ideal V DD[ps]T inv1V ThIdeal T invIdeal V Th0.110EECS241B L02 TECHNOLOGY[V]100Lg [nm]100027

Technology Flavors LP keeps drain leakage constantEECS241B L02 TECHNOLOGY28

32nm Technology Flavors (Intel)C.-H. Jan, IEDM’09, P. VanDerVoorn, VLSI Tech’10EECS241B L02 TECHNOLOGY29

5nm FlavorsEECS241B L02 TECHNOLOGYTSMC, IEDM’1930

Lg, R, C scaling1010000Nominal feature size11000250nm0.7X every 2years180nmnm130nm m90nmGate Length65nm45nm0.110032nm70nm22nm50nm35nm 30nm0.0110197019801990200020102020 With scaling L, need to scale up doping - scale junction depth (control leakage) – S/Dresistance goes up External resistance limits currentID VDS / Rchannel Rext EECS241B L02 TECHNOLOGY31

Parasitic Capacitance ScalingReality: Overlap fringe can be 50% of Cchannel in 32nmS. Thompson, Materials Today, 2006.EECS241B L02 TECHNOLOGY32

FinFET FDSOI Intel, VLSI’14 Intel, IEDM’12 ST, VLSI’12 Intel, IEDM’09 TSMC, Samsung Intel, IEDM’17 . Physical Gate Scaling Source: Intel, IEDM presentations Changes in slope at 250nm, 45nm 20nm . External resistance limits current m 10000 1000 100 10 10 1 0.1 0.01 130nm nm 90nm 70nm 50nm Gate Length 65nm 35nm