Chapter 1 Digital Design Using VHDL And PLDs

ECOM 4311Digital System DesignInstructor: Ruba A. SalamahChapter 1Digital Design Using VHDLand PLDs

Reading Text Book:Sections: 1.1, 1.2, 1.3 Assignment#1:Problems: 1.2, 1.9, 1.10, 1.11, 1.142

VHDL/PLD design methodology VHDL is a programming language fordesigning and modeling digital hardwaresystems. Using VHDL with electronic designautomation (EDA) software tools and userprogrammable logic devices (PLDs), we canquickly design, verify, and implement a digitalsystem. We refer to this approach as the VHDL/PLDdesign methodology3

VHDL/PLD design methodologyThe VHDL/PLD design methodology uses: VHDL to describe both the system being designedand the testbench used to verify the design A software simulator tool to simulate the design toverify its functionality and timing A software synthesis tool to create the logicdescribed by the VHDL description A software place-and-route tool to map thesynthesized logic to the target PLD and to generatea timing model and a configuration file A PLD to physically implement the design4

PLDECE 448 – FPGA and ASIC Design with VHDL5

VHDL Model A VHDL model is a textual description of asystem that, when simulated, behaves likethe intended or actual system. Different models may be created torepresent the same system at differentlevels of abstraction (detail). A model at a particular level of abstractionrepresents all the information that isrelevant at that level and leaves out allirrelevant details.6

VHDL/PLD Design flow7

Step1: Requirements Analysis During the requirements analysis phase,the problem that the system is to solve isanalyzed to establish a clear problemdefinition. Any constraints imposed by theenvironment in which the system mustoperate, such as speed of operation andmaximum power consumption; are alsodetermined.8

Step2: Develop Specification Using the requirements analysis documentas a basis, a specification is written thatdefines: The system’s interface to its environment The functions the system must accomplish tosolve the problem. A system specification also includes anyperformance requirements and constraints,such as speed of operation and maximumpower consumption.9

Step3: VHDL Design Description Design description refers to a VHDL program thatcan be synthesized into hardware. A design description can be behavioral orstructural. A behavioral description specifies the computationof output values as a function of input values. In contrast,a structural description is a hierarchicaldescription of interconnected components. For a structural description to be complete, eachcomponent must have an associated behavioraldescription.10

Half Adder Example For a function that is specified by a truth table, we can write thesum of minterms equation for each output. Unlike in traditional design, we would not bother to simplifythese equations, because the synthesizer will automatically dothis for us.11

Design description of a half adder12

Keywords Keywords (reserved words) are words thathave special meaning in VHDL. They canonly be used for the purposes defined bythe language. In the book, keywords in program listingsare boldfaced.13

Statements A design description is composed ofstatements (instructions). A statement is a construct that specifiesone or more actions that are to take place The end of each statement is delimited(marked) by a semicolon.sum (not a and b) or (a and not b);14

Comments Comments are used to clarify a program. They areinvaluable to others who must read and understandour programs and to ourselves when we return to aprogram after a considerable amount of time. A comment starts with two hyphens and continuesto the end of the line. There is no block comment feature in VHDL. Comments in programs in the book are italicized-- Declare signals to assign values to and to observesignal a tb, b tb, sum tb, carry out tb : std logic;15

Context Clause A context clause, consists of a library clause anda use clause. A library clause is required when objects that arenot predefined in the VHDL language, but aredefined in a library, are used. The half-adder program uses a data type calledstd logic for its input and output signals.This datatype is defined in the package STD LOGIC 1164in the library ieee.library ieee; -- Context clauseuse ieee.std logic 1164.all;16

Design Entity The simplest VHDL design descriptionsconsist of a single design entity. A design entity can represent all or a portionof a design. A design entity has well-defined inputs andoutputs and performs a well-defined function. A design entity consists of two parts: an entity declaration and an architecture body. These two parts can be placed in the samefile, or they can be placed in separate files.17

Entity Declaration An entity declaration gives a design entity itsname and describes its interface (input andoutput signals). The entity declaration in provides informationsimilar to that provided by the block diagramof circuit. An entity declaration starts with the keyword entity, followed by theentity’s name.18

Ports A design entity’s input and output signals are calledports and are listed in the entity declarationfollowing the keyword port. The type of data each port transfers is alsospecified. A signal’s data type determines the values thesignal may have and the operations that can beperformed on those values. Type std logic provides nine different values torepresent a logic signal. This allows a more detailed representation of alogic signal’s state than does type bit. Both types include the values '0' and '1'.19

Architecture Body An architecture body starts with the keyword architecturefollowed by the name given to the architecture. Followingthe keyword of is the name of the entity declaration withwhich the architecture is associated. A design entity’s architecture describes either the entity’sbehavior or its structure. In the half adder example the architecture is written in astyle called dataflow, which describes a system’s behaviorin terms of how data flows through the system.architecture dataflow of half adder is-- Architecture bodybeginsum (not a and b) or (a and not b);carry out a and b;end dataflow;20

Concurrent Signal AssignmentStatementssum (not a and b) or (a and not b);carry out a and b; Each of the previous concurrent signal assignmentstatements assigns a new value to the signal on the lefthand side of the signal assignment symbol ( ) wheneverthere is an event on one of the signals on the right-handside of the assignment symbol. The signal assignment statement is said to be sensitive tothe signals on the right-hand side of the statement. The symbol is read as “gets.” So, the secondassignment statement is read as :''carry out gets a and b.'‘ the signal assignment symbol ( ), are called compounddelimiters.21

Execution Order of ConcurrentStatements A concurrent signal assignment statement executes only inresponse to an event on one or more of the signals to which itis sensitive. The order of execution of concurrent signal assignmentstatements is determined by the order of events on the signalsto which the concurrent statements are sensitive. In the following concurrent statements:sum (not a and b) or (a and not b);carry out a and b; if there is an event on signal a, both assignment statements areexecuted simultaneously to determine new values for sum andcarry out. These statements are called concurrent because they allow thepossibility of simultaneous execution, which they must if theyare going to model the operation of logic circuits. It creates a distinction between VHDL and the sequentialexecution of statements in a conventional programminglanguage.22

Sequential Statements VHDL also has sequential statements, like those inconventional programming languages. VHDL’s sequential statements can only appear insidea process statement or a subprogram. As a result, when reading a program it is easy todetermine from its location whether a statement isconcurrent or sequential. A process statement is a concurrent statement thatcontains a sequence of sequential statements.proc1: process (a, b, c)beginx a and b and c;End process proc1;23

Sequential vs. Concurrent24

Design Description Compilation A VHDL design description is compiled like aprogram written in a conventional programminglanguage, such as C or Ada. VHDL compilers are sometimes called analyzers.The term “analyze” means to check a design file forsyntax and static semantic errors before it issimulated. This term is sometimes used instead of the term“compile,” because compiling typically means togenerate executable object code. In contrast, codegeneration for VHDL was initially associated onlywith simulation. Analyzed VHDL code is stored in an intermediateform in a library for subsequent simulation25

Syntax Errors Semantic errors are violations of the meaning of thelanguage. Static semantic errors are errors in meaning thatcan be detected by a compiler before a simulationis performed. dynamic semantic errors can only be detectedduring simulation. For example, if we have a signal assignmentstatement where the left-hand and righthand sidesare the same type, but during execution thecomputed value of the righthand side is outside theallowed range of values for that type26

Verification Using Simulation Three types of simulation: Functional simulation Post-synthesis (gate-level) simulation Timing (post-route) simulation There are three approaches to generatingstimulus: interactive (manual) command line Testbench.27

Finally!!?Any Question28

VHDL/PLD design methodology VHDL is a programming language for designing and modeling digital hardware systems. Using VHDL with electronic design automation (EDA) software tools and user programmable logic devices (PLDs), we can quickly design, verify, and implement a digital system. W