CIC IP CoreUser Guide - Cornell University
CIC IP CoreUser GuideSubscribeSend FeedbackUG-CIC2014.12.15101 Innovation DriveSan Jose, CA 95134www.altera.com
TOC-2ContentsAbout The CIC IP Core.1-1Altera DSP IP Core Features. 1-1CIC IP Core Features.1-1CIC IP Core Device Family Support. 1-2DSP IP Core Verification.1-2CIC IP Core Release Information.1-2CIC IP Core Performance and Resource Utilization. 1-3CIC IP Core Getting Started. 2-1Installing and Licensing IP Cores. 2-1OpenCore Plus IP Evaluation. 2-1CIC IP Core OpenCore Plus Timeout Behavior. 2-2IP Catalog and Parameter Editor.2-2Specifying IP Core Parameters and Options.2-3Files Generated for Altera IP Cores.2-4Simulating Altera IP Cores in other EDA Tools. 2-7DSP Builder Design Flow.2-8CIC IP Core Functional Description. 3-1Variable Rate Change Factors. 3-2Multichannel Support. 3-2Multiple Input Single Output (MISO). 3-2Single Input Multiple Output (SIMO). 3-3Output Options. 3-4Output Data Width.3-4Output Rounding.3-5Hogenauer Pruning. 3-6FIR Filter Compensation Coefficients. 3-6CIC IP Core Parameters.3-7CIC IP Core Interfaces and Signals. 3-9Avalon-ST Interfaces in DSP IP Cores. 3-10CIC IP Core Signals. 3-11Avalon-ST Interface Data Transfer Timing. 3-12Packet Data Transfers.3-12Document Revision History.4-1Altera Corporation
1About The CIC IP Core2014.12.15UG-CICSubscribeSend FeedbackThe Altera CIC IP core implements a cascaded integrator-comb (CIC) filter with data ports that arecompatible with the Avalon Streaming (Avalon-ST) interface. CIC filters (also known as Hogenauerfilters) are computationally efficient for extracting baseband signals from narrow-band sources usingdecimation. They also construct narrow-band signals from processed baseband signals usinginterpolation.CIC filters use only adders and registers; they require no multipliers to handle large rate changes.Therefore, CIC is a suitable and economical filter architecture for hardware implementation, and is widelyused in sample rate conversion designs such as digital down converters (DDC) and digital up converters(DUC).Altera DSP IP Core Features Avalon Streaming (Avalon-ST) interfacesDSP Builder readyTestbenches to verify the IP coreIP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulatorsCIC IP Core Features Interpolation and decimation filters with variable rate change factors (2 to 32,000), a configurablenumber of stages (1 to 12), and two differential delay options (1 or 2). Single clock domain with selectable number of interfaces and a maximum of 1,024 channels. Selectable data storage options with an option to use pipelined integrators. Configurable input data width (1 to 32 bits) and output data width (1 to full resolution data width). Selectable output rounding modes (truncation, convergent rounding, rounding up, or saturation) andHogenauer pruning support. Optimization for speed by specifying the number of pipeline stages used by each integrator. Compensation filter coefficients generation. IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators. DSP Builder ready. 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.www.altera.com101 Innovation Drive, San Jose, CA 95134ISO9001:2008Registered
1-2UG-CIC2014.12.15CIC IP Core Device Family SupportCIC IP Core Device Family SupportAltera offers the following device support levels for Altera IP cores: Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.The IP core meets all functional requirements, but might still be undergoing timing analysis for thedevice family. You can use it in production designs with caution. Final support—Altera verifies the IP core with final timing models for this device family. The IP coremeets all functional and timing requirements for the device family. You can use it in productiondesigns.Table 1-1: Device Family SupportDevice FamilySupportArria II GXFinalArria II GZFinalArriaVFinalArria10FinalCyclone IV GXFinalStratix IV GTFinalStratix IV GX/EFinalStratix VFinalOther device familiesNo support DSP IP Core VerificationBefore releasing a version of an IP core, Altera runs comprehensive regression tests to verify its qualityand correctness. Altera generates custom variations of the IP core to exercise the various parameteroptions and thoroughly simulates the resulting simulation models with the results verified against mastersimulation models.CIC IP Core Release InformationTable 1-2: CIC IP Core Release InformationItemDescriptionVersion14.1Release DateDecember 2014Ordering CodeIP-CICProduct ID(s)00BBVendor ID(s)6AF7Altera CorporationAbout The CIC IP CoreSend Feedback
UG-CIC2014.12.15CIC IP Core Performance and Resource Utilization1-3Altera verifies that the current version of the Quartus II software compiles the previous version of each IPcore. Altera does not verify that the Quartus II software compiles IP core versions older than the previousversion. The Altera IP Release Notes lists any exceptions.Related Information Altera IP Release Notes Errata for CIC IP core in the Knowledge BaseCIC IP Core Performance and Resource UtilizationThe following parameters apply: Number of stages: 8Rate change factor: 8Differential delay: 1Integrator data storage: Memory (whenever possible)Differentiator data storage: Memory (whenever possible)Input data width: 16Output data width: Full precisionOutput rounding: No roundingThe target fMAX is 1 GHz.Table 1-3: CIC IP Core PerformanceTypical performance using the Quartus II software with the Arria V (5AGXFB3H4F40C4), Cyclone V(5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devicesDeviceFilter TypeMemoryALMM10KM20KRegistersPrimarySecondaryfMAX (MHz)Arria V Decimator4932--1,1495207.34Arria V Decimator 5Channels1,1622--3,7496207Arria V Decimator 5Channels 3Interfaces91137--1,7226255Arria V Decimator352Hogenauer Pruning1--78512304Arria V DecimatorTrunction4632--1,0555198.69Arria V Decimator VariableRate Change91937--1,7307256Arria V Interpolator3261--72818320Arria V Interpolator 5Channels7621--2,36927288About The CIC IP CoreSend FeedbackAltera Corporation
1-4UG-CIC2014.12.15CIC IP Core Performance and Resource UtilizationDeviceFilter TypeMemoryALMM10KM20KRegistersPrimarySecondaryfMAX (MHz)Arria V Interpolator 5Channels 3Interfaces88627--1,77617232.61Arria V InterpolatorConvergentRounding3521--78512304Arria V InterpolatorVariable RateChange88927--1,77223235Cyclone DecimatorV4922--1,13717182Cyclone Decimator 5VChannels1,1622--3,7488190.15Cyclone Decimator 5VChannels 3Interfaces90637--1,7199204Cyclone Decimator352VHogenauer Pruning1--78414246Cyclone DecimatorVTruncation4632--1,0544177Cyclone Decimator VariableVRate Change91737--1,7305193.27Cyclone InterpolatorV3241--70937264Cyclone Interpolator 5VChannels7601--2,38311235Cyclone Interpolator 5VChannels 3Interfaces89027--1,74748168Cyclone clone InterpolatorVVariable 1,1526377StratixVDecimator 5Channels1,176--13,7508413Altera CorporationAbout The CIC IP CoreSend Feedback
UG-CIC2014.12.15CIC IP Core Performance and Resource UtilizationDeviceFilter TypeStratixVDecimator 5Channels ndaryfMAX (MHz)--115,5628450.05Decimator361Hogenauer 11,0594376StratixVDecimator VariableRate 73714450.05StratixVInterpolator 5Channels771--02,3908450StratixVInterpolator 5Channels a 10 InterpolatorVariable RateChangeAbout The CIC IP CoreSend Feedback1,891Memory1-5Altera Corporation
CIC IP Core Getting Started22014.12.15UG-CICSubscribeSend FeedbackInstalling and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for your production use without purchasingan additional license. Some Altera MegaCore IP functions require that you purchase a separate licensefor production use. However, the OpenCore feature allows evaluation of any Altera IP core in simulationand compilation in the Quartus II software. After you are satisfied with functionality and perfformance,visit the Self Service Licensing Center to obtain a license number for any Altera product.Figure 2-1: IP Core Installation Pathacdsquartus - Contains the Quartus II softwareip - Contains the Altera IP Library and third-party IP coresaltera - Contains the Altera IP Library source code IP core name - Contains the IP core source filesNote: The default IP installation directory on Windows is drive :\altera\ version number ; on Linux it is home directory /altera/ version number .Related Information Altera Licensing Site Altera Software Installation and Licensing ManualOpenCore Plus IP EvaluationAltera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation andhardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to takeyour design to production. OpenCore Plus supports the following evaluations: Simulate the behavior of a licensed IP core in your system.Verify the functionality, size, and speed of the IP core quickly and easily.Generate time-limited device programming files for designs that include IP cores.Program a device with your IP core and verify your design in hardware. 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.www.altera.com101 Innovation Drive, San Jose, CA 95134ISO9001:2008Registered
2-2UG-CIC2014.12.15CIC IP Core OpenCore Plus Timeout BehaviorOpenCore Plus evaluation supports the following two operation modes: Untethered—run the design containing the licensed IP for a limited time. Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires aconnection between your board and the host computer.Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design timesout.CIC IP Core OpenCore Plus Timeout BehaviorAll IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. Ifthere is more than one IP core in a design, the time-out behavior of the other IP cores may mask the timeout behavior of a specific IP core .All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. Ifthere is more than one IP core in a design, a specific IP core's time-out behavior may be masked by thetime-out behavior of the other IP cores. For IP cores, the untethered time-out is 1 hour; the tethered timeout value is indefinite. Your design stops working after the hardware evaluation time expires. The QuartusII software uses OpenCore Plus Files (.ocp) in your project directory to identify your use of the OpenCorePlus evaluation program. After you activate the feature, do not delete these files.When the evaluation time expires, the data output signal goes low.Related Information AN 320: OpenCore Plus Evaluation of MegafunctionsIP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools IP Catalog) and parameter editor help you easily customize andintegrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,and generate files representing your custom IP variation.Note: The IP Catalog (Tools IP Catalog) and parameter editor replace the MegaWizard Plug-InManager for IP selection and parameterization, beginning in Quartus II software version 14.0. Usethe IP Catalog and parameter editor to locate and paramaterize Altera IP cores. The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch theparameter editor and generate files representing your IP variation. The parameter editor prompts you tospecify an IP variation name, optional ports, and output file generation options. The parameter editorgenerates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in yourproject. You can also parameterize an IP variation without an open project.Use the following features to help you quickly locate and select an IP core: Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have noproject open, select the Device Family in IP Catalog. Type in the Search field to locate any full or partial IP core name in IP Catalog. Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core'sinstallation folder, and view links to documentation. Click Search for Partner IP, to access partner IP information on the Altera website.Altera CorporationCIC IP Core Getting StartedSend Feedback
UG-CIC2014.12.15Specifying IP Core Parameters and Options2-3Figure 2-2: Quartus II IP CatalogShow IP only for target deviceSearch for installed IP coresDouble-click to customize, right-click fordetailed informationNote: The IP Catalog is also available in Qsys (View IP Catalog). The Qsys IP Catalog includesexclusive system interconnect, video and image processing, and other system-level IP that are notavailable in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, referto Creating a System with Qsys in the Quartus II Handbook.Specifying IP Core Parameters and OptionsYou can quickly configure a custom IP variation in the parameter editor. Use the following steps tospecify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parametersand Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.1. In the IP Catalog (Tools IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variationsettings in a file named your ip .qsys. Click OK.3. Specify the parameters and options for your IP variation in the parameter editor, including one ormore of the following. Refer to your IP core user guide for information about specific IP coreparameters.CIC IP Core Getting StartedSend FeedbackAltera Corporation
2-4UG-CIC2014.12.15Files Generated for Altera IP Cores4.5.6.7.8.9. Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications. Specify parameters defining the IP core functionality, port configurations, and device-specificfeatures. Specify options for processing the IP core files in other EDA tools.Click Generate HDL, the Generation dialog box appears.Specify output file generation options, and then click Generate. The IP variation files generateaccording to your specifications.To generate a simulation testbench, click Generate Generate Testbench System.To generate an HDL instantiation template that you can copy and paste into your text editor, clickGenerate HDL Example.Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. Ifyou are prompted to manually add the .qsys file to the project, click Project Add/Remove Files inProject to add the file.After generating and instantiating your IP variation, make appropriate pin assignments to connectports.Figure 2-3: IP Parameter EditorView IP portand parameterdetailsSpecify your IP variation nameand target deviceApply preset parameters forspecific applicationsFiles Generated for Altera IP CoresThe Quartus II software generates the following IP core output file structure:Altera CorporationCIC IP Core Getting StartedSend Feedback
UG-CIC2014.12.15Files Generated for Altera IP Cores2-5Figure 2-4: IP Core Generated Files project directory your ip .qsys - System or IP integration file your ip .sopcinfo - Software tool-chain integration file your ip your ip n testbench tbIP variation filesIP variation filestestbench system your ip tb.qsysTestbench system file your ip .cmp - VHDL component declaration file your ip bb.v - Verilog HDL black box EDA synthesis file your ip inst.v or .vhd - Sample instantiation template your ip .ppf - XML I/O pin information file testbench tbtestbench files your ip .qip - Lists IP synthesis files your testbench tb.csv your ip .sip - Contains assingments for IP simulation files your testbench tb.spd your ip generation.rpt - IP generation report your ip .debuginfo - Contains post-generation information your ip .html - Connection and memory map datasimsimulation files your ip .bsf - Block symbol schematic your ip .spd - Combines simulation scripts for multiple cores EDA tool setupscripts simsynthSimulation filesIP synthesis files your ip .v or .vhdTop-level simulation file EDA tool name Simulator scripts simulator setup scripts ip subcores nSubcore libraries your ip .v or .vhdTop-level IP synthesis filesynthSubcoresynthesis filessimSubcoreSimulation files HDL files HDL files Table 2-1: IP Core Generated FilesFile NameDescription my ip .qsysThe Qsys system or top-level IP variation file. my ip is the namethat you give your IP variation. system .sopcinfoDescribes the connections and IP component parameterizations inyour Qsys system. You can parse its contents to get requirementswhen you develop software drivers for IP components.Downstream tools such as the Nios II tool chain use this file.The .sopcinfo file and the system.h file generated for the Nios II toolchain include address map information for each slave relative to eachmaster that accesses the slave. Different masters may have a differentaddress map to access a particular slave component.CIC IP Core Getting StartedSend FeedbackAltera Corporation
2-6UG-CIC2014.12.15Files Generated for Altera IP CoresFile NameDescription my ip .cmpThe VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that you can use in VHDLdesign files. my ip .htmlA report that contains connection information, a memory mapshowing the address of each slave with respect to each master towhich it is connected, and parameter assignments. my ip generation.rptIP or Qsys generation log file. A summary of the messages during IPgeneration. my ip .debuginfoContains post-generation information. Used to pass System Consoleand Bus Analyzer Toolkit information about the Qsys interconnect.The Bus Analysis Toolkit uses this file to identify debug componentsin the Qsys interconnect. my ip .qipContains all the required information about the IP component tointegrate and compile the IP component in the Quartus II software. my ip .csvContains information about the upgrade status of the IP component. my ip .bsfA Block Symbol File (.bsf) representation of the IP variation for usein Quartus II Block Diagram Files (.bdf). my ip .spdRequired input file for ip-make-simscript to generate simulationscripts for supported simulators. The .spd file contains a list of filesgenerated for simulation, along with information about memoriesthat you can initialize. my ip .ppfThe Pin Planner File (.ppf) stores the port and node assignments forIP components created for use with the Pin Planner. my ip bb.vYou can use the Verilog black-box ( bb.v) file as an empty moduledeclaration for use as a black box. my ip .sipContains information required for NativeLink simulation of IPcomponents. You must add the .sip file to your Quartus project. my ip inst.v or inst.vhdHDL example instantiation template. You can copy and paste thecontents of this file into your HDL file to instantiate the IP variation. my ip .regmapIf the IP contains register information, the .regmap file generates.The .regmap file describes the register map information of masterand slave interfaces. This file complements the .sopcinfo file byproviding more detailed register information about the system. Thisenables register display views and user customizable statistics inSystem Console.Altera CorporationCIC IP Core Getting StartedSend Feedback
UG-CIC2014.12.15Simulating Altera IP Cores in other EDA ToolsFile Name my ip .svd2-7DescriptionAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.During synthesis, the .svd files for slave interfaces visible to SystemConsole masters are stored in the .sof file in the debug section.System Console reads this section, which Qsys can query for registermap information. For system slaves, Qsys can access the registers byname. my ip .vorHDL files that instantiate each submodule or child IP core forsynthesis or simulation. my ip .vhdmentor/Contains a ModelSim script msim setup.tcl to set up and run asimulation.aldec/Contains a Riviera-PRO script rivierapro setup.tcl to setup and run asimulation./synopsys/vcsContains a shell script vcs setup.sh to set up and run a VCS simulation./synopsys/vcsmxContains a shell script vcsmx setup.sh and synopsys sim.setup file toset up and run a VCS MX simulation./cadenceContains a shell script ncsim setup.sh and other setup files to set upand run an NCSIM simulation./submodulesContains HDL files for the IP core submodule. child IP cores /For each generated child IP core directory, Qsys generates /synth and /sim sub-directories.Simulating Altera IP Cores in other EDA ToolsThe Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supportedEDA simulators. Simulation involves setting up your simulator working environment, compilingsimulation model libraries, and running your simulation.You can use the functional simulation model and the testbench or example design generated with your IPcore for simulation. The functional simulation model and testbench files are generated in a projectsubdirectory. This directory may also include scripts to compile and run the testbench. For a complete listof models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.NativeLink launches your preferred simulator from within the Quartus II software.CIC IP Core Getting StartedSend FeedbackAltera Corporation
2-8UG-CIC2014.12.15DSP Builder Design FlowFigure 2-5: Simulation in Quartus II Design FlowDesign Entry(HDL, Qsys, DSP Builder)Altera SimulationModelsQuartus IIDesign FlowGate-Level SimulationAnalysis & SynthesisFitter(place-and-route)TimeQuest Timing AnalyzerRTL SimulationEDANetlistWriterPost-synthesis functionalsimulation netlistPost-synthesisfunctionalsimulationPost-fit functionalsimulation netlistPost-fit functionalsimulationPost-fit timingsimulation netlist(Optional)Post-fitPost-fit timingtimingsimulationsimulation(3)Device ProgrammerNote: Post-fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the currentversion of the Quartus II software. Altera IP supports a variety of simulation models, includingsimulation-specific IP functional simulation models and encrypted RTL models, and plain textRTL models. These are all cycle-accurate models. The models support fast functional simulation ofyour IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores,only the plain text RTL model is generated, and you can simulate that model. Use the simulationmodels only for simulation and not for synthesis or any other purposes. Using these models forsynthesis creates a nonfunctional design.Related InformationSimulating Altera DesignsDSP Builder Design FlowDSP Builder shortens digital signal processing (DSP) design cycles by helping you create the hardwarerepresentation of a DSP design in an algorithm-friendly development environment.This IP core supports DSP Builder. Use the DSP Builder flow if you want to create a DSP Builder modelthat includes an IP core variation; use IP Catalog if you want to create an IP core variation that you caninstantiate manually in your design. For more information about the DSP Builder flow, refer to theAltera CorporationCIC IP Core Getting StartedSend Feedback
UG-CIC2014.12.15DSP Builder Design Flow2-9Related InformationUsing MegaCore Functions chapter in the DSP Builder Handbook.CIC IP Core Getting StartedSend FeedbackAltera Corporation
CIC IP Core Functional Description32014.12.15UG-CICSubscribeSend FeedbackYou can select either a decimation or interpolation CIC filter. A decimation CIC filter comprises acascade of integrators (integrator), followed by a down sampling block (decimator) and a cascade ofdifferentiators (called the differentiator or comb section). Similarly an interpolation CIC filter comprises acascade of differentiators, followed by an up sampling block (inte
101 Innovation Drive, San Jose, CA 95134. CIC IP Core Device Family Support Altera offers the following device support levels for Altera IP cores: Preliminary support—Altera verifies the IP co
U-CIC/U-CIC-M model Completely-in-canal. YOUR WIDEX HEARING AID (To be filled out by the hearing care professional) Vent: Short Full length None CIC CIC-M Your hearing aid series: 2. PROGRAM Universal Audibility Extender Quiet Audibility Extender
Project Report Yi Li Cornell University yl2326@cornell.edu Rudhir Gupta Cornell University rg495@cornell.edu Yoshiyuki Nagasaki Cornell University yn253@cornell.edu Tianhe Zhang Cornell University tz249@cornell.edu Abstract—For our project, we decided to experiment, desig
CIC Business Manager - Supervisor CIC Business Manager - Supervisor Accessing Business Manager The Business Manager - Supervisor program will be installed separately on your computer from the CIC Client. To open the Business Manager application you will need to launch the pro-Note: gram from the start menu or by double clicking the icon.
Aman Agarwal Cornell University Ithaca, NY aa2398@cornell.edu Ivan Zaitsev Cornell University Ithaca, NY iz44@cornell.edu Xuanhui Wang, Cheng Li, Marc Najork Google Inc. Mountain View, CA {xuanhui,chgli,najork}@google.com Thorsten Joachims Cornell University Ithaca, NY tj@cs.cornell.edu AB
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Georg.Hoffstaetter@Cornell.edu - October 19, 2020 -American Linear Collider Workshop 1 Ongoing and potential Cornell contributions to the EIC Potential ILC contributions from Cornell Georg Hoffstaetter for Cornell Laboratory for Accelerator Based Sciences and Education Cornell has experience in using CESR to study wiggler-dominated ILC
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