NET 50/20M Jumpers And Components - Digi International
NET 50/20M Jumpersand Components90000282 C
NET 50 Jumpers andComponents GuidePart number/version: 90000282 CRelease date: March 2006www.digi.com
2001-2006 Digi International Inc.Printed in the United States of America. All rights reserved.Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, a DigiInternational Company, NET , NET OS and NET Works are trademarks or registered trademarks of DigiInternational, Inc. in the United States and other countries worldwide. All other trademarks are theproperty of their respective owners.Information in this document is subject to change without notice and does not represent a committmenton the part of Digi International.Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including,but not limited to, the implied warranties of, fitness or merchantability for a particular purpose. Digi maymake improvements and/or changes in this manual or in the product(s) and/or the program(s) describedin this manual at any time.This product could include technical inaccuracies or typographical errors. Changes are made periodicallyto the information herein; these changes may be incorporated in new editions of the publication.Digi International11001 Bren Road EastMinnetonka, MN 55343 U.S.A.United States: 1 877 912-3444Other locations: 1 952 912-3444www.digi.com/supportwww.digi.com
ContentsChapter 1:H a r d w a r e D e s c r i p t i o n .1Features of the development board . 2Chip select configuration. 2Jumpers and single DIP switch SW2. 3Connectors. 4DIP switches .Switch 5 .Switch 6 .Switch 3 .Switch 4 .55566Expansion plugs . 7Ethernet interface. 8MIC (IEEE1284, GPIO, and ENI interfaces) .1284 parallel port ENI interface .GPIO interface .ENI/DPO interface .9999Protype breadboard area . 10Chapter 2:S c h e m a t i c s . 11Chapter 3: NET Works Development Board Bill ofM a t e r i a l s . 27BOM — NET 50 development board. 28iii
Using This GuideReview this section for basic information about this guide, as well as forgeneral support contact information.v
About this guideThis guide provides information about the jumpers and components of theNET 50 development board. The NET 50, part of the Digi NET ARM line of SoC(System-on-Chip) products, supports any type of high bandwidth application inIntelligent Networked Devices.The NET ARM chip is part of the NET Works integrated product family, whichincludes the NET OS network software suite.Who should read this guideThis guide is for hardware developers, system software developers, andapplication programmers who want to use the NET 50 for development.To complete the tasks described in this guide, you must: Understand the basics of hardware and software design, operatingsystems, and microprocessor design.Understand the NET 50 architecture.What’s in this guideThis table shows where you can find information in this guide:viTo read aboutSeeA description of the NET Works developmentboard hardwareChapter 1, “Hardware Description”The NET 50 board schematicsChapter 2, “Schematics”The bill of materials (BOM) for the NET 50development boardChapter 3, “Bill of Materials”NET 5 0JumpersandComponentsGuide
Conventions used in this guideThis table describes the typographic conventions used in this guide:This conventionIs used foritalic typeEmphasis, new terms, variables, and document titles.bold, sans serif typeMenu commands, dialog box components, and otheritems that appear on-screen.Select Menu optionmonospaced typeMenu commands. The first word is the menu name; thewords that follow are menu selections.Filenames, pathnames, and code examples.Related documentation For information about the chip you are using, see the NET 50 HardwareReference. For information about third-party products and other components, reviewthe documentation CD-ROM that came with your development kit.Documentation updatesDigi occasionally provides documentation updates on the Web site.Be aware that if you see differences between the documentation you receivedin your NET Works package and the documentation on the Web site, the Website content is the latest version.Customer supportTo get help with a question or technical problem with this product, or to makecomments and recommendations about our products or documentation, use thecontact information listed in the table shown next.www.digi.comvii
viiiForContact informationTechnical supportTelephone: 1 877 912-3444/ 1 952 912-3456Fax: 1 952 912-4960Documentationtechpubs@digi.comDigi home pOnline problem reportingwww.digi.com/problemreporting.jspNET 5 0JumpersandComponentsGuide
Hardware DescriptionCHAPTER1This chapter provides a hardware description of the NET Works developmentboard. In addition, this chapter describes how to configure the base address foreach chip select, DIP switches, and the 1284 parallel port and ENI interfaces.The board is identifiable by this information: Market name. NET Works Development Board Part number. 6127030 Test reference. S2NCCTPThe NET 50 consists of a 208 plastic-quad-flat-pack (PQFP) package and a 208 ballgrid-array (BGA) package. A high-performance, highly-integrated 32-bit chip, theNET 50 is designed for use in intelligent network devices and Internet appliances.1
Hardware DescriptionFeatures of the development boardThe NET Works development board provides these basic features: 44.3 MHz NET 50 (BGA).The NET 50 BGA development board supports applications using the NET 50QFP processor. 18.432 MHz crystal, with option for external oscillator. ARM JTAG ICE port. Six LED indicators: two each on PORT C, PORT B, and the Ethernet connector. 2 ASYNC 1 Mbps serial ports, one with RS485 option, user selectable. 10/100BaseT Ethernet port. 8Kx8 EEPROM, expandable to 32Kx8. Serial EEPROM standard (64K, 8192x8, SPI part on GPIO pins). 16Mb DRAM. 2MB flash, expandable to 16 MB. MIC Port (GPIO, IEEE1284, ENI) interface connector. Bootstrap configuration DIP switches. Expansion board plugs. All NET ARM bus signals are brought out. TEK Mictor headers for logic analyzer connections. Large breadboard area.Chip select configurationThe peripheral devices are connected to specific chip selects on the NET ARM chip.The base address for each chip select must be configured using NET ARM internalregisters, as listed in this table:2NET 50JumpersandComponentsGuide
Hardware DescriptionChip selectPeripheralMaximum sizeCS0Flash16 MBCS1SDRAM16 MBCS2Expansion connector256 KBCS3Parallel EE (default) or expansion connector32 KB (default) or 256 KBCS4Expansion connector256 KBTable 1: Chip select configurationJumpers and single DIP switch SW2This table defines the jumpers and DIP switch designations:JumperPurposeJP1Serial port B 232 1-2 (default); 485 2-3JP2Serial port B 232 ON (default); 485 OFF (on a single pin only)SW2Serial port B 232 1-4 ON, 5-8 OFF (default); 485 1-4 OFF, 5-8 ONP5-P6x16 vs x 32 bit SDRAM configuration - SDRAM x32 (default)P7-P9x16 vs x 32 bit flash configuration - flash x16 (default)Table 2: Jumpers and DIP switcheswww.digi.com3
Hardware DescriptionConnectorsThis table defines the connectors and their designations:Reference numberTypePurposeJ1/J2Mini/din jackPower connector - 5 pin din populatedJ3RJ45 MAG-jack10/100 BT Ethernet with LEDsJ4-8Mictor 38 pinTEK configured emulator headersP1DB9 maleSerial port A RS232, 1 Mbps, full modem supportP2DB9 maleSerial port B RS232, 1 Mbps or RS485P3Header 2x7ARM ICE portP4Header 1x6Manufacturing test plugP10Header 50 pinMIC port interface - IDC or PCB to PCBP11Header 60 pinExpansion interface D31:16 - IDC or PCB to PCBP12Header 60 pinExpansion interface D15:00 - IDC or PCB to PCBTable 3: ConnectorsThis information applies to P10, P11, and P12: 4Mating connectors:—Nanoflex high density connectors—Yamaichi (search for part number or nfs); http://www.yamaichi.us/PBC socket:—P10 (change 50 to 60 for P11-P12)—nfs-50-1314xxICD socket with strain relief:—P10 (change 50 to 60 for P11-12—nfs-50A-0111NET 50JumpersandComponentsGuide
Hardware DescriptionDIP switchesA group of four 8-position DIP switches is provided for: Configuring the NET ARM Selecting Write or Read enable Selecting MIC port: Either ENI/DPO or IEEE1284 or GPIO modesThe tables in this section give details about each switch.In all cases, normal default position.Switch 5PositionFunctionOffOn1PULINTNormalENI pulsed interrupt out2EPACKNormalENI flow control ACK*3ReservedNormalReserved4DMAENormalENI DMA lines enabled5I 0CNormalENI interrupt TTL6DINT2NormalENI pulsed interrupt in7WR OCNormalENI wait/ACK TTL8PSIONormalEnable PSIO ENI modeTable 4: Switch 5Switch 6PositionFunctionOffOn1ReservedNormal32-bit BUS for NET 122 GEN ID9ID0NormalFactory default3 GEN ID10ID1NormalManufacturing testTable 5: Switch 6www.digi.com5
Hardware DescriptionPositionFunctionOffOn4 GEN ID11ID2NormalSpare5 GEN ID12ID3NormalParallel ports bit 06 GEN ID13ID4NormalParallel ports bit 17 GEN ID14ID5NormalForce download mode8 GEN ID15ID6Media type bit 0Normal MIITable 5: Switch 6Switch 3PositionFunctionOffOn1 GEN ID16ID7Media type bit 1Normal MII2 GEN ID17ID8Serial ports bit 0Normal two3 GEN ID18ID9Serial ports bit 1Normal two4 GEN ID19ID10NormalSpare5PCM0MIC mode bit 0Normal GPIO6PCM1MIC mode bit 1Normal GPIO7PCM2MIC mode bit 2Normal GPIO8CS00NormalCS0 bootTable 6: Switch 3Switch 4PositionFunctionOffOn1CS01NormalCS0 32 bit flash boot2EARBNormalExternal bus arbiter3ARMDNormalARM disableTable 7: Switch 46NET 50JumpersandComponentsGuide
Hardware DescriptionPositionFunctionOffOn4LENDNormalLittle Endian5FWRITEFlash write disableNormal6FRREADFlash Read disableNormal7SP7NormalSpare (NC)8SP8NormalSpare (NC)Table 7: Switch 4Expansion plugsThe two 60-pin plugs bring out the entire NETARM system bus, including ports A:C.Some signals have on-board use, but option resistors allow even these to be broughtout. If a 16-bit data bus is required, only P11 needs to be attached. Devices thatinterface to this connector must have 3V signaling levels. The inputs to theNET ARM are not 5V-tolerant.The P11 expansion plug is a 16 bit bus; the P12 expansion plug provides theadditional 16 bits for a 32 bit bus.This table shows the functions for P11:Signal nameFunctionVCC or 3.3V5.0V @ 500 mA or 3.3V 300 mA (includes both P11 P12)A7:0Address lines (up to 256 KB)D31:16Data lines upperBE3:2Byte enable lines upperCS2*, CS4*Chip selectsCS3*Chip select used by parallel EE (R71 isolates)OE*, WE*, RW*Chip select directionCASI*Used by SDRAMTable 8: P11 functionswww.digi.com7
Hardware DescriptionSignal nameFunctionRESET*Hardware reset input to NETARMPORTA7:0Used on board (R57, 58, 59, 14, 143,34,26,25 isolates)PORTB7:0Used on board (R29, 39, 31, 80, 16, 20, 17, 21 isolates)PORTC7, PORTC5Used on board (R121 and R90 isolates)Table 8: P11 functionsThis table shows the functions for P12:Signal nameFunctionVCC or 3.3V5.0V @ 500V or 3.3V 300mA (includes both P11 P12)A27:8Address lines (up to 256MB)D15:0Data lines lowerBE1:0*Byte enable lines lowerTA*, TEA*Bus controlTS*No connectBR*, BG*, BUSY*No connectPORTC6 or CAS0*Used on board (R162 113 or R161 selects or isolates)PORT4:3Used on board (R122, 144 isolates)PORTC2Used on board (R163 5 or R164 selects or isolates)PORTC1Used on board (166 7 or R165 selects or isolates)PORTC0Used on board (R79 isolates)Ethernet interfaceThe 10/100 version of the development board provides a full-duplex 10/100MbitEthernet interface using the Intel (formerly Level1) 3V PHY in a BGA package, whichuses the standard MII interface.8NET 50JumpersandComponentsGuide
Hardware DescriptionThe RJ45 connector is integrated with the isolation transformer, EMI filtercomponents, link, and receive LEDs.You also can use the MII interface to determine the current Ethernet link status.Change of link status can cause an interrupt on IRQ0*.The Intel 3V PHY Reset* signal can be connected to the NET ARM PORTB4 GPIOsignal or hardware reset using option resistors. The PORTB4 (R80) signal can bedriven low to provide a hard reset to the PHY. Current population uses hardwarereset (R75).The Intel PHY PHYINT* signal is connected to the NET ARM PORTC0 IRQ0* signal. ThePORTC0 input can be configured to generate an interrupt on the high to lowtransition of PHYINT*. Using this interrupt is not a requirement.MIC (IEEE1284, GPIO, and ENI interfaces)You can configure the development board to operate using either the IEEE1284parallel ports, GPIO mode, or the ENI interface. You can use one interface at a time.1284 parallel port ENI interfaceExternal glue logic is required to use the IEEE1284 interface. See the IEEE1284section in the Hardware Reference Guide. This is a multiplexed interface that usesone 74FCT16646 per port. All inputs require 5V to 3.3V translation.GPIO interfaceThere are 16 I/O pins and 16 input only pins. Inputs can be set to cause an interruptor can be polled. Most outputs have 2ma drive with the exception of PORTF7, whichhas 8ma drive. Signals PBD15:8 should have no connections in GPIO mode.ENI/DPO interfaceIf you use a cable to connect to connector P10, the cable should be three inches orshorter. A data buffer may be required. This buffer can be controlled by ENI signalsPBRW*(DIR) and PEN*(OE*).www.digi.com9
Hardware DescriptionProtype breadboard areaThis area provides space for:10 2 SIOC16 or SIOC14 ICs 4 SOT23-6, SOT23-5, SOT23-4. Discretes in the 1206 package Minidip 8 pin through hole IC GND connection points 3.3V connection pointsNET 50JumpersandComponentsGuide
SchematicsCHAPTER2This chapter provides the schematics for the NET Works development board.11
Schematics60 PINSCS2, CS3 & CS4PORT AD31:16.PORT BNETARM EXPANSIONPORT C3.3VD15:0R12.5VSB7SB85V3.3V450 PINSMIC PORT:ENI/GPIO,IEEE12843.3V3.3VBURST TERM.8PORT BPORT CGPIO F7 GATESGPI G40SW4-62FLASHWRITEENABLE8PORT AGPIO DDIP SWITCHESON8*MIC PORTADDR. LINE BOOTSTRAPONGPI H2WE-, CS-CAS1-, CS1-NET 20M - 10/100MIC NOTMACAVAILABLEBGAMII31 ADDR/CONT'L1825MHzRST-RESET P.B.3.3VD31:0A27:0CONT'L LINESRESET*ANDMAX811NET 20M/50BGA/PQFPBUF3.3V10/100 BTXNET 20M PORTS B & C,"PICK ANY 8".*MIC Multi Interface ControllerFLASHREADENABLE32 DATA LINESORPHY INT. (C0)LXT971 PHYSB5RST-SW3, SW4, SW5, SW63.3VGPIO RESET PHY( B4)SB65VBCLK5JTAGALL NET ARMP11(EXP)R167P3 14 PINXTAL2STANDARD. x16(1MB) or x32(2MB)P10(MIC)R160DEBUGCS0 FLASH MEMORY, x16(1-8MB) or x32( 2-16MB)CS1 SDRAM MEMORY, x16(8 MB) or x32(16MB)LNKLEDMAGJACK64K, 8192x8P10SW4-5SER. EEGPIO(A4)SB9RECLED3.3VSW2, JP1, JP2RIA*ENI / IEEE1284LDOP11J3 RJ45RS485(C1)FB5LDO60 PINSRS232(C2)P12CUST. LEDS CPU LEDSP2 DB9-M(B0)RS2325VJ2 DIN(B2)P1 DB9-MPOWER IN - ARD SAME2.5VCS3 PARALLEL EE, x8(2-32KB)CORE, PLL1/O44.2368MHz3.3VSD CLKSTANDARD 8K x 8(5) MICTOR EMILATOR HEADERS - 38 PIN12NET 50PROTOTYPING AREA - (2)SIOC16,(4)SOT23-6, (8)1206, (1)MINIDIP-8,GND & POWER POINTS.JumpersandNetSilicon - A Digi International CompanyTitleNET50/20M Dev. Brd. Block DiagramSizeBDocument NumberDate:Monday, September 09, 2002RevANET20M 50BD.DSNComponentsSheetGuide1of1
SchematicsCONFIDENTIAL MATERIAL TO NetSilicon - A Digi International CompanyNOTES:1. ALL RESISTOR VALUES ARE IN OHMS AND IN THE 0603 SIZE UNLESS OTHERWISE NOTED2. ALL RESISTOR VALUES ARE 5% UNLESS OTHERWISE NOTED3. ALL CAPACITORS ARE RATED IN uFARADS AND IN THE 0603 SIZE UNLESS OTHERWISE NOTED4. ALL CAPACITORS ARE RATED AT 50 VDC OR HIGHER UNLESS OTHERWISE NOTED5. L AST USED:PROPRIETARY DOCUMENTPROPERTY OF NETSILICON, INC., NOT TO BE REPRODUCEDBY ANY MEANS OR USED TO FURNISH INFORMATION TO OTHERSWITHOUT THE EXPLICIT CONSENT OF NETSILICON, INC.ALL RIGHTS GLOBAL FUDUCIALSFIDFIDZ1Z2Z3Z4NCNCNCNCMT 125MT 125MT 125MT 125TOOLING HOLESBOARD REVISIONSN20M50Bga04/18/02 1951000 REV A07/23/02 1951001 REV BDEVELOPMENT BOARDBOARD REV NOTESREB B PCB incorperates REV B SH.13 correctionSHEET REV NOTESSh.02 Rev B: Updates PORT DescriptionsSh.04 Rev B: Updates Table 1 C1 to C22Sh.08 Rev B: Updates Note for RTSB* 1K pull-down.SHEET DESCRIPTIONSh.09 Rev B: Updates Note for TXD3:0 Resistors - Sh.01 to Rev CSh.12 Rev B: Changes 2.5 regulator Capacitor C10 from 4.7 to 10uF LESRSh.13 Rev B: Swapped mis-connected 3.3V & GND pins on U16SH. # CRIPTIONCover SheetPort & Chip Select InformationNETARM BGA & BCLK BufferEmulator Hdrs., Jtag, & Addr. BuffersFlash, Parallel & Serial EE MemorySDRAM Memory1Mbps Serial Port A(1)1Mbps Serial Port B(2) or RS485Ethernet Front End; 10/100BaseTXENI/GPIO PortSystem Bus Expansion Conn. & DipswitchesPower Supply, Breadboard Area, & LEDsNETARM PQFPREF SCH1951001DE SIGNER: Don StoneNetSilicon - A Digi International Company, Waltham, MATitleNET ARM 20M/50 COVER SHEETSizeDocument NumberDate:Thur sday, September 05, 2002Revn20m50b01.SCHSheetwww.digi.comC1of1313
SchematicsPort A - High Speed RS232 Serial Port with Modem SupportChip Selects0DCD* Serial port 11CTS* Serial port 12DSR* Serial port 13RxDSerial port 14Burst Terminate (0 Outside arms burst terminate fix)5RTS* Serial port 16DTR* Serial port 17TxDSerial port 1All 8 bits go to Expansion Connector and can be disabled for off-board use.CS0CS1CS2CS3CS4Flash Memory, x16 or x32, 1-16MbytesSDRAM Memory, x16 or x32, 8-16MbytesSpare to Expansion ConnectorParallel EE Memory & to Expansion ConnectorSpare to Expansion ConnectorFlash Write and Read are separately controlled bydipswitchLarger SDRAM Support can be done on Daughter Board.CS1 can be disabled on board.Port B - High Speed RS232 Serial Port or RS4850General Purpose LED, (0 Outside LED on)1CTS* Serial port 22General Purpose LED, (0 Outside LED on)3RxDSerial port 2/RS485 Input4Reset PHY, (0 Outside reset. Board is Strapped for Hardware RESET)5RTS*Serial port 2/ RS485 Driver Enable, (1 Outside Enable)6DTR* Serial port 2/ RS485 Receiver Enable, (0 Outside Enable)7TxDSerial port 2/ RS485 OutputAll 8 bits go to Expansion Connector and can be disabled for off-board use.ENI Port ( NET 50 Only)All Supported GPIO's go to ENI ConnectorSupports ENI mode (Data Buffer if required, canbe added on daughter board)Port C - Serial EE Memory0Interrupt from PHY (input)1CPU LED Green, (0 Outside LED on)2CPU LED Yellow, (0 Outside LED on)3Serial EE Clock (output) or AMUX4Serial EE (data input)5Serial EE (data output)6RIA* Serial port 1(Or Serial EE Clock output)7Serial EE chip select, (0 Outside selected)All 8 bits go to Expansion Connector and can be disabled for off-board use.For NET 20M to NET 20UM migration only eight(8) of thesixteen(16) combined PORTB and PORTC pins should beused.NetSilicon - A Digi Internation
bold, sans serif type Menu commands, dialog box components, and other items that appear on-screen. Select Menu option Menu commands. The first word is the menu name; the words that follow are menu selections. monospaced type Filenames, pathnames, and code examples.
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2 August 2015 Page 3 www.showsec.co.nz Ribbon & Prize Allocation Event Height Entries Ribbons to: Jumpers A1 Maxi 39 4th (108 dogs) Medium 48 5th Mini/Micro 21 2nd Jumpers B1 Maxi 43 4th (103 dogs) Medium 39 4th Mini/Micro 21 2nd Jumpers C1 Maxi 48 5th (119 Mediumdogs) 32 3rd Mini 24 2nd Micro 15 2nd Jumpers A2 Maxi 39 4th (107 dogs) Medium 47
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Dec. 16th 2013 FANUC A-97606_0715E_02 2/7 High wrist payload type of M-20i A/20M Higher wrist payload from 20kg to 35kg The smart robot can be applied in handling applications with narrow space Enhance wrist moment by 2 2.4 times, and wrist inertia by 1.5 2 times for M-20i A/20M Same kinematics and same engineering with M-20i A/20M
Dec. 16th 2013 FANUC A-97606_0715E_02 2/7 High wrist payload type of M-20i A/20M Higher wrist payload from 20kg to 35kg The smart robot can be applied in handling applications with narrow space Enhance wrist moment by 2 2.4 times, and wrist inertia by 1.5 2 times for M-20i A/20M Same kinematics and same engineering with M-20i A/20M
Cushcraft R-7 Vertical Antenna for 10M/15M/20M/40M Cushcraft R-5 Vertical Antenna for 10M/15M/20M (SARC has two of these.) 6M Dipole 10M Dipole 15M Dipole 20M Dipole 75M Dipole (second one) G5RV Antenna Finance and Review – Paul Guido, N5IUT, has not
ASP.NET, and Oracle Data Provider for .NET (ODP.NET). ODP.NET is a native .NET data access provider for Oracle databases. It offers standard ADO.NET data access for .NET Framework 1.x, 2.0, and higher. For developers who have used another ADO.NET provider, basic ODP.NET data access requires very little new to learn.
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