Chapter Virtuoso Layout Editor - University Of Utah
Chapter5Virtuoso Layout Editor
68CHAPTER 5: Virtuoso Layout EditorFigure 5.1: Inverter schematicFigure 5.2: Inverter symbol
69(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.3: Dialog for creating a Layout View of the inverter cellFigure 5.4: Initial nactive rectangle
70CHAPTER 5: Virtuoso Layout EditorFigure 5.5: nactive rectangle with measurement rulers
71(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.6: Create contact dialog box
72CHAPTER 5: Virtuoso Layout EditorFigure 5.7: nactive showing source and drain connectionsFigure 5.8: Nmos transistor 3µ wide and 0.6µ long
73Figure 5.9: A pmos transistor 6µ wide and 0.6µ long
74CHAPTER 5: Virtuoso Layout EditorFigure 5.10: A pmos transistor inside of an NWELL region(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.11: Extra features dialog box in move mode
75(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.12: Dialog box for the path command
76CHAPTER 5: Virtuoso Layout EditorFigure 5.13: Inverter layout with input and output connections made
77Figure 5.14: Inverter layout with power supply connections
78CHAPTER 5: Virtuoso Layout EditorFigure 5.15: Inverter layout with well and substrate connections
79(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.16: Shape pin dialog box
80CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.17: Final inverter layout
81(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.18: Layout with four inverter instances
82CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.19: Layout with four inverter instances expanded to see all levels of layout
83(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.20: Submit Plot dialog box
84CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.21: Plot Options dialog boxFigure 5.22: Nmos transistor layout (with DRC errors)
85(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.23: DIVA DRC control window
86CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.24: Results from the DRC in the CIW windowFigure 5.25: Nmos transistor layout (with DRC errors flagged)
87(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.26: Explanation of DRC violation(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.27: Finding all DRC violations
88CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.28: DIVA extraction control window
89(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.29: DIVA extraction special switches
90CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.30: DIVA extraction result in the CIW
91(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.31: Extracted view of the inverter
92CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.32: DIVA LVS control window
93(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.33: DIVA LVS Control Form(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.34: NCSU form to modify LVS rules
94CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.35: DIVA LVS completion indication
95(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.36: DIVA LVS output
96CHAPTER 5: Virtuoso Layout Editor(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.37: DIVA LVS output (scrolled)
97(Copyright c 2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)Figure 5.38: DIVA LVS Run Information window
98CHAPTER 5: Virtuoso Layout Editor
68 CHAPTER 5: Virtuoso Layout Editor Figure 5.1: Inverter schematic Figure 5.2: Inverter symbol
Virtuoso Layout Editor This tutorial will cover the basic steps involved in using the Cadence layout editor called Virtuoso, extracting layout, and running simulation on the created layout. The inverter layout is used as an example in the
Part One: Heir of Ash Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 Chapter 25 Chapter 26 Chapter 27 Chapter 28 Chapter 29 Chapter 30 .
1. Creating layout with Virtuoso layout XL (VXL) We will be using PCELLs developed by NCSU to layout a 2 inputs nand gate, denoted as nand2. If you are not running CDS tools, do so according to Lab 1. First we need to create a layout view of our nand2. Go to the library manager and execute
For schematic-based designs, try the AMS Designer Virtuoso use model: AMS Designer Virtuoso use model For analog-centric designs, run the AMS Designer simulator from the Virtuoso Analog Design Environment (ADE) using the OSS netlister and irun. Both use models feature the simulation front end (SFE) parser, which is the same parser that
TO KILL A MOCKINGBIRD. Contents Dedication Epigraph Part One Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Part Two Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18. Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 Chapter 25 Chapter 26
All 13 Layouts use White Daisy CS for bases, so you will need 26 sheets for your layouts. Whisper CS #3 4 x 12 Layout B 4 x 12 Layout B 4 x 12 Layout C Whisper CS #4 4 x 12 Layout C 4 x 12 Layout C 4 x 12 Layout C Saffron Letter B&T #1 (letters facing sideways) 6 x 10 ½ Layout A 6 x 8 Layout A 6 x 4 Layout K 6 x 1 ½ Cricut
8 Virtuoso Layout Integration Analysis Group FDTD/MODE Virtuoso Layout Suite direct bridge Layer Builder Design Challenges: Users need to define layouts in both layout editor and FDTD/MODE solvers, which is time-consuming Inconsistency between two layouts is difficult to resolve Exporting GDS to FDTD/MODE does not support parametric analysis Goal: Facilitate component design .
Archaeological Investigations and Recording 1994-2011 by David James Etheridge with scientific analysis by Dr David Dungworth Avon Archaeological Unit Limited Avondale Business Centre, Woodland Way, Kingswood, Bristol, BS15 1AW Bristol 2012 Illustration taken from the ‘Annales des Mines” Vol 10, dated 1825 . William Champion’s Warmley Brass and Zinc works, Warmley, South Gloucestershire .
