Performance Analysis Of Different 8x8 Bit CMOS Multiplier Using 65nm .

International Journal of Computer Applications (0975 – 8887)Volume 148 – No.13, August 2016Performance Analysis of Different 8x8 Bit CMOSMultiplier using 65nm TechnologySona RaniAjay KumarVikas SinglaRakesh SinglaDepartment ofElectronics andCommunicationYadavindra College ofEngineeringTalwandi Sabo, IndiaLecturerDepartment ofElectronics andCommunicationShaheed Bhagat SinghState Technical Campus(PW), Ferozepur, IndiaAssistant ProfessorDepartment ofInformation TechnologyMalout Institute ofManagement &Information TechnologyMalout, Punjab, IndiaLecturerDepartment ofInformation TechnologyBaba Hira Singh BhattalInstitute of Engg. &Technology (PW),Lehragaga, Distt.Sangrur, IndiaABSTRACTIn this paper different low power 8x8 bit multipliers which areimplemented with Tanner Tool v13.0 at 250MHz and500MHz frequency with 65nm technology which is having asupply voltage 1.0v. There are different CMOS multipliercircuits are analyzed which are Array multiplier, Wallace treemultiplier, Row bypass Braun multiplier, Column bypassBraun multiplier, Row and Column bypass Braun multiplierand these multiplier are realized using bridge style full adder.All these multipliers are compared in terms of delay, powerdissipation and power delay product. Simulation results showthat the Array multiplier and Wallace tree multiplier usingbridge style adder has less power delay product and is fasteras compared to other CMOS multipliers.A number of approaches have been adopted to implement amultiplier circuit with low transistor count, low powerconsumption, high speed etc. The basic and typical arraymultiplier performs multiplication by arranging the full-addersto add the partial products for each output bit [4].Power dissipation is the most important parameter for CMOScircuits and it is classified into dynamic and static powerdissipation. Dynamic dissipation is due to charging anddischarging load capacitances as gates switch and “shortcircuit” current while both pMOS and nMOS stacks arepartially ON [5]. Static dissipation is due to sub thresholdleakage through OFF transistors, gate leakage through gatedielectric, and junction leakage from source/drain diffusions.Putting this together gives the total power of a circuitKeywordsCMOS, PDP, VLSI, Multiplier, Array multiplier, WallaceTree, Braun bypass multiplier.1. INTRODUCTIONMultiplication put up in a variety of applications in most ofthe Digital Signal Processing (DSP) applications. In highspeed digital signal processing (DSP) and image processingmultiplier play a vital role. With the rapid development ofmobile computing and battery-powered system as well as theenergy conservation consideration, low power VLSI designhas become a very important issue in the VLSI industry.Higher power and energy dissipation in high performancesystems require more expensive packaging and coolingtechnologies, increase cost, and decrease system reliability.[1] The multiplier is the arithmetic operation unit formicroprocessors and many DSP applications, such as filtering,convolution, Fast Fourier Transform (FFT), etc [2].Hence, it is very important to develop low-power multipliersto enhance the performance of overall system. Therefore lowpower multiplier design has been an important part in lowpower VLSI system design. Also these low power designsystems reduce cooling cost and increase the reliability ofhigh density designs. With the recent advances in technology,many researchers have tried to implement increasinglyefficient multiplier. They aim at offering low powerconsumption, high speed and reduced delay. [3]. This paperproposes and evaluates the technique to reduce the powerdissipation of multipliers. Various techniques at the differentlevels of the design process have been implemented to reducethe power dissipation at the circuit, architectural and systemlevel.Ptotal Pdynamic Pstatic V2dd.fclk.CL.α α/12 (Vdd – 2Vth)3 tr/tf IleakageVddWhere fclk is the system clock frequency, CL is the loadcapacitance, α is the switching activity factor, tr/, tf is the riseand fall time of input signal, Ileakage is the total leakage currentflowing through the device . The dynamic power of CMOScircuits is becoming a major concern in the design of devices[6]. In this paper we optimize the dynamic power of multipliercircuits.In this paper low power Array multiplier, Wallace treemultiplier and Braun multiplier with bypassing techniques arepresented and modified adder module is implemented for alow power high speed multipliers. The full adder circuit isbasic block of multiplier circuit. In these multiplier bridgestyle full adder cell [13] is used which has less powerdissipation as compare to static adder.2. MULTIPLIER ARCHITECTUREThe multipliers have a predominant effect on the systemperformance, many high performance algorithms andarchitectures have been proposed [7].Some of architecture ofmultipliers are explained below:-2.1 Array multiplierBraun multiplier is a simple parallel multiplier and it isgenerally known as carry save array multiplier and in a n nbit Braun multiplier, the multiplier array consists of (n-1)rows of carry-save adders (CSAs) and a (n-1) bit ripple-carryadder in the last row, in which each row contains (n-1) fulladder (FAs). Array multiplier has a regular structure .It is easy1

International Journal of Computer Applications (0975 – 8887)Volume 148 – No.13, August 2016to layout and also it has small size. The design time of anarray multiplier is much less than other multipliers [8].Fig.3: 4-bit Braun Multiplier with Row Bypassing2.4 Braun Multiplier with ColumnBypassingFig.1: 4x4 bit Braun multiplier2.2 Wallace tree multiplierIn Wallace tree multiplier architecture, all the bits of all of thepartial products in each column are added together by a set ofadders in parallel without propagating any carries. The entireprocedure is carried out into three steps: partial product (PP)generation, partial product grouping & reduction, and finaladdition. [9].Partial products6543First stage210654(a)FA543210 Bit position210(b)Second stage6In column bypassing technique an addition operation ofcolumn can be disabled if the corresponding bit in themultiplicand is 0. In this multiplier FA is only attached by twotri-state buffers and one 2-to-1 multiplexer [11], so themodified FA is simpler than that of used in the row bypassingmultiplier.Final adder32106543HA(c)(d).Fig.2: Dot diagram of 4-bit Wallace tree multiplierIn a Wallace multiplier, the number of partial productsgenerated is the same as in the Array Multiplier. Thus thereare still N2 AND gates required for an N-bit by N-bitmultiplication. The main disadvantage of Wallace multiplieris its irregular layout. Due to used carry-save operations, itreduced the delay time2.3 Braun Multiplier with Row BypassingThe particular rows of adders is bypassed when the multiplierbit is zero in the basic multiplier array in Row bypassingtechnique to save the switching power. The Braun multiplierwith row bypassing uses additional three tri-state buffers andtwo 2-to-1multiplexers and these are attached to FA cell[10]. The extra correcting circuits must be added in thismultiplier to correct the multiplication result.Fig.4: 4-bit Braun Multiplier with Column BypassingIt also eliminates the extra correcting circuit. So it uses lesshardware as compare to row bypass multiplier.2.5 Braun Multiplier with Row and ColumnBypassingIn Row and Column Bypassing technique the additionoperation in the (i 1)-th column or the j-th row can bebypassed if the bit, ai in the multiplicand is 0 or the bit, bj inthe multiplier is 0. In this the (i 1, j) FA can be bypassed ifthe product, aibj, is 0 and the carry bit, ci,j-1, is 0, that is, asthe product, aibj, is 1 or the bit, ci,j-1, is 1, the additionoperation in the (i 1, j) FA can be executed [12].Simplification of full adders is done for the additionoperation. The simplified adder, A 1, in the CSA array isattached by one tri-state buffer and two 2-to-1 multiplexersand simplified adder, A B 1, in the CSA array is attached bytwo tri-state buffers and two 2-to-1 multiplexers.2

International Journal of Computer Applications (0975 – 8887)Volume 148 – No.13, August 2016.Fig.8: Circuit Diagram of Tristate BufferFig.5: 4-bit Braun Multiplier with Row and ColumnBypassingFig.9: Circuit Diagram of 2:1 MuxFig.6: (a) A 1 Adder (b) A B Adder (c) A B 1 Adder3. PROPOSED MULTIPLIER DESIGNIn this paper, we design and analyze different multiplier withbridge style full adder cell [13]. It has the less PDP ascompared with conventional static adder. Due to the minimumtime delay of sum and carry out, the adder enhance the overallperformance of multipliers. Circuit diagram of full adder, subcircuits and different multiplier design are shown in Fig. 7 toFig. 17.Fig.10: A 1 adderFig.11: A B 1 adderFig.7: Circuit Diagram of bridge style one bit full adderFig.12: XOR gate3

International Journal of Computer Applications (0975 – 8887)Volume 148 – No.13, August 2016Fig.13: Circuit Diagram of 8-bit Array multiplierFig.14: Circuit Diagram of 8-bit Wallace tree multiplierFig.15: Circuit Diagram of 8-bit Row Bypass BraunMultiplierFig.16: Circuit Diagram of 8-bit Column Bypass Braunmultiplier4

International Journal of Computer Applications (0975 – 8887)Volume 148 – No.13, August 2016Table2: Average Power dissipation, Delay and PowerDelay Product comparision of 8-bit multiplier at Power DelayProduct(pJ)500MhzArray .0294.79848.119Row BypassingBraun Multiplier31.7573.657116.135ColumnBypassingBraun aun Multiplier33.2064.749157.695Table3:Transistors Count of different 8 bit multipliersType of MultiplierTransistorCountFig.17: Circuit Diagram of 8-bit Row and Column BypassBraun multiplierArray Multiplier(conventional)1952Braun (Array) Multiplier1648Wallace Tree Multiplier1648Row Bypassing Braun Multiplier5046Column Bypassing BraunMultiplier3622Row And Column BypassingBraun Multiplier41964. SIMULATION RESULTSSimulations are performed using 65nm CMOS technology.Spice simulation are carried out with supply voltage 1V and atdifferent frequency 250MHz and 500MHz. For all possibleinput combination sets applicable to the multiplier, I havecalculated the average power consumption, delay, and powerdelay product. All result of different multipliers aresummerised in the form of table which are described below:Table1: Average Power Dissipation, Delay and PDPcomparision of 8-bit multiplier at 250MHzofPower(mw)FrequencyDelay(ns)Power DelayProduct(pJ)250MhzArray 79252.906TreeRow BypassingBraun Multiplier24.1217.647184.453ColumnBypassing BraunMultiplier11.4969.625110.649Row and ColumnBypassing BraunMultiplier25.7359.751250.942PDP (pJ)TypeMultiplier300250200150100500PDP(pJ) at250MhzPDP(pJ) at500MhzFig.18: Comparison of PDP for different 8-bit multiplier at250MHz and 500MHz5. CONCLUSIONThis paper analysis comparative study of some of the wellknown existing multiplier named as Braun multiplier, Wallacetree multiplier, Row bypass Braun multiplier, Column bypass5