A 0.029-mm 17-fJ/Conversion-Step Third-Order CT Σ And Second-Order .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. XX, NO. XX, XXXX 20181A 0.029-mm2 17-fJ/Conversion-StepThird-Order CT Σ ADC With a Single OTAand Second-Order Noise-Shaping SAR QuantizerJiaxin Liu, Student Member, IEEE, Shaolan Li, Student Member, IEEE, Wenjuan Guo, Member, IEEE,Guangjun Wen, Senior Member, IEEE, and Nan Sun, Senior Member, IEEEAbstract—This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma ( Σ) ADCwith a single operational transconductance amplifier (OTA).A 4-bit second-order fully passive noise-shaping successiveapproximation-register (SAR) analog-to-digital converter (ADC)is employed as the quantizer while inherently provides twoadditional noise shaping orders. Fabricated in 40nm CMOS, theprototype occupies 0.029 mm2 of active area and consumes 1.16mW of power when clocked at 500 MHz sampling frequency.The proposed CT Σ ADC achieves a peak signal-to-noise-anddistortion ratio (SNDR) of 70.4 dB over 12.5 MHz bandwidth,yielding a Walden figure of merit (FoM) of 17 fJ/conversion-step.QHE CT Σ ADC is a suitable architecture for highresolution, low-power, and wide-bandwidth applications.Comparing to its discrete-time (DT) counterpart, the CT ΣADC is preferred owing to its relaxed integrator settling requirement and inherent anti-alias filtering capability. A typicalCT Σ ADC is shown in Fig. 1(a), which consists of aloop filter, a feedback digital-to-analog converter (DAC), anda quantizer. There are three common ways to boost the signalto-quantization-noise ratio (SQNR) of a Σ ADC. First,the oversampling ratio (OSR) can be enlarged by increasingthe sampling frequency fs ; however, this directly increasesthe power consumption. Second, the loop filter order canbe increased to achieve more aggressive noise shaping, butthis comes with the cost of increased circuit complexity andTThis work was supported by NSF under Grant 1254459, 1509767, and1527320. (Corresponding author: Nan Sun.)Jiaxin Liu is with School of Information and Communication Engineering,University of Electronic Science and Technology of China, Chengdu, Sichuan611731 China. He was a visiting PhD student in Department of Electricaland Computer Engineering, The University of Texas at Austin, Austin, TX78712 USA. He is now also a postdoctoral researcher in Department ofElectrical Engineering, Tsinghua University, Beijing 100084 China. (e-mail:jiaxin.liu@ieee.org).Guangjun Wen is with School of Information and Communication Engineering, University of Electronic Science and Technology of China, Chengdu,Sichuan 611731 China. (e-mail: wgj@uestc.edu.cn)Shaolan Li, Wenjuan Guo and Nan Sun are with Department of Electricaland Computer Engineering, The University of Texas at Austin, Austin, TX78712 USA. (e-mail: nansun@mail.utexas.edu).LoopFilterV inDoutDAC(a)(1-z -1)QfsLoopFilterVinDout-Index Terms—analog-to-digital converter (ADC), continuoustime (CT) delta-sigma ( Σ) ADC, successive approximationregister (SAR), hybrid ADC, passive noise-shaping, excess loopdelay compensation (ELDC), coefficient scaling, low-noise andhigh-speed comparator.I. I NTRODUCTIONfsDAC(b)Fig. 1. (a) A typical CT Σ ADC; (b) a CT Σ ADC with a noise-shapingquantizer.degraded loop stability. The third approach is to increase thequantizer resolution, but it comes with its own limitation. Aflash quantizer is often limited to 4-bit because its hardwarecost (power, area and complexity) increases exponentially withthe number of bits [1]–[3]. By contrast, a SAR quantizer ismore energy efficient for moderate resolution as its hardwarecost scales linearly with the number of bits. However, whenused inside a wide-band closed-loop Σ ADC, the SARquantizer resolution is limited to 6-bit or below due to itsspeed constraint [4]–[10].An effective solution to address the quantizer resolutionlimitation is to embed noise-shaping (NS) capability inside thequantizer. This way, the quantizer can achieve higher in-bandresolution with a relatively small nominal resolution. A modelof a CT Σ ADC with a first-order NS quantizer is shownin Fig. 1(b). Comparing to Fig. 1(a), the difference is that thequantization error in Fig. 1(b) is shaped before injecting intothe main loop. Fig. 2 shows the simulated SQNRs of a 7-bitconventional quantizer and a 4-bit NS quantizer as well asthe cases of embedding them in a first-order and second-orderloop filters. It can be seen that the 4-bit NS quantizer canoutperform the 7-bit conventional quantizer by oversampling,owing to its inherent NS capability. With the additional NSorder provided by the quantizer, the requirement on the loopfilter order, the sampling frequency, and the quantizer nominalDigital Object Identifier: 10.1109/JSSC.2018.28799551558-173X c 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. XX, NO. XX, XXXX 2018110Standalone 7-bit quantizer1st-order LF 7-bit quantizer2nd-order LF 7-bit quantizerStandalone 4-bit NS quantizer1st-order LF 4-bit NS quantizer2nd-order LF 4-bit NS quantizer100SQNR [dB]90807060504030248OSR1632Fig. 2. Simulated SQNRs with conventional and NS quantizers.resolution of the Σ ADC can be greatly relaxed. Having saidthat, a NS quantizer does not come for free; however, as longas its cost can be made small, it is an attractive alternative toboost the ADC resolution.Due to their merits, there have been emerging efforts inthe research community to develop novel NS quantizers [11]–[21]. The noise-shaped integrating quantizer (NSIQ) proposedin [11] achieved first-order NS, but it requires an active OTA.Thus, the total number of OTAs in the Σ ADC is unchanged;it is still the same as the NTF order. Moreover, it requires a fastcounting clock whose frequency increases exponentially withthe resolution. Although the speed and resolution trade-off canbe alleviated by incorporating a digital back-end integratoras in [12], the Gm -C integrator inside the quantizer requirescalibration to ensure robustness against process, voltage, andtemperature (PVT) variations. To obviate the need for OTAsthat are scaling incompatible and power hungry, voltage controlled oscillator (VCO) based NS quantizer has been proposedin [13]–[19]. It is mostly digital and thus scaling friendly.Moreover, in addition to the first-order NS, it can bring intrinsic dynamic element matching (DEM) capability [13]–[15].Nevertheless, the VCO’s voltage-to-frequency gain is highlynonlinear and sensitive to PVT variation. Note that the NSIQand the VCO quantizer can be combined to achieve secondorder NS and 6-bit nominal resolution, therefore significantlyimproving the quantizer resolution [20]. Yet, additional nonidealities, including leakage from both quantizers and theirgain mismatches, degrade the overall performance. It requiresa delay-locked-loop for tuning, but this increases the circuitcomplexity. Recently, a first-order NS SAR quantizer in a DT Σ ADC is proposed in [21]. This SAR based NS quantizeris fully passive, OTA-free, and PVT robust. However, with anNTF zero at 0.5, its NS capability is rather limited. It can onlyprovide 9.5 dB in-band SQNR improvement.This paper presents a third-order CT Σ ADC with a novelsecond-order NS SAR quantizer. Comparing to a conventionalsecond-order passive DT loop filter with SAR quantizer, theNS SAR quantizer is simpler and more power efficient, forit uses the same capacitor array for multi-bit quantization,digital-to-analog conversion, and analog subtraction. This NSSAR quantizer also has several key advantages over the priorNS quantizers for Σ ADCs. First, its circuit is simple, as itrequires only a few extra switches, capacitors, and comparator2input pairs on top of a standard SAR ADC. Second, it is OTAfree and scaling friendly. Third, the quantizer NTF is set bycomponent ratios, and thus, is robust against PVT variationand is calibration-free. Fourth, it achieves the second-orderNS with the NTF of (1 0.75z 1 )2 and provides 24 dBin-band SQNR improvement. Lastly, the excess loop delaycompensation (ELDC) can be easily embedded inside it, whichreduces the overall circuit complexity. Moreover, comparingto the prior standalone second-order NS SAR ADC in [22],the proposed NS SAR quantizer has two clear merits. First,it significantly reduces the kT /C noise. Thus, for the samethermal noise budget, the total capacitance can be reducedby 2.4 times, leading to substantial area and power saving.The capacitance reduction also shortens the DAC settling time,speeding up the quantizer operation. Second, the comparatornoise requirement is relaxed, resulting in over 40% reductionin the comparator power.Owing to the inherent second-order NS capability of thequantizer, the proposed CT Σ ADC achieves an overallthird-order NS with the NTF of (1 z 1 )(1 0.75z 1 )2 butrequiring only a single OTA. As a result, the overall circuitpower and complexity are reduced. The loop stability is alsoimproved. Because two noise shaping orders are realized inthe DT domain using switched capacitors inside the quantizer,they are insensitive to PVT variations. As a result, the overallstability of the proposed third-order CT Σ ADC is similarto that of a first-order CT Σ ADC when considering theRC variation. From a different angle, the proposed Σ ADCcan also be viewed as a CT-DT hybrid with the one-order NSrealized in CT and two-order NS realized in DT. It combinesthe merits of CT Σ ADCs, which are anti-alias filteringcapability and low power, with the merit of DT Σ ADCs,which is PVT robustness. A prototype chip is realized in 40nm CMOS with an active area of only 0.029 mm2 . It achievesa peak SNDR of 70.4 dB over 12.5 MHz bandwidth whileconsuming only 1.16 mW of power, leading to a competitiveWalden figure of merit (FoM) of 17 fJ/conversion-step.This paper provides the detailed analyses and implementation of the proposed CT Σ ADC. It is a significant extensionof [23] and is organized as follows. Section II discussesthe proposed second-order NS SAR quantizer. Section IIIpresents the proposed CT Σ ADC. Section IV provides themeasurement results. Finally, Section V concludes this paper.II. P ROPOSED S ECOND -O RDER NS SAR Q UANTIZERA. Brief Review of NS SAR ADCsThe NS SAR ADC is an emerging ADC architecture thataims to combine the benefits of both SAR and Σ ADCswhile simultaneously obviating their drawbacks [22], [24]–[31]. The works of [24]–[26] use OTA to build active filtersand realize aggressive NTF, however at the cost of OTA’s largepower consumption and scaling unfriendliness. The works of[30], [31] use dynamic amplifiers to replace OTAs to reduceboth power and noise. Nevertheless, the gain of dynamicamplifier is sensitive to PVT variations. Digital backgroundcalibration can be used to ensure PVT robustness, but itincreases the design complexity and requires many input
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. XX, NO. XX, XXXX 20183CDACVinΦsΦ01g1g2Φ1Φ3n-1C0 CDAC /3C2 CDACC1Φ2C0C1 CDACDoutg1 4g2 16ΦcnΦsΦcΦ0Φ3Φ1Φ2C2(a)n DACResidue sampling n 0,Φ3Vinz -1n 0,Φ11/43/4n 2,Φ21/416Doutn 1,Φ1C0 reset1/4n 0,Φ03/4z -13/4z -14st21 -order integrationnd-order integrationComparison(b)Input samplingVinΦsCDACn DAC2 C0 resetΦ0 n- DACkTCDACResidue samplingC0n 0,Φ0 2 n- 0,Φ0kT 3kT C0 CDACn 0,Φ1 2 Φ1n- 0,Φ1kTC 19kT C0 (C1 C 0 ) 4CDACn 0,Φ3 2 n- 0,Φ3kTC DAC9kT C0 (CDAC C0 ) 4CDAC2 nd -order integration1st-order integrationC0Φ3 C0CDACC1 n- 1,Φ1n 1,Φ1 2 C0kTC 0kT C1 (C1 C 0 ) 4CDACn 2,Φ22 Φ2C2 n- 2,Φ2kTC 0kT C2 (C2 C 0 ) 4CDAC(c)Fig. 3. Prior NS SAR ADC [22]: (a) simplified schematic and timing; (b) signal flow diagram with kT /C noise; (c) noise definition and calculation.samples for convergence [31]. Alternatively, a few recentworks propose to use switched capacitors to build fully passivefilters [22], [27]–[29]. They are simple, OTA free, and scalingfriendly. Moreover, their NTF is set by component ratio, andthus, is accurate and calibration free. Comparing to OTA-basedactive filters, the limitation for using lossy passive filters is thatthe NTF zeros cannot be placed at the unit cycle. In addition,passive filters do not provide voltage gain, and hence, thecomparator noise suppression is not as effective. Yet, a fullypassive NS SAR is well suited as a NS quantizer for ΣADCs. Its merits of simplicity, low power, and PVT robustnessare maintained, while its limitations are easily addressed byplacing it after an active RC filter. The front-end filter providesgain and sufficient suppression for both the quantization errorand the comparator noise.(φ0 φ3 ) and three capacitors (C0 C2 ) are addedon top of a standard SAR ADC to implement the passiveintegrators. At the end of a complete SAR conversion, theresidue voltage on CDAC is sampled on a small capacitor,C0 CDAC /3, and then sequentially merged with twocapacitors, C1 C2 CDAC , for passive integrations. Signalattenuations happen due to the charge sharing operations,which are CDAC /(CDAC C0 ) 3/4 by residue samplingand C0 /(C0 C1,2 ) 1/4 by each passive integration. A 3input-pair comparator works as a dynamic adder in the feedforward path. The three input pairs are sized with the ratio of1:4:16 to provide the passive gains, g1 and g2 , to compensatefor the signal attenuations. The NTF zeros of the NS SARADC are determined by the ratios of C0 to C1 and C2 , whichare z C1,2 /(C0 C1,2 ) 3/4. The resulted NTF of the NSSAR ADC is (1 0.75z 1 )2 .B. Prior Second-Order NS SAR ADC of [22]The residue sampling on C0 results in two significant disadvantages. One is the signal attenuation of 3/4 as mentionedearlier. The other is the greatly increased kT /C noise. Fig.Fig. 3(a) shows the simplified core schematic of the priorstandalone second-order NS SAR ADC of [22]. Four switches
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. XX, NO. XX, XXXX 20184CDACΦsVinn-11g1g2Φ1Φ2C1DoutΦcC1 3CDACΦsC2 3CDACΦcg1 3g2 12Φ1Φ2C2n(a)n 0,Φ1n DACVinz -11/4n 2,Φ21/4Dout12n 1,Φ13/4z -13/4z -13st21 -order integrationnd-order integrationComparison(b)Input samplingVinΦsCDACn DAC2 kTCDAC2 nd -order integration1st-order integration n- DACCDACn 0,Φ1 2 Φ1n- 0,Φ1kTC 13kT CDAC(C1 CDAC) 4CDACC1 n- 1,Φ1n 1,Φ1 2 kTC DACkT C1 (C1 C DAC) 12CDACCDACn 2,Φ22 Φ2 C2 n- 2,Φ2kTC DACkT C2 (C2 C DAC) 12CDAC(c)Fig. 4. Proposed NS SAR ADC: (a) simplified schematic and timing; (b) signal flow diagram with kT /C noise; (c) noise definition and calculation.3(b) shows the signal flow diagram of the NS SAR ADC withkT /C noise. The overall input referred kT /C noise can becalculated as:31ntot nDAC (n0,φ3 n0,φ0 )(2 z 1 ) 4n1,φ144. (1)33 4n0,φ1 (1 z 1 ) 16n2,φ2 (1 z 1 )44The above noise expressions are in amplitude. The quadraticexpression of every noise source is defined and shown in Fig.3(c). Note that n0,φ1 and n1,φ1 are from the same clock phase.They are correlated but with the opposite sign. The other noisesources are independent.C. Proposed Second-Order NS SAR ADCThe proposed second-order fully passive NS SAR ADC isshown in Fig. 4(a). Comparing to [22], the proposed NS SARhas lower circuit complexity. It adds only two switches andtwo capacitors on top of a standard SAR ADC. The proposedscheme obviates the residue sampling on C0 in Fig. 3(a);instead, it directly connects CDAC to two large capacitorsC1 and C2 for integrations, where C1 C2 3CDAC .Even though this modification seems small, it brings two keyadvantages. First, it removes the signal attenuation of 3/4 dueto the residue sampling on C0 . To realize the same NTFof (1 0.75z 1 )2 , the comparator input pair ratio can bereduced from 1:4:16 of [22] to 1:3:12 of the proposed work.The relaxed comparator gain requirement leads to reducedcomparator power. For the same comparator input referrednoise budget, the proposed scheme reduces the comparatorpower by more than 40%. Second, it removes two large kT /Cnoise sources due to C0 reset and residue sampling, which aren0,φ0 and n0,φ3 in Fig. 3(b).The signal flow diagram and noise calculation of the proposed NS SAR ADC are shown in Fig. 4(b) and Fig. 4(c).For the proposed NS SAR scheme, the overall input referredkT /C noise is given by3ntot nDAC 3n1,φ1 3n0,φ1 (1 z 1 )4.(2)3 12n2,φ2 (1 z 1 )4Comparing to (1), the noise sources of n0,φ3 and n0,φ0 areeliminated. Additionally, the coefficients for n1,φ1 , n0,φ1 , andn2,φ2 in (1) are scaled by 3/4 in (2), leading to the over 40%noise power reduction.Fig. 5 compares the total input referred kT /C noise powerspectral densities (PSDs) of the prior NS SAR of [22] withthe proposed NS SAR. Both PSDs are flat in-band. The inband PSDs of the prior and the proposed NS SAR schemesare 18kT /(CDAC · fs ) and 3.6kT /(CDAC · fs ), respectively.Thus, for the same CDAC , the proposed architecture reducesthe kT /C noise by 5 times. From a different perspective, for
2 [2kT/(C.ntotDAC f s )]IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. XX, NO. XX, XXXX 201810Prior NS SARProposed NS SAR25Vout Vout -Vout OSR 2010V2o V2o-V2o 10Vout V2o V2o 1V2o V1o -00.005f s0.05f sV1o 0.5f sFrequencyV1o -Fig. 5. Input referred overall kT /C noise power spectral densities.TABLE IC APACITOR VALUES FOR T HE S AME OVERALL kT /C N OISE B UDGET.C0C1C2TotalPrior work [22]CC/3CC10C/3Proposed workC/5-3C/53C/57C/5CDACthe same total kT /C noise budget, the proposed NS SARarchitecture can use a 5-time smaller CDAC . This relaxesthe quantizer driver requirement and the power consumption.It also reduces the DAC switching power and settling time.Table I summarizes the capacitor values used by the two NSSAR architectures for the same kT /C noise budget. The totalcapacitance of the proposed NS SAR quantizer is 2.4 timessmaller than that of the prior NS SAR of [22], which is asignificant area saving. Note that because CDAC has to bepartitioned into smaller unit capacitors, its capacitance densityis smaller than that for lump capacitors C0 C2 , and thus,the actual area saving in real implementation is even larger.Besides, a minor drawback of the proposed NS SAR schemeis that the two passive integrations cannot be done within thesampling phase as in the prior work [22], thus more clockcycles are required. However, as long as the comparison resultof last bit is determined, the first-order integration can start. Inthis manner, the first-order integration phase Φ1 can be mergedwith the remaining time for DAC feedback of the last bit cycle.Therefore, the clock cycle for Φ1 is saved and only one extracycle for Φ2 is required, as shown in Fig. 4(a). Moreover,considering that the proposed scheme greatly relaxes the DACsettling requirement by reducing the capacitor size, the overallADC operation speed may not be slowed.D. Proposed 3-Input-Pair ComparatorFig. 6 presents the schematic of the proposed 3-stage 3input-pair dynamic comparator1 used in the NS SAR quantizer,the waveforms of key nodes are also sketched alongside. Thewidth ratios of the 3 input pairs are set to 1:3:12, whichrealizes the relative path gains, g1 3 and g2 12, asshown in Fig. 4(b). When at clock rising edges, the transientsignal jumps of the drains and sources of input pairs canbe coupled to input through the gate-drain and gate-sourcecapacitance, resulting in kickback noise. For the StrongArm1 In Fig. 4 of the prior conference paper [23], the V1o /V1o connectionsof the comparator are wrongly drawn.V1o Vd-Vint 0:2 1:3:12ΦcV1o V1o Vd Vd Vd Vint 0:2 1:3:12Vint-ΦcVint Fig. 6. Schematic of the proposed 3-stage 3-input-pair comparator.latch based comparator as in [22], both the gate-source andgate-drain couplings result in kickback noise, and the drainsexperience rail-to-rail signal jumps. In the proposed design,the sources of input pairs are grounded, thereby removing thekickback due to gate-source coupling [32]; it only suffers fromthe kickback by the gate-drain coupling, and the drain jumpsare only a fraction of the rail-to-rail swing. As a result, thearrangement in the proposed comparator reduces the kick-backnoise. In addition, it removes the dependence of the sourcevoltage on the gate voltage, making the path gains g1 and g2to be first-order independent from the input differential-modevoltages. The two inverters connecting V1o and V2o comprisethe comparator second stage. They act as dynamic amplifiersand serve as the intermediate buffer between the first-stagepre-amplifier and the last stage latch, reducing the loading ofthe first stage and accelerating the comparison speed. Theyalso provide extra voltage gain, reducing the noise and theoffset from the latch, as well as shortening the time neededfor the latch regeneration. The inverter outputs are applied tothe latch stage as both input and clock signals. As a result,the proposed comparator requires only one clock at the firststage, relaxing the clock path driving requirement.E. Robustness of Proposed NS SAR Against PVT VariationsTo analyze the robustness of the proposed second-order NSSAR ADC, let us examine its NTF. With C1 C2 3CDACas mentioned earlier, the NTF can be derived and shownbelow:3(1 z 1 )24N T F (z) (3)g19g23 13g1 21 ( )z ( )z416 21616Since the NTF zeros are solely set by capacitor ratios, theirlocations are insensitive to PVT variations. The pole locations,however, depend on not only capacitor ratios, but also g1 andg2 . g1 and g2 represent relative strengths of the comparatorinput pairs. They are first-order set by transistor width ratios,and hence, are not sensitive to process corner, voltage, andtemperature variations. Yet, g1 and g2 can change due to
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. XX, NO. XX, XXXX 2018g15080.0-3σ60.0-2σμ-σσ2σ3σ500 MC samples of (g1, g2)307g 1 g2 492040.01020.000.01.41.82.22.63.0 3.4 3.8Values4.24.6μσ2σNo. of Samples-σ34g1567Number 500Mean 59.7 1.0100Number 500Mean 12.1Std Dev 1.72-2σ2120g2120.0-3σ1Fig. 8. Stability condition and scatter plot of g1 and g2 .150.080.005.2(a)No. of SamplesTarget (g1 , g2 )40Number 500Mean 3.05Std Dev 0.483100.0g2No. of s182005522(b)65Fig. 9. Monte-Carlo simulation result of the proposed NS SAR ADC.Fig. 7. Monte-Carlo simulation results of (a) g1 and (b) g2 .random mismatches in the transistor threshold voltages. Thetransistor threshold mismatch can be suppressed by enlargingthe transistor size; however, this comes with the cost ofincreased comparator power and kickback noise. To balancethese trade-offs, the comparator input pair sizes in the prototype ADC are chosen to be 0.24um/0.04um, 0.72um/0.04um,and 2.88um/0.04um, respectively. Under this condition, the500-run Monte-Carlo (MC) SPICE simulation results for g1and g2 are plotted in Fig. 7. It can be seen that the meanvalues of g1 and g2 are close to 3 and 12, respectively. Theirstandard deviations are 0.48 and 1.7, respectively.To ensure the stability of the NS SAR, the NTF poles needto be within the unity circle, which translates to the stabilitycondition of 7g1 g2 49. It is shown in Fig. 8, togetherwith the scatter plots of g1 and g2 . It can be seen that they arewithin the stable region, indicated as the green dotted area. Ifmore margins are needed, the nominal values for g1 and g2 canbe downward shifted from 3 and 12 to 2.5 and 10, respectively.This comes with a small SQNR penalty of 1.5 dB. The otheroption is to enlarge the transistor sizes, as mentioned earlier.Because g1 and g2 variations only slightly alter the locationof NTF poles, their influence on the overall ADC SQNRis limited. Fig. 9 shows the simulated SQNR distributionof a 4-bit second-order NS SAR ADC at the OSR of 20,based on the g1 and g2 values from the 500-run Monte-Carlosimulation results of Fig. 7. The mean SQNR is 59.7 dB, whilethe standard deviation is only 1 dB, which demonstrates therobustness of the proposed NS SAR ADC architecture. Thefundamental reason for its robustness is that the NTF polesand zeros are first-order set by capacitor and transistor sizeratios, which are insensitive to PVT variations.60SQNR [dB]CVin(1-0.75zRVsOTACT domainRDAC-1 2) Q(z)fsD outSecond-orderNS SAR ADCDT domainFig. 10. Basic architecture of the proposed third-order CT Σ ADC withthe second-order NS SAR quantizer.III. P ROPOSED CT Σ ADC WITH NS SAR Q UANTIZERA. CT-DT Hybrid ArchitectureThe basic idea of the proposed third-order Σ ADC isdepicted in Fig. 10. It is a CT-DT hybrid. The CT portionshown on the left hand side of Fig. 10 includes an active RCintegrator and a 4-bit non-return-to-zero (NRZ) resistor DAC(RDAC). The DT portion, shown on the right hand side ofFig. 10, is the proposed NS SAR.The RC integrator realizes the CT transfer function of 1/s,it can be translated into the z-domain as z 1 /(1 z 1 ).Combining with the (1 0.75z 1 )2 second-order shaping bythe NS quantizer, the overall NTF of proposed CT Σ ADCisN T F (1 z 1 )(1 0.75z 1 )2 .(4)Taking advantage of the second-order noise shaping capability provided by the NS SAR quantizer, the CT loop filteris greatly simplified. Even though the overall Σ ADC isthird order, it requires only a single OTA. Furthermore, theCT-DT hybrid architecture combines the merits of both CT
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. XX, NO. XX, XXXX 201879080TTSSFFSFFS70SQNR [dB]SQNR [dB]85Proposed NS SAR quantizerProposed CT ΔΣ ADC6050404816208032OSR750.95Fig. 11. Simulated SQNRs of the CT Σ ADC and the NS SAR quantizer.1.1Supply voltage [V]1.25(a)10060Number 500Mean 79.5 1.6TTFF104060 65 70 7520075SS82280SQNR [dB]85Fig. 12. Monte-Carlo simulation result of the proposed CT Σ ADC.and DT Σ ADCs. CT Σ ADC has anti-alias filteringcapability and reduces OTA power by relaxing its settlingrequirement; however, its loop filter response is sensitive toRC product variation. By contrast, the DT Σ ADC’s NTFis robust against PVT variations, but it is less power efficientand does not have anti-alias filtering capability. The proposedCT-DT hybrid maintains anti-alias filtering capability and lowpower consumption of the front-end OTA by operating it inthe CT domain, and at the same time, benefits from the PVTrobustness of the DT second-order NS SAR quantizer. Becauseit has only one active RC filter, the robustness of the proposedthird-order Σ ADC is similar to that of a first-order CT ΣADC. Its robustness against RC product variation is higherthan that of a third-order purely CT Σ ADC.Fig. 11 shows the simulated SQNR of the proposed thirdorder Σ ADC and the proposed second-order NS SARquantizer. At the OSR of 20, the second-order NS SARquantizer itself already achieves 60 dB SQNR. Placing this NSSAR quantizer inside a first-order CT loop filter, the overallthird-order Σ ADC achieves 80 dB SQNR.Fig. 12 shows the SQNR distribution of the proposed ΣADC based on the g1 and g2 values from the 500-run MonteCarlo simulation results of Fig. 7. Overall, the mean value ofthe SQNR distribution is 79.5 dB with a standard deviationof 1.6 dB. It can be seen that 99% samples achieve SQNRbeyond 75 dB.Fig. 13(a) is the simulated SQNRs of the CT Σ ADCversus process corner and supply voltage variations, underthe temperature of 27 C. It shows that the SQNRs of theCT Σ ADC are between 77 dB and 84 dB with the fiveprocess corners and the supply voltage range from 0.95 Vto 1.25 V. The SQNR fluctuations across process corners areSQNR [dB]No. of Samples8084SF80FS7876-2027Temperature [ o C]85(b)Fig. 13. Simulated SQNRs of the CT Σ ADC (a) with supply voltage andprocess corner variations, (b) with temperature and process corner variations.caused by the RC variations of the CT loop filter, which canbe compensated via a factory calibration. Fig. 13(b) is thesimulated SQNRs of the CT Σ ADC versus process cornerand temperature variations, under the supply voltage of 1.1 V.It shows that all the simulated SQNRs are above 77 dB acrossthe five process corners and the temperature range from -20 C to 85 C. The simulation results show the robustness ofthe proposed CT-DT hybrid architecture.B. ELDC and Coefficient ScalingIn the idealistic architecture of Fig. 10, we have assumedthe NS SAR quantizer to be delay-free. In reality, the NSSAR quantizer delay can be a large portion of the samplingclock period, and can degrade the overall Σ ADC stability ifuncompensated. The commonly used method for ELDC is toadd a direct feedback path around the quantizer [33], whichrequires an additional DAC and an additional active adder.Thanks to the charge domain operation of the SAR ADC,the ELDC can be embedded inside the NS SAR quantizer[8], [9]. Comparing to the conventional ELDC method, theembedded charge domain ELDC obviates the need of theadditional feedback DAC and adder, which reduces the circuitcomplexity, power, and area.With the embedded charge domain ELDC, the model ofthe proposed Σ ADC is adapted from Fig. 10 to Fig. 14(a).Yet, there is one more practical issue to address: the signalswing of the integrator output, Vs , becomes 2 times of thefull swing, resulting in saturation of the integrator. To addressthis issue, coefficient scaling is performed, as illustrated in
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. XX, NO. XX, XXXX 2018CVin82R1-1 2) Q(z)fsVsD outOTACT domain(1-0.75zSecond-orderNS SAR ADCELDCz -1RDACDT domain(a)4C1/4 11/2(1-0.75zVinR) Q(z)/4fsVsD out4OTASecond-orderNS SAR ADCELDC1/4CT domain-1 2z -1RDACDT domain(b)Fig. 14. Adapted models of proposed CT Σ ADC with the second-order NS SAR quantizer and embedded ELDC (a) before and (b) after coefficient scaling.CDACVs [n]D3 0[n-1]/0/1CattCELDC3280/1/D3 0 [n]ΦsCSAR4218421Vint 0 Vint 1 CDAC C ELDC CSAR CattΦ1CELDC CSAR CDAC /4C1 C2 3CDACSARlogic1312C1CLKVint 2 Φ2C2Fig. 15. Implementation of the proposed second-order NS SAR quantizer with embedded ELDC.Fig. 14(b). The ELDC component is attenuated by 1/4 beforefeeding back to the subtraction node. It is then recovered by a
third-order Σ ADC is similar to that of a first-order CT Σ ADC. Its robustness against RC product variation is higher than that of a third-order purely CT Σ ADC. Fig. 11 shows the simulated SQNR of the proposed third-order Σ ADC and the proposed second-order NS SAR quantizer. At the OSR of 20, the second-order NS SAR
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uate the quality of grain damaged by rodents with respect to nutritional value, infection by moulds and aflatoxin contamination. 2 Materials and methods 2.1 Study area The study was conducted in Mwarakaya ward (03 49.17́'S; 039 41.498′E) located in Kilifi-south sub-county, in the low landtropical(LLT)zoneofKenya.Thisstudy site wasselect-
akuntansi musyarakah (sak no 106) Ayat tentang Musyarakah (Q.S. 39; 29) لًََّز ãَ åِاَ óِ îَخظَْ ó Þَْ ë Þٍجُزَِ ß ا äًَّ àَط لًَّجُرَ íَ åَ îظُِ Ûاَش
Collectively make tawbah to Allāh S so that you may acquire falāḥ [of this world and the Hereafter]. (24:31) The one who repents also becomes the beloved of Allāh S, Âَْ Èِﺑاﻮَّﺘﻟاَّﺐُّ ßُِ çﻪَّٰﻠﻟانَّاِ Verily, Allāh S loves those who are most repenting. (2:22
College Reading and Writing ENG 1301.029 COURSE SYLLABUS: Fall 2016 Instructor: Joyce Sample Classroom Location: Hall of Languages 201 Class Time: M W F 3:00 p.m. - 3:50 pm Office Location: TBD Office Hours: M W F 9:00 a.m. – 11:00 a.m. and by appointment Office Phone: 903-886-5908 Office Fax: 903-886-5980 University Email Address: joyce.sample@tamuc.edu .
