Digikey.pt
Freescale SemiconductorDocument Number: MPC8641DRev. 3, 05/2014Technical DataMPC8641 and MPC8641DIntegrated Host ProcessorHardware Specifications1OverviewThe MPC8641 processor family integrates either one or twoPower Architecture e600 processor cores with systemlogic required for networking, storage, wirelessinfrastructure, and general-purpose embedded applications.The MPC8641 integrates one e600 core while theMPC8641D integrates two cores.This section provides a high-level overview of the MPC8641and MPC8641D features. When referring to the MPC8641throughout the document, the functionality described appliesto both the MPC8641 and the MPC8641D. Any differencesspecific to the MPC8641D are noted.Figure 1 shows the major functional units within theMPC8641 and MPC8641D. The major difference betweenthe MPC8641 and MPC8641D is that there are two cores onthe MPC8641D.Freescale reserves the right to change the detail specifications as may be requiredto permit improvements in the design of its products. 2008-2014 Freescale Semiconductor, Inc. All rights .18.19.20.21.22.ContentsOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 20DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 21DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Ethernet: Enhanced Three-Speed Ethernet (eTSEC),MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Ethernet Management Interface ElectricalCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 59PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Signal Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108System Design Information . . . . . . . . . . . . . . . . . . 116Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 126Document Revision History . . . . . . . . . . . . . . . . . . 128
Overviewe600 Core Blocke600 Core Blocke600 Core32-KbyteL1 Instruction Cache1-MbyteL2 Cache32-KbyteL1 Data Cachee600 Core32-KbyteL1 Instruction Cache1-MbyteL2 Cache32-KbyteL1 Data CacheMPX BusMPX Coherency Module (MCM)Platform BusSDRAMDDR SDRAM ControllerSDRAMDDR SDRAM ControllerROM,GPIOLocal Bus Controller(LBC)IRQsMultiprocessorProgrammable InterruptController(MPIC)SerialDual CI2C ControllerI2CI2C ControllerRMII, GMII,MII, RGMII,TBI, RTBIRMII, GMII,MII, RGMII,TBI, RTBIEnhanced TSECController[ x1/x2/x4/x8 PCI Exp (4 GB/s)AND 1x/4x SRIO (2.5 GB/s) ]OR [2-x1/x2/x4/x8 PCI Express(8 GB/S) ]Enhanced TSECControllerPCI ExpressInterfaceEnhanced TSECController10/100/1GbRMII, GMII,MII, RGMII,TBI, RTBIOCeaNSwitchFabricSerial RapidIOInterfaceorPCI ExpressInterface10/100/1Gb10/100/1GbRMII, GMII,MII, RGMII,TBI, RTBIPlatformFour-ChannelDMA ControllerExternalControlEnhanced TSECController10/100/1GbFigure 1. MPC8641 and MPC8641DMPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 32Freescale Semiconductor
Overview1.1Key FeaturesThe following lists an overview of the MPC8641 key feature set: Major features of the e600 core are as follows:— High-performance, 32-bit superscalar microprocessor that implements the PowerPC ISA— Eleven independent execution units and three register files– Branch processing unit (BPU)– Four integer units (IUs) that share 32 GPRs for integer operands– 64-bit floating-point unit (FPU)– Four vector units and a 32-entry vector register file (VRs)– Three-stage load/store unit (LSU)— Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,respectively, in a cycle.— Rename buffers— Dispatch unit— Completion unit— Two separate 32-Kbyte instruction and data level 1 (L1) caches— Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cachewith ECC— 36-bit real addressing— Separate memory management units (MMUs) for instructions and data— Multiprocessing support features— Power and thermal management— Performance monitor— In-system testability and debugging features— Reliability and serviceability MPX coherency module (MCM)— Ten local address windows plus two default windows— Optional low memory offset mode for core 1 to allow for address disambiguation Address translation and mapping units (ATMUs)— Eight local access windows define mapping within local 36-bit address space— Inbound and outbound ATMUs map to larger external address spaces— Three inbound windows plus a configuration window on PCI Express— Four inbound windows plus a default window on serial RapidIO— Four outbound windows plus default translation for PCI Express— Eight outbound windows plus default translation for serial RapidIO with segmentation andsub-segmentation supportMPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3Freescale Semiconductor3
Overview DDR memory controllers— Dual 64-bit memory controllers (72-bit with ECC)— Support of up to a 300-MHz clock rate and a 600-MHz DDR2 SDRAM— Support for DDR, DDR2 SDRAM— Up to 16 Gbytes per memory controller— Cache line and page interleaving between memory controllers.Serial RapidIO interface unit— Supports RapidIO Interconnect Specification, Revision 1.2— Both 1x and 4x LP-Serial link interfaces— Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) perlane— RapidIO–compliant message unit— RapidIO atomic transactions to the memory controllerPCI Express interface— PCI Express 1.0a compatible— Supports x1, x2, x4, and x8 link widths— 2.5 Gbaud, 2.0 Gbps laneFour enhanced three-speed Ethernet controllers (eTSECs)— Three-speed support (10/100/1000 Mbps)— Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab-compatible controllers— Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI——————— Support a full-duplex FIFO mode for high-efficiency ASIC connectivityTCP/IP off-loadHeader parsingQuality of service supportVLAN insertion and deletionMAC address recognitionBuffer descriptors are backward compatible with PowerQUICC II and PowerQUICC IIIprogramming models— RMON statistics support— MII management interface for control and statusProgrammable interrupt controller (PIC)— Programming model is compliant with the OpenPIC architecture— Supports 16 programmable interrupt and processor task priority levels— Supports 12 discrete external interrupts and 48 internal interrupts— Eight global high resolution timers/counters that can generate interrupts— Allows processors to interrupt each other with 32b messagesMPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 34Freescale Semiconductor
Overview — Support for PCI-Express message-shared interrupts (MSIs)Local bus controller (LBC)— Multiplexed 32-bit address and data operating at up to 133 MHz— Eight chip selects support eight external slavesIntegrated DMA controller— Four-channel controller— All channels accessible by both the local and the remote masters— Supports transfers to or from any local memory or I/O port— Ability to start and flow control each DMA channel from external 3-pin interfaceDevice performance monitor— Supports eight 32-bit counters that count the occurrence of selected events— Ability to count up to 512 counter-specific events— Supports 64 reference events that can be counted on any of the 8 counters— Supports duration and quantity threshold counting— Burstiness feature that permits counting of burst events with a programmable time betweenbursts— Triggering and chaining capability— Ability to generate an interrupt on overflowDual I2C controllers— Two-wire interface— Multiple master support— Master or slave I2C mode support— On-chip digital filtering rejects spikes on the busBoot sequencer— Optionally loads configuration data from serial ROM at reset via the I2C interface— Can be used to initialize configuration registers and/or memory— Supports extended I2C addressing mode— Data integrity checked with preamble signature and CRCDUART— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)— Programming model compatible with the original 16450 UART and the PC16550DIEEE 1149.1-compatible, JTAG boundary scanAvailable as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA)MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3Freescale Semiconductor5
Electrical Characteristics2Electrical CharacteristicsThis section provides the AC and DC electrical specifications and thermal characteristics for theMPC8641. The MPC8641 is currently targeted to these specifications.2.1Overall DC Electrical CharacteristicsThis section covers the ratings, conditions, and other characteristics.2.1.1Absolute Maximum RatingsTable 1 provides the absolute maximum ratings.Table 1. Absolute Maximum Ratings1CharacteristicSymbolAbsolute MaximumValueUnitNotesCores supply voltagesVDD Core0,VDD Core1–0.3 to 1.21 VV2Cores PLL supplyAVDD Core0,AVDD Core1–0.3 to 1.21 VV—SVDD–0.3 to 1.21 VV—SerDes Serial I/O Supply Port 1XVDD SRDS1–0.3 to 1.21VV—SerDes Serial I/O Supply Port 2XVDD SRDS2–0.3 to 1.21 VV—SerDes DLL and PLL supply voltage for Port 1 and Port 2AVDD SRDS1,AVDD SRDS2–0.3 to 1.21VV—Platform Supply voltageVDD PLAT–0.3 to 1.21VV—Local Bus and Platform PLL supply voltageAVDD LB,AVDD PLAT–0.3 to 1.21VV—D1 GVDD,D2 GVDD–0.3 to 2.75 VV3–0.3 to 1.98 VV3LVDD–0.3 to 3.63 VV4–0.3 to 2.75 VV4–0.3 to 3.63 VV4–0.3 to 2.75 VV4–0.3 to 3.63 VV—SerDes Transceiver Supply (Ports 1 and 2)DDR and DDR2 SDRAM I/O supply voltageseTSEC 1 and 2 I/O supply voltageeTSEC 3 and 4 I/O supply voltageLocal Bus, DUART, DMA, Multiprocessor Interrupts, SystemControl & Clocking, Debug, Test, Power management, I2C, JTAGand Miscellaneous I/O voltageTVDDOVDDMPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 36Freescale Semiconductor
Electrical CharacteristicsTable 1. Absolute Maximum Ratings1 (continued)CharacteristicInput voltageSymbolAbsolute MaximumValueUnitNotesDn MVIN– 0.3 to (Dn GVDD 0.3)V5Dn MVREF– 0.3 to (Dn GVDD/2 0.3)V—Three-speed Ethernet signalsLVINTVINGND to (LVDD 0.3)GND to (TVDD 0.3)V5DUART, Local Bus, DMA,Multiprocessor Interrupts, SystemControl & Clocking, Debug, Test,Power management, I2C, JTAG andMiscellaneous I/O voltageOVINGND to (OVDD 0.3)V5TSTG–55 to 150 C—DDR and DDR2 SDRAM signalsDDR and DDR2 SDRAM referenceStorage temperature rangeNotes:1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, andfunctional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or causepermanent damage to the device.2. Core 1 characteristics apply only to MPC8641D. If two separate power supplies are used for VDD Core0 and VDD Core1,they must be kept within 100 mV of each other during normal run time.3. The –0.3 to 2.75 V range is for DDR and –0.3 to 1.98 V range is for DDR2.4. The 3.63V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75Vmaximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details onthe recommended operating conditions per protocol.5. During run time (M,L,T,O)VIN and Dn MVREF may overshoot/undershoot to a voltage and for a maximum duration as shownin Figure 2.2.1.2Recommended Operating ConditionsTable 2 provides the recommended operating conditions for the MPC8641. Note that the values in Table 2are the recommended and tested operating conditions. Proper device operation outside of these conditionsis not guaranteed. For details on order information and specific operating conditions for parts, seeSection 21, “Ordering Information.”Table 2. Recommended Operating ConditionsCharacteristicCores supply voltagesCores PLL supplySerDes Transceiver Supply (Ports 1 and 2)SymbolVDD Core0,VDD Core1AVDD Core0,AVDD Core1SVDDRecommendedValueUnitNotes1.10 50 mVV1, 2, 81.05 50 mV1, 2, 70.95 50 mV1, 2, 121.10 50 mVV8, 131.05 50 mV7, 130.95 50 mV12, 131.10 50 mV1.05 50 mVV8, 117, 11MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3Freescale Semiconductor7
Electrical CharacteristicsTable 2. Recommended Operating Conditions (continued)CharacteristicSerDes Serial I/O Supply Port 1SymbolRecommendedValueUnitNotesXVDD SRDS11.10 50 mVV81.05 50 mVSerDes Serial I/O Supply Port 2XVDD SRDS21.10 50 mV7V1.05 50 mVSerDes DLL and PLL supply voltage for Port 1 and Port 2Platform Supply voltageAVDD SRDS1,AVDD SRDS21.10 50 mVVDD PLAT1.10 50 mV7V1.05 50 mVV87AVDD LB,AVDD PLAT1.10 50 mVD1 GVDD,D2 GVDD2.5 V 125 mVV91.8 V 90 mVV9LVDD3.3 V 165 mVV102.5 V 125 mVV103.3 V 165 mVV102.5 V 125 mVV10OVDD3.3 V 165 mVV5Dn MVINGND to Dn GVDDV3, 6Dn MVREFDn GVDD/2 1%VThree-speed Ethernet signalsLVINTVINGND to LVDDGND to TVDDV4, 6DUART, Local Bus, DMA,Multiprocessor Interrupts, SystemControl & Clocking, Debug, Test,Power management, I2C, JTAGand Miscellaneous I/O voltageOVINGND to OVDDV5,6DDR and DDR2 SDRAM I/O supply voltageseTSEC 1 and 2 I/O supply voltageeTSEC 3 and 4 I/O supply voltageLocal Bus, DUART, DMA, Multiprocessor Interrupts, SystemControl & Clocking, Debug, Test, Power management, I2C,JTAG and Miscellaneous I/O voltageInput voltage871.05 50 mVLocal Bus and Platform PLL supply voltage8DDR and DDR2 SDRAM signalsDDR and DDR2 SDRAM referenceTVDDV1.05 50 mV87MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 38Freescale Semiconductor
Electrical CharacteristicsTable 2. Recommended Operating Conditions (continued)CharacteristicJunction temperature rangeSymbolRecommendedValueUnitNotesTJ0 to 105 C—Notes:1. Core 1 characteristics apply only to MPC8641D2. If two separate power supplies are used for VDD Core0 and VDD Core1, they must be at the same nominal voltage and theindividual power supplies must be tracked and kept within 100 mV of each other during normal run time.3. Caution: Dn MVIN must meet the overshoot/undershoot requirements for Dn GVDD as shown in Figure 2.4. Caution: L/TVIN must meet the overshoot/undershoot requirements for L/TVDD as shown in Figure 2 during regular run time.5. Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 2 during regular run time.6. Timing limitations for M,L,T,O)VIN and Dn MVREF during regular run time is provided in Figure 27. Applies to devices marked with a core frequency of 1333 MHz and below. Refer to Table 74 Part Numbering Nomenclatureto determine if the device has been marked for a core frequency of 1333 MHz and below.8. Applies to devices marked with a core frequency above 1333 MHz. Refer to Table 74 Part Numbering Nomenclature todetermine if the device has been marked for a core frequency above 1333 MHz.9. The 2.5 V 125 mV range is for DDR and 1.8 V 90 mV range is for DDR2.10. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on the recommendedoperating conditions per protocol.11. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. For more information refer toSection 14.4.3, “Differential Receiver (RX) Input Specifications.”12. Applies to Part Number MC8641xxx1000NX only. VDD Coren 0.95 V and VDD PLAT 1.05 V devices. Refer to Table 74Part Numbering Nomenclature to determine if the device has been marked for VDD Coren 0.95 V.13. This voltage is the input to the filter discussed in Section 20.2, “Power Supply Design and Sequencing,” and not necessarilythe voltage at the AVDD Coren pin, which may be reduced from VDD Coren by the filter.MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3Freescale Semiconductor9
Electrical CharacteristicsFigure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8641.L/T/Dn G/O/X/SVDD 20%L/T/Dn G/O/X/SVDD 5%VIHL/T/Dn G/O/X/SVDDGNDGND – 0.3 VVILGND – 0.7 VNot to Exceed 10%of tCLK1Note:1. tCLK references clocks for various functional blocks as follows:DDRn 10% of Dn MCK periodeTSECn 10% of ECn GTX CLK125 periodLocal Bus 10% of LCLK[0:2] periodI2C 10% of SYSCLKJTAG 10% of SYSCLKFigure 2. Overshoot/Undershoot Voltage for Dn M/O/L/TVINThe MPC8641 core voltage must always be provided at nominal VDD Coren (See Table 2 for actualrecommended core voltage). Voltage to the processor interface I/Os are provided through separate sets ofsupply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales withrespect to the associated I/O supply voltage. OVDD and L/TVDD based receivers are simple CMOS I/Ocircuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses asingle-ended differential receiver referenced to each externally supplied Dn MVREF signal (nominally setto Dn GVDD/2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards.MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 310Freescale Semiconductor
Electrical Characteristics2.1.3Output Driver CharacteristicsTable 3 provides information on the characteristics of the output driver strengths. The values arepreliminary estimates.Table 3. Output Drive CapabilityDriver TypeProgrammableOutput Impedance(Ω)SupplyVoltageNotesDDR1 signal1836 (half strength mode)Dn GVDD 2.5 V4, 9DDR2 signal1836 (half strength mode)Dn GVDD 1.8 V1, 5, 9Local Bus signals4525OVDD 3.3 V2, 6eTSEC/10/100 signals45T/LVDD 3.3 V630T/LVDD 2.5 V6DUART, DMA, Multiprocessor Interrupts, SystemControl & Clocking, Debug, Test, Power management,JTAG and Miscellaneous I/O voltage45OVDD 3.3 V6I2C150OVDD 3.3 V7SRIO, PCI Express100SVDD 1.1/1.05 V3, 8Notes:1. See the DDR Control Driver registers in the MPC8641D reference manual for more information.2. Only the following local bus signals have programmable drive strengths: LALE, LAD[0:31], LDP[0:3], LA[27:31], LCKE,LCS[1:2], LWE[0:3], LGPL1, LGPL2, LGPL3, LGPL4, LGPL5, LCLK[0:2]. The other local bus signals have a fixed drivestrength of 45 Ω. See the POR Impedance Control register in the MPC8641D reference manual for more information aboutlocal bus signals and their drive strength programmability.3. See Section 17, “Signal Listings,” for details on resistor requirements for the calibration of SDn IMP CAL TX andSDn IMP CAL RX transmit and receive signals.4. Stub Series Terminated Logic (SSTL-25) type pins.5. Stub Series Terminated Logic (SSTL-18) type pins.6. Low Voltage Transistor-Transistor Logic (LVTTL) type pins.7. Open Drain type pins.8. Low Voltage Differential Signaling (LVDS) type pins.9. The drive strength of the DDR interface in half strength mode is at Tj 105C and at Dn GVDD (min).2.2Power Up/Down SequenceThe MPC8641 requires its power rails to be applied in a specific sequence in order to ensure proper deviceoperation.NOTEThe recommended maximum ramp up time for power supplies is 20milliseconds.The chronological order of power up is as follows:1. All power rails other than DDR I/O (Dn GVDD, and Dn MVREF).MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3Freescale Semiconductor11
Electrical CharacteristicsNOTEThere is no required order sequence between the individual rails for thisitem (# 1). However, VDD PLAT, AVDD PLAT rails must reach 90% oftheir recommended value before the rail for Dn GVDD, and Dn MVREF (innext step) reaches 10% of their recommended value. AVDD type suppliesmust be delayed with respect to their source supplies by the RC timeconstant of the PLL filter circuit described in Section 20.2.1, “PLL PowerSupply Filtering.”2. Dn GVDD, Dn MVREFNOTEIt is possible to leave the related power supply (Dn GVDD, Dn MVREF)turned off at reset for a DDR port that will not be used. Note that these powersupplies can only be powered up again at reset for functionality to occur onthe DDR port.3. SYSCLKThe recommended order of power down is as follows:1. Dn GVDD, Dn MVREF2. All power rails other than DDR I/O (Dn GVDD, Dn MVREF).NOTESYSCLK may be powered down simultaneous to either of item # 1 or # 2 inthe power down sequence. Beyond this, the power supplies may powerdown simultaneously if the preservation of DDRn memory is not a concern.See Figure 3 for more details on the Power and Reset Sequencing details.MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 312Freescale Semiconductor
Electrical CharacteristicsFigure 3 illustrates the Power Up sequence as described above.3.3 VL/T/OVDDDC Power Supply VoltageIf1L/TVDD 2.5 V2.5 VDn GVDD, 1.8/2.5 VDn MVREF1.8 VVDD PLAT, AVDD PLATAVDD LB, SVDD, XVDD SRDSnAVDD SRDSnVDD Coren, AVDD Coren1.2 V100 µs Platform PLLRelock Time 370Power Supply Ramp Up 2TimeSYSCLK 8 (not drawn to scale)9HRESET (& TRST)Asserted for100 μs afterSYSCLK is functional 4e6005PLLResetConfiguration PinsCycles Setup and hold Time 6Notes:1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 2.2. The recommended maximum ramp up time for power supplies is 20 milliseconds.3. Refer to Section 5, “RESET Initialization” for additional information on PLL relock and reset signalassertion timing requirements.4. Refer to Table 11 for additional information on reset configuration pin setup timing requirements. Inaddition see Figure 68 regarding HRESET and JTAG connection details including TRST.5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX clk cycles.6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configurationinputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cyclesafter HRESET has negated (hold requirement). See Section 5, “RESET Initialization” for moreinformation on setup and hold time of reset configuration signals.7. VDD PLAT, AVDD PLAT must strictly reach 90% of their recommended voltage before the rail forDn GVDD, and Dn MVREF reaches 10% of their recommended voltage.8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2 TXD[4],TSEC2 TX ER)must be valid BEFORE HRESET is asserted.Figure 3. MPC8641 Power-Up and Reset SequenceMPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3Freescale Semiconductor13
Power Characteristics3Power CharacteristicsThe power dissipation for the dual core MPC8641D device is shown in Table 4.Table 4. MPC8641D Power Dissipation (Dual Core)Power ModeCore Frequency(MHz)PlatformFrequency (MHz)VDD Coren,VDD PLAT(Volts)TypicalThermal1500 MHz600 MHz1.1 VMaximum1333 MHz533 MHz1.05 VMaximum1250 MHz500 MHz1, 243.41, 349.91, 423.91, 230.01, 334.11, 423.91, 230.01, 334.11, 423.91, 230.01, 334.11, 416.21, 2, 521.81, 3, 525.01, 4, 5105 oC105 oC651000 MHz400 MHzoC1.05 V105 oCMaximumTypicalMaximum32.1105 oCTypicalThermal65 oC1.05 VMaximumThermalNotes65 oCTypicalThermalPower(Watts)65 oCTypicalThermalJunctionTemperature651000 MHz500 MHz0.95 V,1.05 VoC105 oCNotes:1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies andconfigurations. The values do not include power dissipation for I/O supplies.2. Typical power is an average value measured at the nominal recommended core voltage (VDD Coren) and 65 C junctiontemperature (see Table 2)while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz with one coreat 100% efficiency and the second core at 65% efficiency.3. Thermal power is the average power measured at nominal core voltage (VDD Coren) and maximum operating junctiontemperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz on bothcores and a typical workload on platform interfaces.4. Maximum power is the maximum power measured at nominal core voltage (VDD Coren) and maximum operating junctiontemperature (see Table 2) while running a test which includes an entirely L1-cache-resident, contrived sequence ofinstructions which keep all the execution units maximally busy on both cores.5. These power numbers are for Part Number MC8641Dxx1000NX only. VDD Coren 0.95 V and VDD PLAT 1.05 V.MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 314Freescale Semiconductor
Power CharacteristicsThe maximum power dissipation for individual power supplies of the MPC8641D is shown in Table 5.Table 5. MPC8641D Individual Supply Maximum Power Dissipation 1Component DescriptionSupply Voltage(Volts)Power(Watts)Per Core voltage SupplyVDD Core0/VDD Core1 1.1 V @ 1500 MHz21.00Per Core PLL voltage supplyAVDD Core0/AVDD Core1 1.1 V @ 1500 MHz0.0125Per Core voltage SupplyVDD Core0/VDD Core1 1.05 V @ 1333 MHz17.00Per Core PLL voltage supplyAVDD Core0/AVDD Core1 1.05 V @ 1333 MHz0.0125Per Core voltage SupplyVDD Core0/VDD Core1 0.95 V @ 1000 MHz11.505Per Core PLL voltage supplyAVDD Core0/AVDD Core1 0.95 V @ 1000 MHz0.01255DDR Controller I/O voltage supplyDn GVDD 2.5 V @ 400 MHz0.802Dn GVDD 1.8 V @ 533 MHz0.682Dn GVDD 1.8 V @ 600 MHz0.77216-bit FIFO @ 200 MHzeTsec 1&2/3&4 Voltage SupplyL/TVDD 3.3 V0.112, 3non-FIFO eTsecn Voltage SupplyL/TVDD 3.3 V0.082x8 SerDes transceiver SupplySVDD 1.1 V0.702x8 SerDes I/O SupplyXVDD SRDSn 1.1 V0.662SerDes PLL voltage supply Port 1 or 2AVDD SRDS1/AVDD SRDS2 1.1 V0.10Platform I/O SupplyOVDD 3.3 V0.45Platform source SupplyVDD PLAT 1.1 V @ 600 MHz12.00Platform source SupplyVDD PLAT 1.05 Vn @ 500 MHz9.80Platform source SupplyVDD PLAT 1.05 Vn @ 400 MHz7.70Platform, Local Bus PLL voltage SupplyAVDD PLAT, AVDD LB 1.1 V0.0125Notes45Notes:1. This is a maximum power supply number which is provided for power supply and board design information. The numbers arebased on 100% bus utilization for each component. The components listed are not expected to have 100% bus usagesimultaneously for all components. Actual numbers may vary based on activity.2. Number is based on a per port/interface value.3. This is based on one eTSEC port used. Since 16-bit FIFO mode involves two ports, the number will need to be multiplied bytwo for the total. The other eTSEC protocols dissipate less than this number per port. Note that the power needs to bemultiplied by the number of ports used for the protocol for the total eTSEC port power dissipation.4.This includes Local Bus, DUART, I2C, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Powermanagement, JTAG and Miscellaneous I/O voltage.5. These power numbers are for Part Number MC8641xxx1000NX only. VDD Coren 0.95 V and VDD PLAT 1.05 V.MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 3Freescale Semiconductor15
Power CharacteristicsThe power dissipation for the MPC8641 single core device is shown in Table 6.Table 6. MPC8641 Power Dissipation (Single Core)Power ModeCore Frequency(MHz)PlatformFrequency (MHz)VDD Coren,VDD PLAT(Volts)TypicalThermal1500 MHz600 MHz1.1 VMaxim1333 MHz533 MHz1.05 VTypical500 MHz1, 225.21, 328.91, 416.31, 220.21, 323.21, 416.31, 220.21, 323.21, 416.31, 220.21, 323.21, 411.61, 2, 514.41, 3, 516.51, 4, 5105 oC105 oCoC105 oC65 oC1000 MHz400 MHz1.05 V105 oCMaximumTypicalMaximum20.31.05 VTypicalThermal65 oC651250 MHzMaximumThermalNotes65 Temperature651000 MHz500 MHz0.95 V,1.05 VoC105 oCNotes:1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies andconfigurations. The values do not include power dissipation for I/O supplies.2. Typical power is an average value measured at the nominal recommended core voltage (VDD Coren) and 65 C junctiontemperature (see Table 2)while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.3. Thermal power is the average power measured at nominal core voltage (VDD Coren) and maximum operating junctiontemperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz and a typicalworkload on platform interfaces.4. Maximum power is the maximum power measured at nominal core voltage (VDD Coren) and maximum operating junctiontemperature (see Table 2) while running a test which includes an entirely L1-cache-resident, contrived sequence ofinstructions which keep all the execution units maximally busy.5. These power numbers are for Part Number MC8641xx1000NX only. VDD Coren 0.95 V and VDD PLAT 1.05 V.MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 316Freescale Semiconductor
Input Clocks4Input ClocksTable 7 provides the system clock (SYSCLK) DC specifications for the MPC8641.Table 7. SYSCLK DC Electrical Characteristics (OVDD 3.3 V 165 mV)ParameterSymbolMinMaxUnitHigh-level input voltageVIH2OVDD 0.3VLow-level input voltageVIL–0.30.8VInput current(VIN 1 0 V or VIN VDD)IIN— 5μANote:1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.4.1System Clock TimingTable 8 pro
2008-2014 Freescale Semiconductor, Inc. All rights reserved. Freescale Semiconductor Technical Data Freescale reserves the right to change the detail .
Get dataset D t {(s t,π*(s t))} D Aggregate dataset D D D t Train classifier π i ̂ 1 on D p̂t π θ(y1 set t s t) π θ(y t 2 s t) draw Bernoulli variable Z t 1 of parameter b b p̂t if Z t π i for t 1to T * After completing his Ph.D., Ellis worked at Bell Labs from 1969 to 1972 on probability theory. Name Entity .
Yaesu FT-736R PSU repair Updated for DigiKey (North American) sources & data . PSU PCB with 105 C versions, but not necessarily the rectifier filter's 470 uF/200 V big caps, if they seem OK and you can measure their value or even better, the ESR too. b. Replace R17 and R18 (optional) with a pair of 5W, 33ohm resistors (DigiKey p/n
TOOL WRAP/STRIP/UNWRAP MOD 30AWG OK Industries/Div of Jonard Ind Corp, WSU-30M Digikey Part Number K105-ND 31.85 Wire Wrap Wire – 30 Gauge Digikey Part Number K229-ND 30 foot roll for 9.65
Ed.4, NFPA 79 Temporary surge voltage (over-voltage) - TOV 871 V Voltage type AC Connection data Wire connection method Screw connection Type of connection Screw connection Stripping length, rated connection 18 mm Tightening torque, min. 2 Nm Tightening torque, max. 4.5 Nm Clamping range, rated connection 16 mm²
Arduino (PlatformIO) Tip We offer a variety of products from Kittenbot which are compatible with Micro:bit. Click here to learn more about these products. Tip If you want to learn more about Artificial Intelligence, don't forget to check our blo
Cat.No.C85E-2 Safety Certified Ceramic Capacitors/ High Voltage Ceramic Capacitors This PDF catalog is downloaded from
–Sparkfun Eagle library ViewPlot (Gerber Viewer) Online DRC –BatchPCB, Advanced Circuits . Demonstration . Key Tips . –Digikey – The leader for professional prototyping & small volume –Mouser – Easier to n
–Email tax exemption certificate to salestax@digikey.com –Ship to home address –Email gim@mit.eduand negarr@mit.edufor approval –Applies to PCB. Reimbursement via direct deposit. 6.101 Spring 2020 Lecture 11 5 OS ‐ECAD OS Number Windows 14 macOS 8 Ubuntu 1 ECAD Number KiCad 14 Circuitm
