Evolution And Expansion Of SOI In VLSI Technologies: IEEE International .
IEEE InternationalSOI ConferenceOct. 2, 2012 - Napa, CA1Evolution and Expansion of SOIin VLSI Technologies:Planar to 3DDr. Gary PattonVP, IBM Semiconductor Research &Development Center 2012 IBM Corporation978-1-4673-2691-9/12/ 31.00 2012 IEEE
Evolution and Expansion of SOI in VLSITechnologies: Planar to 3DI.SOI History and Advantages High Performance Logic Applications Embedded Memories Analog Mixed-Signal ApplicationsII. Fully Depleted Devices Fundamentals FDSOI FinFETsIII. Business ConsiderationsInternational SOI Conference Oct. 2, 20122
The Marketplace is M High-End ServersDesktop Class Processors & PrintersGamesCommunications & StorageOther ConsumerSOI can help take solutions well into the futureInternational SOI Conference Oct. 2, 20123
SOI Value Adders High Speed Switching Superior Isolation– 2X lower junction perimeter capacitance– Improved Short‐Channel Effects– No Well Taps required– Smaller circuit foot‐print– Latch‐up free operation Less susceptibility to soft errors– SER reduced by 5‐7X– Low power high reliability Reduced Variation within Die– Short‐channel Vt roll‐off suppression– Less variation in Vt vs Lgate.– No Well‐Proximity Effects (no deep wellsin SOI)International SOI Conference Oct. 2, 20124
IBM SOI Technology Roadmap10nmScaledFinFET14nmGenerations of technologyLeadershipFinFET3rd Gen. HiK22 nm2nd Gen. HiK32 nmgyoolnchetHigh-K gate dielectric on SOI45 nm65 nm90 nmAdvanced StrainedSiliconLow-k dielectrics DSL130 nm180 nmeDRAMUltra Low-k metal dielectricsImmersion lithography2nd Gen. H/S PDSOIednaitsSuniotvaoninH/S Silicon-on-Insulator International SOI Conference Oct. 2, 2012inIBM5
SOI‐enabled Revolution in Computing SystemsWatson meets Jeopardy!Beats two human competitors on the popular U.S. quiz show "Jeopardy!" in a three-day showdown .What’s in Watson?Watson is powered by 10 racks of IBM POWER 750 systemsProcessor Based on 45 nm SOI Technology with embedded DRAM (eDRAM) memoryWatson can operate at 80 teraflops per second – 80 trillion operations per secondIBM, Nuance to Tune Watson for Use in Health Care & Other ApplicationsInternational SOI Conference Oct. 2, 20126
Integrating DRAM and LogicInnovations to Obtain High Performance Systems Technology:Array passgate Use SOI buried oxide tosimplify process & reduceparasitics Scale the pass transistor forhigher performance Design:Cu M1 BitlineBOXSTIDeeptrenchcapacitorsBulkC ycle tim e (ns)50 Address retention throughconcurrent refresh Innovative direct sensearchitecture for performanceWCt40SOITypical commodity DRAM3020100250International SOI Conference Oct. 2, 2012180130906545Node7
How SOI Facilitates eDRAMProcess Simplification: 10-15% AdderCollar process eliminationBuried Plate process eliminationPlate is nowBuilt into SOI waferInternational SOI Conference Oct. 2, 20128
Integrated Embedded Memory Solutions Memory is 50-70% of the die –key to optimizing performance High Performance eDRAM delivers 3Xmore memory at same die size & power 3X density benefit vs SRAM 5X standby power benefit 1000X SER benefit Compact decoupling cap for noisereduction and I/O is a great 0010.50.40.30.20.10P e rfo rm a n c e (A U )L e a k a g e (n A )100Power 7 Process Chip– 567mm2 32nm SOI eDRAMtechnology– Eight processor cores– 80MB on chip eDRAM shared L3– Equivalent function of 5.4Btransistors due to eDRAMefficiencyCell Size ( m2)International SOI Conference Oct. 2, 20129
eDRAM Scalability eDRAM continues to scale with Logic Innovations enabling continued scaling include:– High‐k Trench capacitor– N‐epi plate– FinFET transfer device Scaling increases leverage over SRAM– Trend expected to continue to foreseeable futureHi K node metal electrodeCell Size (um2)1.000N-epi plate0.1000.01018013090654532221410Technology Node (nm)International SOI Conference Oct. 2, 2012Schematic ofFIN -DTIntegration10
More than Moore PDSOI SOI is a Value‐Add to mature CMOS base Technologies– Integration of wide variety of applications readily enabled High‐Voltage: (dielectric isolation eliminates latch‐up and leakage) High performance analog: ( Complementary Bipolar with low Ccs and dielectricisolation) RF – intrinsically low isolation capacitances and Low harmonic distortion withappropriate substrate design/engineering High reliability applications ( greatly reduced soft error rates)– Superior Isolation High resistivity substrates– Enables high Q passives with low loss– Low Harmonic distortion from coupling between adjacent devices– Reduced coupling from substrate noise Very High‐temperature Operation– No long‐range carrier collection to swamp devices with thermally‐generatedleakages– No Latch‐up concerns Easy support for Positive AND Negative Voltages on dieInternational SOI Conference Oct. 2, 201211
RF SOI for Smartphone ApplicationsIBM technologiesAntenna tunerPower controlRF CMOSPowercontrolSwitchPAPAPAPACellular power ampsRF SOI*, SiGe, RF CMOSCellular transceiversRF CMOS, SiGeWireless SoC transceiver(GPS, Bluetooth, Wi-Fi)RF CMOS, CMOSTV tunerSiGe, RF CMOSWireless SoCtransceiver(GPS, BT, Wi-Fi)TV tunerPowermanagementPower managementHV CMOSCellular transceivers /Analog basebandWi-Fiswitch /LNAPADigital rnational SOI Conference Oct. 2, 2012Antenna tunersRF SOI*, RF MEMSSingle-pole/multi-throw switchRF SOI*Cellular front-end moduleintegration opportunitiesRF SOIWi-Fi RF switch, LNARF SOI*Wi-Fi front-end moduleintegration opportunitiesSiGeWi-Fi power ampsSiGeProcessor integration opportunitiesApplication processorsTechnology Development Alliance/Common Platform technology12
IBM CSOI7RF Technology for Switches Leverage IBM’s proven expertise inSOI of 6 generations (180‐32nm) Based on 180‐nm Lithography– Combination of SOI server technologyand CMRF7SF BEOLG Custom SOI wafer with highresistivity substrate and thick BOXSDFloating Body– High switch isolation Technology FeaturesBuried Oxide (BOX)– 2.5V (std) and 1.5V (opt) FETs– MIMcap and High‐Value serpentineresistor– SOI PSP models for accurate analogmodeling– ESD protection diodesPartially Depleted SOIGate BiasVgR 10KWch 1 mmRF signal1GHz, 10V peakT1T2T3T4 2.5V2.5V2.5V2.5V50 OhmLoadGSStacked DG nFET for switch4-cell device shown as International SOI Conference Oct. 2, 201213
Evolution and Expansion of SOI in VLSITechnologies: Planar to 3DI.SOI History and Advantages High Performance Logic Applications Embedded Memories Analog Mixed-Signal ApplicationsII. Fully Depleted Devices Fundamentals FDSOI FinFETsIII. Business ConsiderationsInternational SOI Conference Oct. 2, 201214
Fully Depleted Device 1VSiGateLeakPDSOIFDSOIFinFETGate controls this.Gate controls this.Gates control this.Gate can not controlbelow that. So currentcan leak through there.No leakage path.No leakage path.Have more Si andthus can carry morecurrent. Better Electrostatics Stronger Gate Control– Lower Vt for the same leakage– Shorter channel for the same Vt Reduced Channel Doping Better SRAMs– Less doping-driven threshold fluctuation– Lower supply voltage (Vmin) – by about 150mV– Lower voltages means lower power – up to 40%International SOI Conference Oct. 2, 2012GateDrainSource15
FDSOI TechnologiesElectrostatic Issues High Sub‐VT slope High DIBLElectrostatic Recovery Low Sub‐VT slope Low DIBLElectrostatic Issues Low Body Biasing EfficiencyIsolated Well/Channel Low Body Biasing EfficiencyInternational SOI Conference Oct. 2, 2012Electrostatic Recovery Low Sub‐VT slope Low DIBLBack Gate Biasing Scheme High Body Biasing Efficiency16
FDSOI Advantages K. Cheng, et al., IEDM 2009Planar technology that leverages conventional CMOS processing and designmethodologyExcellent short channel controlSuperior performance for low-power (LP) applicationsUndoped body means much lower random dopant fluctuations (RDF)FDSOI with competitive performance demonstrated in 20nm GRInternational SOI Conference Oct. 2, 201217Slide 17
FDSOI Back‐gating for Enhanced FlexibilityIndependent multi‐gate device allows the following:– Dynamically changing Vt on devices (trade leakage for performance)– Adjust out typical process induced Vt variation (tighter control of Vt)– Device optimization depending on the use condition: Multi‐Vt enablementInternational SOI Conference Oct. 2, 201218
28nm UTBB FDSOI ‐ Process Integration Gate-first type FEOL, same as ST/ISDA 28LPgate No HP/G-type complex stressors FE process: 80% common with ST/ISDA 28LP20% specific 10% less steps in UTBB vs. 28LP Same LDD implants for all GO1 devices, incl. SRAM No pocket implants 20 implant steps saved vs. 28LP (2 VTs case) BE process: identical to ST/ISDA 28LP Already qualified for volume production STI isolationNW/PW/DNWBPN/BPPBOX removedHKMGSPACEREPI (raised S/D)LDD implantationS/D implantationNiPtSi SilicidationStd backendThin Silicon filmFDSOIBULKBOX 25nm Same defect density vs. ISDA 28LP Improved vs. “HP” technologiesCourtesy ofInternational SOI Conference Oct. 2, 201219
obP”m“HmSOI28FDSO28nm28FD28LP28nm “HP”DVFS not efficientLP2828n28nm LP not fastenough, dynamicpower penalizedby overdrive usageile28nm UTBB FDSOI ‐ Performance & Power28LPI“ HP”mobile28LPCourtesy ofInternational SOI Conference Oct. 2, 201220
Why Double‐Gate CMOSBulk, PDSOI, UTTB-SOITINVGateLSDXDDouble-Gate FETTINVSTINVSubstrateGateLDGate No voltage divider action with substrateNear‐ideal sub‐threshold swing ( lower VT for same off‐current) Scale to smallest LPOLY for a given TOX and TSiSource shielded from drain by two gates Net: Improved density, performance, power.International SOI Conference Oct. 2, 201221
Why FinFET is the Double‐Gate SolutionnGateFiMany intrinsic advantages in FinFETQuasi‐planar processing enables self‐aligned double gates dense front side contacts to both gates symmetric front‐side access to bothsides of source‐drainDrainSourcenterur owC flFinFETAdded benefit: “fin effect” meansWeff larger than footprintInternational SOI Conference Oct. 2, 201222
FinFET AdvantagesPerformanceExample of Device Benefit of FinFET at 20nm .)7980DIBL(mV/V)8282High-Speed BenefitLow-Power Benefit(Better SCEs for same Lgate/Tinv)(Equivalent SCEs for higher Tinv)Lower SRAM power Undoped fin minimizes dopantcontribution to variability Other mechanisms such as work‐functionvariations remain extant Net: Large overall reduction in mismatchInternational SOI Conference Oct. 2, 201223
A Decade of FinFET R&D at IBM/AllianceHigh speedFinFET deviceN&P(2001)FinFETCMOS demo(2002)FinFETfully-depletedRO demo(2003)Conformaldoping inFinFET(2011)0.063um2 SRAMwith FinFET (2010)Functional SRAM0.22um2 (2002)International SOI Conference Oct. 2, 201224
GatesSOI FinFETs: Processing InnovationsKey Innovations: Highly scaled FIN defined by Sidewall-ImageTransfer (SIT)RMG w/ new metal fill solution and reliabilitypackageDual in-situ doped epitaxial source/drain forlow resistanceFinsWorld’s Smallest Flycellw/ Optical LithoGATEFINsFIN70C70CPPPP0.06 20.06um2umIBM CONFIDENTIAL64CPP64CPP0.04u2m 20.04um25
Junction‐isolated Bulk llustrationscourtesy of GSSSubstrateFINFET VariabilityGateXGateCapacitanceTEM courtesy ofUBM TechInsightsHigh KHKSource/DrainLeakageFINGSSTEM courtesy of ChipworksSeveral Key power / performance issues of junction-isolated bulk FinFETs:o Gate Height Variation from STI recess degrades performanceo Gate Capacitance degrades performance and adds powero Source / Drain Leakage increases power (junction and GIDL)International SOI Conference Oct. 2, 201226
FinFET Isolation SchemesJunction-IsolatedBulk FinFETDielectric-IsolatedSOI FinFET (FOX)Gate ElectrodeGate ElectrodeFinFindep/etch ox.BOXDielectric-IsolatedBulk FinFET (FOX)Gate ElectrodeReplacementOxide fillFindep/etch ox.Punch-through stopsilicon substrateFin on bulksilicon substrateFin on SOI– Fin height controlled by ox– Fin height set byetchsubstrate– Complex isolation scheme– Simpler isolationscheme– Fin doping control possibleissue– Requires SOI wafer– Uses bulk waferInternational SOI Conference Oct. 2, 2012silicon substrateFin on oxide over bulk– Doping isolationrequirement removed– Isolation scheme stillcomplex– Uses bulk wafer27
SOI ‐ Bulk FinFET ComparisonMetricComparative AnalysisHistory EffectNo floating body in either: timing like Bulk planar CMOSIsolationBiggest challenge for bulk FinFET.Capacitance/leakage tradeoff.VariabilityHeight control very challenging in bulk fin.Isolation doping requirement also adds within‐fin nonuniformity.Analog FETsNo body contact in either. SOI better due to uniform fin doping.Self‐heatingWorse in SOI FinFET – minor consideration for most applications. Highduty factor circuits may suffer up to 5% drive current penalty.PassivesBulk FinFET can more easily introduce bulk planar passives.SOI FinFET enables planar passives with superior isolation properties. FUNDAMENTALLY the same – design for both not a problem. SIGNIFICANT issues in manufacturing – will be addressed by futuregeneration dielectric isolation or other scheme.International SOI Conference Oct. 2, 201228
Junction‐isolated FinFET Tradeoffs1.E-09S/D Isolation MethodsImin/Weff (A/um)low-leakage (10nm delta Xod)high-speed (no delta Xod)1.E-10BTBTleakage floor1.E-111.E 171.E 181.E 19High Doping minimizes Cgate high leakage floor H/S applicationsDeep Gate low leakage floor Cgate penalty L/P applicationsHActive FinHActive FinXODXODHParasitic FinHParasitic FinApplication-intense lifetimeDoping (1/cm3)International SOI Conference Oct. 2, 2012SOIFinFETH/Sbulk finL/Pbulk finStandby lifetime29
1.2Design Margin (qualitative)Vmax (V)1.110.90.8Vmax (FOx)(SOI)VmaxVmax (bulk)Vmax (Gen1 bulk) Vt-rdf (bulk)δVt-rdf(Gen1 bulk)δVt-rdf(Gen2 FOx) Vt-rdf 60.040.020100δVt-rdf V / Nfin .5)SOI vs Junction‐isolated FinFETsChannel Off current (nA/um) VDD Range is modulated by isolation design High channel doping increases RDFs (AVT) Higher Vmin for SRAM. High channel doping Increases EOX for given VT Lower Vmax (BTI and TDDB). High AVT also increases Die Iddq for given Ioff Increased product leakage spec.International SOI Conference Oct. 2, 201230
FinFET Variability and Manufacturing ChallengesChallengeSolutionResultsFin ProfileVariability‐ Shape/taper‐ Height controlThree SOI benefits: Natural height stop Relaxed etchrequirements forstraighter profile No fill/etch‐backneeded for isolationNear idealshapeInternational SOI Conference Oct. 2, 201231
FinFET Variability and Manufacturing ChallengesChallengeSolutionFin ProfileVariability‐ Shape/taper‐ Height controlThree SOI benefits:Near idealshape Natural height stop Relaxed etchrequirements forstraighter profile No fill/etch‐backneeded for isolationNFET Lgate 25nm150DIBLCut‐last process toeliminates end‐finsystematic offset200DIBL (mV)End FinVariabilityResultsConventional SIT process10050DIBLimprovementNew SIT processYamashita, VLSI 2011005101520253035Fin numberFin numberInternational SOI Conference Oct. 2, 201232
FinFET Variability and Manufacturing ChallengesSolutionFin ProfileVariability‐ Shape/taper‐ Height controlThree SOI benefits:Near idealshape Natural height stop Relaxed etchrequirements forstraighter profile No fill/etch‐backneeded for isolationNFET Lgate 25nm150DIBLCut‐last process toeliminates end‐finsystematic offset200DIBL (mV)End FinVariabilityResultsConventional SIT process10050Yamashita, VLSI 201100Fin Doping‐ Verticalnonuniformityin extn and S/D‐ Doping damagein thin bodyConformal dopingtechniquesDIBLimprovementNew SIT process510152025Fin number3035Fin number1.4NFET1.31.2RodlinreductionNormalized RonChallenge1.1Implanted10.90.80.7conformal doping0.60.5Yamashita, VLSI 20110.41520253035Lgate (nm)International SOI Conference Oct. 2, 201233
Fully Depleted Devices for the Next NodeFDSOIFinFETFDSOI:– Excellent Short Channel Control– Conventional planar processing– Back Gate control possible – helps multi-Vt– Body thickness may limit ultimate scalability– Strong potential for today’s expandingLow Power Applications marketFinFET:– Excellent Short Channel Control– Complex process -- variability & manufacturabilitychallenges– Width Quantization can pose SRAM design challenges– Device electrically wider than physical footprint– Better Scalability: 2x or more relaxation inbody thickness requirement– Capability to meet long-term density, performance, &power requirementsInternational SOI Conference Oct. 2, 201234
Evolution and Expansion of SOI in VLSITechnologies: Planar to 3DI.SOI History and Advantages High Performance Logic Applications Embedded Memories Analog Mixed-Signal ApplicationsII. Fully Depleted Devices Fundamentals FDSOI FinFETsIII. Business ConsiderationsInternational SOI Conference Oct. 2, 201235
SOI Advantages & ChallengesPDSOISOI vs BulkDevice PerformanceDevice LeakageCost (substrate process)Design compatibilityManufacturability (variability,CLY, complexity, cycle time, TTM)Supply Chain (high volume, multi‐sourcing, industry perception) ‐‐‐‐ ‐‐International SOI Conference Oct. 2, 201236
Paradigm Shift in SOI Value PropositionDevice PerformanceDevice LeakageCost (substrate process)Design compatibilityManufacturability (variability,CLY, complexity, cycle time, TTM)Supply Chain (high volume, multi‐sourcing, industry perception)PDSOIFINFETSOI vs BulkSOI vs Bulk ‐‐‐‐ ‐‐ International SOI Conference Oct. 2, 201237
SOI ‐ Bulk FinFET Cost Comparison14nm FINFETSOI vs. Bulk (Implant Isolation)Bulk UniqueProcess AddsSubstrate Contact ( 0‐ 30) savingsCommentsSubstrate contactWell contacts 125‐ 175(2.5% ‐ 3.5%) Area impact from well contactsSTI Isolation 175‐ 300Liner / Fill / CMP / Etch Back / Cleans10:1 STI aspect ratio 60‐ 180(2 ‐ 6) Extra Implants for well isolationIsolation ImplantTotal 360‐ 655 Assumption of high volume full wafer processing cost at 22nm process is 5000 Analysis does not include any yield (CLY) benefit of improved variability with SOI FINFETsInternational SOI Conference Oct. 2, 201238
3 SOI / FOX Substrate Suppliers ReadyThere are least 3 FOX Substrate wafers suppliers ready : SOITEC, MEMC, SEHSOITEC AND SHIN-ETSU HANDOTAI ANNOUNCE NEWSMART CUT PARTNERSHIP AND EXTENDEDTECHNOLOGY COOPERATIONThis agreement will accelerate the development andcapacity expansion for silicon on insulator (SOI) wafers tomeet the market opportunity for FinFETs on SOI and FullyDepleted planar circuitsThe combined capacity of the existing suppliers is 2.3-2.4 million wafers/yr by 2014(substantially early)Additional factory capacity can be put in place by the substrate suppliers : With a 12 months notification, incremental capacity of 3 million wafers/yrInternational SOI Conference Oct. 2, 2012Courtesy of39
Summary SOI has enabled industry leadership in planar CMOS exemplifiedby both digital and analog mixed-signal applications Innovative future opportunities for SOI as Industry moves to FullyDepleted Architectures and beyondUniformity and Variability control are at the forefront! Paradigm shift in SOI value proposition as FinFET era arrivesAcknowledgments: D. Harame, T. Hook, S. Iyer, J. Jagannathan, A. Kumar, E. NowakInternational SOI Conference Oct. 2, 201240
Gate Drain Gate controls this. Gate can not control below that. So current can leak through there. PDSOI Gate 1V Gate controls this. No leakage path. FDSOI Gate 1V Leak Source Drain FinFET Si Gate 1V Gate Source Drain Better Electrostatics Stronger Gate Control - Lower V t for the same leakage - Shorter channel for the same V t
SOI CMOS technology has been used to integrate analog circuits. In this section, SOI CMOS op amp is discussed. Then, the performance comparison of op amps using bulk and SOI CMOS technologies is presented. 3.1 Analysis on SOI CMOS Op amp Figure 5 shows an SOI CMOS single stage op amp with a symmetrical topology. This circuit has a good .
through the addition of the body node for bulk multi gate FET. CMGs used to describe the electrical characteristics of SOI FINFETs and bulk FINFETs. From 1990's to till many BSIM models came into existence like bsim3, 4 conventional 6, with their special features. There are two types of SOI transistors-partial depleted SOI and fully depleted SOI.
SOI CMOS transistors. SOI technology simplifies manufacturing process by eliminating well and field implantation steps and allows fabrication of smaller, denser, and faster microcircuits, with reduced interconnect cross-talk. These features make SOI technology particularly attractive in
12.2 Thermal Expansion Most materials expand when heated and contract when cooled. Thermal expansion is a consequence of the change in the dimensions of a body accompanying a change in temperature. 3 types of expansion: Linear expansion. area expansion, volume expansion In solid, all types of thermal expansion are occurred.
Thermal expansion calculation of pipeline & movement capacity of the expansion joints Expansion amount of the pipeline can easily be calculated with below formula, calculated amount is the key parameter for selecting appopriate expansion joint. ΔL α x Δt x L1 ΔL Expansion amount (mm) α Pipe termal expansion coefficient (mm/m C) (To be
La Vie devant soi « L a Vie devant soi » c’est l’histoire de Momo, un petit garçon qui grandit dans le Belleville des Arabes, des Juifs, des prostituées qui partagent joyeusement leur misère et se débattent contre la vie « parce que ça ne pardonne pas » et « parce qu’il n’est pas nécessaire d’avoir des raisons pour avoir .
Pourtant, le concept de l’estime de soi est loin d’être récent. Il a été décrit pour la première fois en 1890 par le psychologue américain William James, qui a notamment expliqué que l’estime de soi se situe dans la personne et qu’elle se définit par la cohésion entre ses
Enterprise Application Integration (EAI)? a. SOI is just like EAI except that a service bus is used instead of a hub or message bus. b. SOI is different than hub-based EAI, but is the same as EAI using a message bus. c. SOI uses a poi
