LogiCORE IP ChipScope AXI Monitor (v3.02.a)
LogiCORE IP ChipScope AXIMonitor (v3.02.a)DS810 January 18, 2012Product SpecificationIntroductionLogiCORE IP Facts TableThe ChipScope AXI Monitor core is designed tomonitor and debug AXI interfaces. The core allows theprobing of any signals going from a peripheral to theAXI interconnect. For example, the user can instantiatea monitor on a MicroBlaze processor instruction ordata interface to observe all memory transactions goingin and out of the processor.Each monitor core works independently which allowsthe changing of trigger outputs to enable takingsystem-level measurements. By using the auxiliarytrigger input and trigger output ports of a monitor core,multi-level triggering situations can be created tosimplify complex system level measurements. Forexample, if a system consists of a master deviceoperating at 100 MHz and a slave device operating at 50MHz, the transfer of data going from one time domainto the next can be analyzed with the multi-tieredtriggering functionality of monitor cores.Moreover, with this system level measurement, notonly can complex multi-time domain system levelissues be debugged, but latency restrictions in a systemcan be analyzed as well.Core SpecificsVirtex -7, Kintex -7(6), Virtex-6(3),Spartan -6(4)Supported DeviceFamily(1)Supported UserInterfacesAXI4, AXI4-Lite, AXI4-StreamResources UsedConfiguration(5)LUTsFlip 6636685313697Provided with CoreDocumentationProduct Specification; UG029 ChipScope ProSoftware and Cores User Guide;AMBA 4 AXI4, AXI4-Lite, and AXI4-StreamProtocol Assertions User GuideDesign FilesVHDLExample DesignNot ProvidedTest BenchNot ProvidedConstraints FileNot ProvidedSimulation ModelN/ATested Design ToolsFeaturesBRAMs(2)Design EntryTools Selectable data samples Generic Trigger/Data Unit with selectable width Auto-generated CDC file Multiple monitor support in single system throughthe use of trigger in and trigger out ports Allows multiple match units per trigger group Added functionality for more than one match unitper trigger group Adjustable counter size for triggers Selectable AXI Protocol Check monitoring for theAXI4 Memory Map and AXI4-Lite interfaces Supports connection to AXI3 Protocol CoresEDKSimulationN/ASynthesis ToolsXSTSupportProvided by Xilinx @ www.xilinx.com/supportNotes:1. For a list of supported derivative devices, m.2. For the supported versions of the tools, see the ISE Design Suite13: Release Notes Guide.3. For more information on the Virtex-6 devices, see the DS150,Virtex-6 Family Overview.4. For more information on the Spartan-6 devices, see the DS160,Spartan-6 Family Overview.5. For configuration details, see Table 4.6. For more information, see DS180, 7 Series FPGAs Overview. Copyright 2010-2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks ofXilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, Cortex, and PrimeCell are trademarks of ARM in the EU and othercountries. All other trademarks are the property of their respective owners.DS810 January 18, 2012Product Specificationwww.xilinx.com1
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Functional DescriptionThe AXI Monitor is used to debug top-level signals in a system that uses AXI4 protocol specifications by connectingit to an AXI Core using Xilinx Platform Studio (XPS). When placed in an AXI system, the connection of the AXIMonitor probes between the AXI Interconnect and the AXI Core. The signal list is shown in Table 1. The user canmonitor either AXI Memory Map signals through the MON AXI bus interface or AXI Streaming signals throughthe MON AXI S bus interface (but not both) with a single AXI Monitor core. Communication with the ILA core isconducted using a connection to the JTAG port through the ICON core. See Figure 1.X-Ref Target - Figure 1Chipscope AXI MonitorChipscope ProICON CoreChipscope ProILA CoreAXI4 ProtocolChecker CoreControl 0AXI4 Memory MapandAXI4-Lite InterfaceControlMON AXIBusMON AXI(Subset) BusAXI3InterfaceAXI4-StreamInterfaceMON AXI SBusTRIG INTRIG OUTDS810 01Figure 1: ChipScope AXI Monitor Block DiagramThe AXI Monitor is a wrapper for the ChipScope ILA core. It functions the same way as the ChipScope ILA, exceptthat the wrapper creates a specific ILA for monitoring AXI signals by creating trigger groups designed fordebugging purposes. When connected to a core in an AXI system, the user will specify which bus interface is to beconnected (AXI4 Memory Map, AXI4-Streaming, AXI3), then supply values for parameters such as sample size andenable trigger out. These parameters are listed in Table 2.After downloading the bitstream from the design to the FPGA, the ChipScope Analyzer Software tool is used to setup triggering and view waveforms from the system. The core generates a CDC file which is used by the ChipScopeAnalyzer tool to label the AXI signals with the appropriate header information and to define the trigger groups.More information on the ChipScope ILA or the ChipScope Analyzer can be found in the DS299 ChipScope ILAdocument and the UG029 ChipScope Analyzer document.The AXI Monitor core is capable of using multiple AXI Monitors in a single AXI system to monitor multiple coresor can be used together by creating a trigger condition for the TRIG OUT port from one monitor, then connectingit to the TRIG IN port of another monitor. In XPS, when instantiating the AXI Monitor, connect the trigger out andtrigger in pins on separate monitors, then use the ChipScope Analyzer to create the trigger condition on the specificmonitor which will trigger the other to begin capturing data.DS810 January 18, 2012Product Specificationwww.xilinx.com2
LogiCORE IP ChipScope AXI Monitor (v3.02.a)AXI Protocol CheckerThe AXI Protocol Checker can be optionally included in the ChipScope AXI Monitor v3.02.a to check forAXI4-Memory Map and AXI4-Lite Protocol violations. The AXI Protocol Checker is designed around the ARMsystem verilog assertions which have been converted into synthesizable HDL. The AXI Protocol Checker suppliesa flag to the ILA which can be triggered on when a violation of the protocol is detected.Upon enabling the AXI Protocol Checker, the user will be given a choice as to which types of protocol checks are tobe monitored (See Note 1). See Table 3 for the complete list of protocol checks or see the AMBA AXI4, AXI4-Lite,and AXI4-Stream Protocol Assertions User Guide. When the user enables a group of protocol checks, that group offlags will be OR’ed, then the OR’ed signal will be connected to a trigger port of the ChipScope ILA core. If theC MON AXI PC TRACE parameter is set to “Store,” the actual error flags will be connected to the DATA port ofthe ILA and will be able to be monitored. It is important to note that the user must trace the AXI signals thatcorrespond to the protocol check to determine where a protocol violation occurs. Depending on the protocol check,the latency of the violation flag triggering data capture, can occur from 1 to 3 clock cycles after the violation hasoccurred. It is necessary to position the violation flag trigger inside the capture window to more than 3 samples inthe position entry to ensure that the AXI protocol violation will be displayed.1.For v3.02.a of the ChipScope AXI Monitor core, the user will be able to enable the Chks only.I/O SignalsThe core I/O signals are listed and described in the subsequent table.Table 1: I/O Signal DescriptionSignal NameInterfaceSignal TypeInitStatusDescriptionAXI4 Memory Map SignalsCHIPSCOPE ICONCONTROL(35:0)N/AI/OControl bus connection to the ICON core.Mandatory.Note: For XPS designs, the direction of this portis IN.MON AXI TRIG OUTN/AOTrigger output port. (Optional)MON AXI TRIG INN/AITrigger input port. (Optional)MON AXI ACLKAXI4IClockMON AXI ARESETN (1)AXI4IReset (active low)MON AXI AWID(C MON AXIID WIDTH-1:0)AXI4IWrite address channel transaction IDMON AXI AWADDR(C MONAXI ADDR WIDTH-1:0)AXI4IWrite address channel addressMON AXI AWLEN(7:0)AXI4IWrite address burst length: Gives the exactnumber of transfers in a burstMON AXI AWSIZE(2:0)AXI4IWrite address burst size: Indicates the size ofeach transfer in the burstMON AXI AWBURST(1:0)AXI4IWrite address burst typeMON AXI AWLOCKAXI4IWrite address lock typeMON AXI AWCACHE(3:0)AXI4IWrite address cache typeMON AXI AWPROT(2:0)AXI4IWrite address protection typeMON AXI AWQOS(3:0)AXI4IWrite address channel quality of serviceDS810 January 18, 2012Product Specificationwww.xilinx.com3
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 1: I/O Signal Description (Cont’d)Signal NameInitStatusInterfaceSignal TypeMON AXI AWREGION(3:0)AXI4ISelects address range within multirange slaveMON AXI AWVALIDAXI4IWrite address valid: Indicates a valid writeaddress and control information is availableMON AXI AWREADYAXI4IWrite address ready: slave is ready to acceptaddress and control informationMON AXI AWUSERAXI4IWrite address channel USER signalsMON AXI WID(C MON AXIID WIDTH)-1:0)AXI3IWrite data channel transaction IDMON AXI WDATA(C MONAXI DATA WIDTH-1:0)AXI4IWrite data busMON AXI WSTRB(C MONAXI DATA WIDTH/8)-1:0)AXI4IWrite strobes: Indicates which byte lanes havevalid data. MON AXI WSTRB[n] corresponds toMON AXI WDATA[(8xn)] 7:(8xn)]MON AXI WLASTAXI4IIndicates last write data wordIWrite valid: Indicated valid write data and strobesare available.1 write data and strobes available0 write data and strobes not availableMON AXI WVALIDAXI4DescriptionMON AXI WREADYAXI4IWrite ready: Indicates the slave can accept thewrite data1 slave ready0 slave not readyMON AXI WUSERAXI4IWrite data channel USER signalsMON AXI BID(C MON AXIID WIDTH-1:0)AXI4IWrite response channel IDMON AXI BRESP(1:0)AXI4IWrite response: Indicates the status of the writetransactionIWrite response valid: Indicates a valid writeresponse is available1 write response available0 write response not availableMON AXI BVALIDAXI4MON AXI BREADYAXI4IWrite response ready: Indicates the master canaccept the response information1 master ready0 master not readyMON AXI BUSERAXI4IWrite response channel USER signalsMON AXI ARID(C MON AXIID WIDTH-1:0)AXI4IRead address IDMON AXI ARADDR(C MONAXI ADDR WIDTH-1:0)AXI4IRead address busMON AXI ARLEN(7:0)AXI4IRead address burst length: Gives the exactnumber of transfers in a burstMON AXI ARSIZE(2:0)AXI4IRead address burst size: Indicates the size ofeach transfer in the burstMON AXI ARBURST(1:0)AXI4IRead address burst typeDS810 January 18, 2012Product Specificationwww.xilinx.com4
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 1: I/O Signal Description (Cont’d)Signal NameInitStatusInterfaceSignal TypeDescriptionMON AXI ARLOCKAXI4IRead address lock typeMON AXI ARCACHE(3:0)AXI4IRead address cache typeMON AXI ARPROT(2:0)AXI4IRead address protection typeMON AXI ARQOS(3:0)AXI4IRead address channel quality ofserviceMON AXI ARREGION(3:0)AXI4ISelects address range within multirange slaveMON AXI ARVALIDAXI4IRead address valid: When HIGH this signalindicates the read address and controlinformation is valid and will remain valid untilMON AXI ARREADY is HIGH1 Address and control information valid0 Address and control information not validMON AXI ARREADYAXI4IAddress ready: Indicates the slave is ready toaccept an address and associated control signalsMON AXI ARUSERAXI4IRead address channel USER signalsMON AXI RID(C MON AXIID WIDTH-1:0)AXI4IRead data IDMON AXI RDATA(C MONAXI DATA WIDTH-1:0)AXI4IRead data busMON AXI RRESP(1:0)AXI4IRead response: Indicates the status of the readtransaction.MON AXI RLASTAXI4IRead last: Indicates last read data wordIRead data valid: Indicates the read data isavailable and the read transfer can complete1 read data available0 read data not availableMON AXI RVALIDAXI4MON AXI RREADYAXI4IRead ready: Indicates the master can accept theread data and response information1 master ready0 master not readyMON AXI RUSERAXI4IRead data channel USER signalsAXI4-Stream SignalsMON AXI S TVALIDAXI4-StreamIAXI4-Stream validMON AXI S TREADYAXI4-StreamIAXI4-Stream readyMON AXI S TDATA(C MONAXI S TDATA WIDTH-1:0)AXI4-StreamIAXI4-Stream data busMON AXI S TKEEP(C MONAXI S TDATA WIDTH/8-1:0)AXI4-StreamIAXI4-Stream byte qualifierMON AXI S TLASTAXI4-StreamIAXI4-Stream last wordMON AXI S TID(C MON AXIS TID WIDTH-1:0)AXI4-StreamIAXI4-Stream IDMON AXI S TDEST(C MONAXI S TDEST WIDTH-1:0)AXI4-StreamIAXI-Stream destinationDS810 January 18, 2012Product Specificationwww.xilinx.com5
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 1: I/O Signal Description (Cont’d)Signal NameInterfaceSignal TypeMON AXI S TUSER(C MONAXI S TUSER eam user dataNotes:1.If the ChipScope AXI Monitor is connected to a core that does not have the AXI4 ARESETN signal, it will be grounded. If anauxiliary reset signal is needed, manually connect this signal to the Trigger In port of the ChipScope AXI Monitor.Design ParametersThe core design parameters are listed and described in the subsequent table.Table 2: Design ParametersFeature DescriptionParameter eger(0,1)0integer(1:255)1integerAllowable ValuesUser Specified AXI Implemented ParametersActive bus interface typeC USE INTERFACE(0: AXI4/AXI4-Lite,1: AXI4-Stream,2: AXI3 Memory map)Sets number of data samplesC NUM DATA SAMPLES(1024, 2048, 4096, 8192,16384, 32768, 65536,131072)Maximum number ofsequencer levelsC MAX SEQUENCER LEVELSEnable trigger inC USE TRIG INTrigger input widthC TRIG IN WIDTHAWLEN/ARLEN Bus WidthC MON AXI BURST LENGTH(4,8)8integerAWLOCK/ARLOCK Bus WidthC MON AXI LOCK LENGTH(1,2)1integerARADDR Number of MatchUnitsC MON AXI ARADDR NUM OFMATCH(0:4)1integerARADDRCONTROL Numberof Match UnitsC MON AXI ARADDRCONTROLNUM OF MATCH(0:4)1integerAWADDR Number of MatchUnitsC MON AXI AWADDR NUM OFMATCH(0:4)1integerAWADDRCONTROL Numberof Match UnitsC MON AXI AWADDRCONTROLNUM OF MATCH(0:4)1integerBRESP Number of Match UnitsC MON AXI BRESP NUM OF MATCH(0:4)1integerGLOBAL Number of MatchUnitsC MON AXI GLOBAL NUM OFMATCH(0:4)1integerRDATA Number of Match UnitsC MON AXI RDATA NUM OF MATCH(0:4)1integerRDATACONTROL Number ofMatch UnitsC MON AXI RDATACONTROL NUM OF MATCH(0:4)1integerWDATA Number of Match UnitsC MON AXI WDATA NUMOF MATCH(0:4)1integerWDATACONTROL Number ofMatch UnitsC MON AXI WDATACONTROLNUM OF MATCH(0:4)1integerDS810 January 18, 2012Product Specificationwww.xilinx.com6
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 2: Design Parameters (Cont’d)Parameter NameAllowable ValuesDefaultValuesTypeAWUSER Number of MatchUnitsC MON AXI AWUSER NUM OFMATCH(0:4)0integerWUSER Number of MatchUnitsC MON AXI WUSER NUM OFMATCH(0:4)0integerBUSER Number of MatchUnitsC MON AXI BUSER NUM OFMATCH(0:4)0integerARUSER Number of MatchUnitsC MON AXI ARUSER NUM OFMATCH(0:4)0integerRUSER Number of MatchUnitsC MON AXI RUSER NUM OFMATCH(0:4)0integerTCONTROL Number of MatchUnitsC MON AXI S TCONTROL NUMOF MATCH(0:4)0integerTDATA Number of Match UnitsC MON AXI S TDATA NUM OFMATCH(0:4)0integerTUSER Number of Match UnitsC MON AXI S TUSER NUM OFMATCH(0:4)0integerC MON AXI ARADDR MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)range withedgesstringC MON AXI ARADDRCONTROLMATCH TYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI AWADDR MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)range withedgesstringC MON AXI AWADDRCONTROLMATCH TYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringFeature DescriptionARADDR Match TypeARADDRCONTROL MatchTypeAWADDR Match TypeAWADDRCONTROL MatchTypeDS810 January 18, 2012Product Specificationwww.xilinx.com7
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 2: Design Parameters (Cont’d)Feature DescriptionBRESP Match TypeGLOBAL Match TypeRDATA Match TypeRDATACONTROL Match TypeWDATA Match TypeWDATACONTROL Match TypeAWUSER Match TypeDS810 January 18, 2012Product SpecificationAllowable ValuesDefaultValuesTypeC MON AXI BRESP MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI GLOBAL MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI RDATA MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)extendedwith edgesstringC MON AXI RDATACONTROLMATCH TYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI WDATA MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)extendedwith edgesstringC MON AXI WDATACONTROLMATCH TYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI AWUSER MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringParameter Namewww.xilinx.com8
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 2: Design Parameters (Cont’d)Feature DescriptionWUSER Match TypeBUSER Match TypeARUSER Match TypeRUSER Match TypeTCONTROL Match TypeTDATA Match TypeTUSER Match TypeDS810 January 18, 2012Product SpecificationAllowable ValuesDefaultValuesTypeC MON AXI WUSER MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI BUSER MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI ARUSER MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI RUSER MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI S TCONTROLMATCH TYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI S TDATA MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringC MON AXI S TUSER MATCHTYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)basic withedgesstringParameter Namewww.xilinx.com9
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 2: Design Parameters (Cont’d)Feature DescriptionParameter NameAllowable ValuesDefaultValuesTypeARADDR Trigger CounterWidthC MON AXI ARADDR TRIGCOUNT WIDTH(1:32)1integerARADDRCONTROL TriggerCounter WidthC MON AXI ARADDRCONTROLTRIG COUNT WIDTH(1:32)1integerAWADDR Trigger CounterWidthC MON AXI AWADDR TRIGCOUNT WIDTH(1:32)1integerAWADDRCONTROL TriggerCounter WidthC MON AXI AWADDRCONTROLTRIG COUNT WIDTH(1:32)1integerBRESP Trigger Counter WidthC MON AXI BRESP TRIGCOUNT WIDTH(1:32)1integerGLOBAL Trigger CounterWidthC MON AXI GLOBAL TRIGCOUNT WIDTH(1:32)1integerRDATA Trigger Counter WidthC MON AXI RDATA TRIGCOUNT WIDTH(1:32)1integerRDATACONTROL TriggerCounter WidthC MON AXI RDATACONTROLTRIG COUNT WIDTH(1:32)1integerWDATA Trigger Counter WidthC MON AXI WDATA TRIGCOUNT WIDTH(1:32)1integerWDATACONTROL TriggerCounter WidthC MON AXI WDATACONTROLTRIG COUNT WIDTH(1:32)1integerAWUSER Trigger CounterWidthC MON AXI AWUSER TRIGCOUNT WIDTH(1:32)1integerWUSER Trigger Counter WidthC MON AXI WUSER TRIGCOUNT WIDTH(1:32)1integerBUSER Trigger Counter WidthC MON AXI BUSER TRIGCOUNT WIDTH(1:32)1integerARUSER Trigger CounterWidthC MON AXI ARUSER TRIGCOUNT WIDTH(1:32)1integerRUSER Trigger Counter WidthC MON AXI RUSER TRIGCOUNT WIDTH(1:32)1integerTCONTROL Trigger CounterWidthC MON AXI S TCONTROLTRIG COUNT WIDTH(1:32)1integerTDATA Trigger Counter WidthC MON AXI S TDATA TRIGCOUNT WIDTH(1:32)1integerTUSER Trigger Counter WidthC MON AXI S TUSER TRIG COUNT WIDTH(1:32)1integerGLOBAL Trigger Store/Trace toILA Data PortC MON AXI GLOBAL TRACE(0: Do Not Store, 1: Store)1stringAWADDRCONTROL TriggerStore/Trace to ILA Data PortC MON AXI AWADDRCONTROLTRACE(0: Do Not Store, 1: Store)1stringAWADDR Trigger Store/Traceto ILA Data PortC MON AXI AWADDR TRACE(0: Do Not Store, 1: Store)1stringWDATACONTROL TriggerStore/Trace to ILA Data PortC MON AXI WDATACONTROLTRACE(0: Do Not Store, 1: Store)1stringWDATA Trigger Store/Trace toILA Data PortC MON AXI WDATA TRACE(0: Do Not Store, 1: Store)1stringDS810 January 18, 2012Product Specificationwww.xilinx.com10
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 2: Design Parameters (Cont’d)Feature DescriptionParameter NameAllowable ValuesDefaultValuesTypeBRESP Trigger Store/Trace toILA Data PortC MON AXI BRESP TRACE(0: Do Not Store, 1: Store)1stringARADDRCONTROL TriggerStore/Trace to ILA Data PortC MON AXI ARADDRCONTROLTRACE(0: Do Not Store, 1: Store)1stringARADDR Trigger Store/Traceto ILA Data PortC MON AXI ARADDR TRACE(0: Do Not Store, 1: Store)1stringRDATACONTROL TriggerStore/Trace to ILA Data PortC MON AXI RDATACONTROLTRACE(0: Do Not Store, 1: Store)1stringRDATA Trigger Store/Trace toILA Data PortC MON AXI RDATA TRACE(0: Do Not Store, 1: Store)1stringAWUSER Trigger Store/Traceto ILA Data PortC MON AXI AWUSER TRACE(0: Do Not Store, 1: Store)0stringWUSER Trigger Store/Trace toILA Data PortC MON AXI WUSER TRACE(0: Do Not Store, 1: Store)0stringBUSER Trigger Store/Trace toILA Data PortC MON AXI BUSER TRACE(0: Do Not Store, 1: Store)0stringARUSER Trigger Store/Traceto ILA Data PortC MON AXI ARUSER TRACE(0: Do Not Store, 1: Store)0stringRUSER Trigger Store/Trace toILA Data PortC MON AXI RUSER TRACE(0: Do Not Store, 1: Store)0stringTCONTROL TriggerStore/Trace to ILA Data PortC MON AXI S TCONTROLTRACE(0: Do Not Store, 1: Store)1stringTDATA Trigger Store/Trace toILA Data PortC MON AXI S TDATA TRACE(0: Do Not Store, 1: Store)1stringTUSER Trigger Store/Trace toILA Data PortC MON AXI S TUSER TRACE(0: Do Not Store, 1: ring(-1, -2, -3)-2stringaxi4, axi4-lite, axi3axi4stringgenericstring0integerSystem Specified AXI Implemented ParametersDevice familyC FAMILYDevice/partC DEVICEDevice packageC PACKAGEDevice speed gradeC SPEEDGRADEvirtex6, spartan6AXI memory map BUSIF name C MON AXI PROTOCOLAXI stream BUSIF nameC MON AXI S PROTOCOLSystem supports threadsC MON AXI SUPPORTSTHREADSAXI memory map ID widthC MON AXI ID WIDTH1integerAXI stream ID widthC MON AXI S TID WIDTH1integerAXI memory map addresswidthC MON AXI ADDR WIDTH3232integerAXI stream TDEST widthC MON AXI S TDEST WIDTH(0:32)32integerAXI4 memory map data widthC MON AXI DATA WIDTH(32, 64, 128, 256)32integerAXI stream data widthC MON AXI S TDATA WIDTH(32, 64, 128, 256)32integerWrite address USER port buswidthC MON AXI AWUSER WIDTH(1:256)(1)1integerDS810 January 18, 2012Product Specificationwww.xilinx.com(0,1)11
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 2: Design Parameters (Cont’d)Feature DescriptionParameter NameAllowable ValuesDefaultValuesTypeWrite data USER port buswidthC MON AXI WUSER WIDTH(1:256)(1)1integerWrite response USER portbus widthC MON AXI BUSER WIDTH(1:256)(1)1integerRead address USER port buswidthC MON AXI ARUSER WIDTH(1:256)(1)1integerRead data USER port buswidthC MON AXI RUSER WIDTH(1:256)(1)1integerStreaming USER port buswidthC MON AXI S TUSER WIDTH(1:256)(1)1integerSystem supports readoperationsC MON AXI SUPPORTS READ(0,1)1integerSystem supports writeoperationsC MON AXI SUPPORTS WRITE(0,1)1integer(0:1)0integerbasic withedgesstringAXI Protocol Checker ParametersProtocol Checker Number ofMatch UnitsC MON AXI PC NUM OFMATCHProtocol Checker Match TypeC MON AXI PC MATCH TYPE(basic basic, basic withedges basic with edges,extended extended,extended withedges extended withedges, range range, rangewith edges range withedges)Protocol Checker TriggerCounter WidthC MON AXI PC TRIG COUNTWIDTH(1:32)1integerProtocol Checker TriggerStore/Trace to ILA Data PortC MON AXI PC TRACE(0: Do Not Store, 1: Store)0stringHandshake Protocol ChecksEnableC MON AXI EN HANDSHAKECHECKS(0,1)0integerComplex Protocol ChecksEnableC MON AXI EN COMPLEXCHECKS(0,1)0integerExclusive Access ProtocolChecks EnableC MON AXI EN EXCLUSIVECHECKS(0,1)0integerIgnore Protocol Checks EnableC MON AXI EN IGNORECHECKS(0,1)0integerIllegal Value Protocol ChecksEnableC MON AXI EN ILLEGALVALUE CHECKS(0,1)0integerReset Protocol Checks EnableC MON AXI EN RESET CHECKS(0,1)0integerAuxiliary Protocol ChecksEnableC MON AXI EN AUX CHECKS(0,1)0integerARM Recommended Max WaitProtocol Checks EnableC MON AXI EN ARM RECWAIT CHECKS(0,1)0integerARM Recommended ProtocolChecks EnableC MON AXI EN ARM RECONLY CHECKS(0,1)0integerDS810 January 18, 2012Product Specificationwww.xilinx.com12
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 2: Design Parameters (Cont’d)Feature DescriptionParameter NameAllowable ValuesDefaultValuesType9595integerProtocol Checker Error BusWidthC MON AXI PC ERRORCOUNTSize of FIFO for StoringOutstanding Read BurstsC MON AXI PC MAXRBURST(2:32)16integerSize of FIFO for StoringOutstanding Read BurstsC MON AXI PC MAXWBURST(2:32)16integerWidth of Exclusive AccessMonitorC MON AXI PC EXMON WIDTH(1:32)1integerNotes:1.These parameters are set by the XPS tool automatically after the ChipScope AXI Monitor is connected to another Xilinx AXI IPcore. If any port(s) for which these parameters set the width are not used, retain the default widths and the XPS tool will ground theport(s). Do not enter a value of 0 in the MHS file to disable the default value.AXI Protocol Checks and DescriptionsThe AXI Protocol Checks are listed and described in the subsequent table.Table 3: AXI Protocol Checks and DescriptionsName of Protocol CheckAXI4 ERRM AWADDRSTABLETypeDescriptionReady/Valid Handshake ChecksAWADDR must remain stable when AWVALID is assertedand AWREADY lowAXI4 ERRM AWBURSTReady/Valid Handshake ChecksSTABLEAWBURST must remain stable when AWVALID is assertedand AWREADY lowAXI4 ERRM AWCACHESTABLEReady/Valid Handshake ChecksAWCACHE must remain stable when AWVALID is assertedand AWREADY lowAXI4 ERRM AWIDSTABLEReady/Valid Handshake ChecksAWID must remain stable when AWVALID is asserted andAWREADY lowAXI4 ERRM AWLENSTABLEReady/Valid Handshake ChecksAWLEN must remain stable when AWVALID is assertedand AWREADY lowAXI4 ERRM AWLOCKSTABLEReady/Valid Handshake ChecksAWLOCK must remain stable when AWVALID is assertedand AWREADY lowAXI4 ERRM AWPROT SReady/Valid Handshake ChecksTABLEAWPROT must remain stable when AWVALID is assertedand AWREADY lowAXI4 ERRM AWSIZESTABLEReady/Valid Handshake ChecksAWSIZE must remain stable when AWVALID is assertedand AWREADY lowAXI4 ERRM AWQOSSTABLEReady/Valid Handshake ChecksAWQOS must remain stable when AWVALID is assertedand AWREADY lowAXI4 ERRM AWREGIONReady/Valid Handshake ChecksSTABLEAWREGION must remain stable when ARVALID isasserted and AWREADY lowAXI4 ERRM AWVALIDSTABLEReady/Valid Handshake ChecksOnce AWVALID is asserted, it must remain asserted untilAWREADY is highAXI4 ERRM WDATASTABLEReady/Valid Handshake ChecksWDATA must remain stable when WVALID is asserted andWREADY lowAXI4 ERRM WLASTSTABLEReady/Valid Handshake ChecksWLAST must remain stable when WVALID is asserted andWREADY lowAXI4 ERRM WSTRBSTABLEReady/Valid Handshake ChecksWSTRB must remain stable when WVALID is asserted andWREADY lowDS810 January 18, 2012Product Specificationwww.xilinx.com13
LogiCORE IP ChipScope AXI Monitor (v3.02.a)Table 3: AXI Protocol Checks and Descriptions (Cont’d)Name of Protocol CheckTypeDescriptionAXI4 ERRM WVALIDSTABLEReady/Valid Handshake ChecksOnce WVALID is asserted, it must remain asserted untilWREADY is highAXI4 ERRS BIDSTABLEReady/Valid Handshake ChecksBID must remain stable when BVALID is asserted andBREADY lowAXI4 ERRS BRESPSTABLEReady/Valid Handshake ChecksBRESP must remain stable when BVALID is asserted andBREADY lowAXI4 ERRS BVALIDSTABLEReady/Valid Handshake ChecksOnce BVALID is asserted, it must remain asserted untilBREADY is highAXI4 ERRM ARADDRSTABLEReady/Valid Handshake ChecksARADDR must remain stable when ARVALID is assertedand ARREADY lowAXI4 ERRM ARBURSTSTABLEReady/Valid Handshake ChecksARBURST must remain stable when ARVALID is assertedand ARREADY lowAXI4 ERRM ARCACHESTABLEReady/Valid Handshake ChecksARCACHE must remain stable when ARVALID is assertedand ARREADY lowAXI4 ERRM ARIDSTABLEReady/Valid Handshake ChecksARID must remain stable when ARVALID is asserted andARREADY lowAXI4 ERRM ARLENSTABLEReady/Valid Handshake ChecksARLEN must remain stable when ARVALID is asserted andARREADY low.AXI4 ERRM ARLOCKSTABLEReady/Valid Handshake ChecksARLOCK must remain stable when ARVALID is assertedand ARREADY lowAXI4 ERRM ARPROTSTABLEReady/Valid Handshake ChecksARPROT must remain stable when ARVALID is assertedand ARREADY lowAXI4 ERRM ARSIZESTABLEReady/Valid Handshake ChecksARSIZE must remain sta
AXI4 Memory Map and AXI4-Lite interfaces Supports connection to AXI3 Protocol Cores LogiCORE IP ChipScope AXI Monitor (v3.02.a) DS810 January 18, 2012 Product Specification LogiCORE IP Facts Table Core Specifics Supported Device Family (1) Virtex -7, Kintex -7(6), Virtex-6(3), Spartan -6(4) Supported User Interfaces AXI4, AXI4-Lite .
“Video IP: AXI Feature Adoption” section of the AXI Reference Guide (UG761). AXI4 Data Width The AXI VDMA core supports the primary AXI4 data bus width of 32, 64, 128, 256, 512, and 1024 bits. AXI4‐Stream Data Width The AXI VDMA core supports the primary AXI4-S tre
This completes tutorial 3 which included: Overview of the ChipScope Pro VIO. Generation of ChipScope Pro ICONand VIO cores. Insertion of ChipScope Pro cores into the project from Tutorial 2. Generation of BlockRAMcore. Insertion of BlockBAMinto the project and proper assignment of signals.
AXI Reference Guide www.xilinx.com 5 UG761 (v13.1) March 7, 2011 Chapter 1 Introducing AXI for Xilinx System Development Introduction Xilinx has adopted the Advanced eXtensible Interface (AXI) protocol for Intellectual Property (IP) cores beginning with the Sparta
AXI Bridge for PCI Express v2.5 www.xilinx.com 8 PG055 November 19, 2014 Chapter 2 Product Specification Figure 2-1 shows the architecture of the AXI Bridge for PCI Express core. The Register block contains registers used in the AXI Bridge for PCI Express core for dynamically mapping the AXI4 memory mapped (MM) address range provided using the
memory-mapped master devices to one or more memory-mapped slave devices. Note: The AXI SmartConnect core is intended for memory-mapped transfers only. For AXI4-Stream transfers, see the LogiCORE IP AXI4-Stream InterConnect Product Guide (PG085) [Ref 1]. The AXI SmartConnect is a Hierarchical IP block that is added to a Vivado IP integrator block
AXI EMC v3.0 www.xilinx.com 7 PG100 April 5, 2017 Chapter 1: Overview AXI4-Lite Interface AXI EMC core provides AXI4-Lite slave interface to allow access to Internal Control and Status registers of the c
SelectIO Resources DMA 8 Channel CoreSight Components Programmable Logic DAP DevC SWDT DMA Sync Notes: 1) Arrow direction shows control (master to slave) 2) Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom 3) Dashed line box indicates 2nd processor in dual-core devices ACP 256K SRAM ation .
Grade-specific K-12 standards in Reading, Writing, Speaking and Listening, and Language translate the broad aims of The Arizona English Language Arts Anchor Standards into age- and attainment-appropriate terms. These standards allow for an integrated approach to literacy to help guide instruction. Process for the Development of the Standards In response to the call from Superintendent Douglas .
