LogiCORE IP AXI Video Direct Memory Access V6
LogiCORE IP AXIVideo Direct MemoryAccess v6.0Product Guide for VivadoDesign SuitePG020 March 20, 2013
Table of ContentsChapter 1: OverviewFeature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6788Chapter 2: Product SpecificationPerformance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Genlock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Chapter 3: Designing with the CoreGeneral Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3939414142Chapter 4: Customizing and Generating the CoreVivado Integrated Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Basic Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Advanced Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Chapter 5: Constraining the CoreChapter 6: Detailed Example DesignTriple Frame Buffer Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Example Read (MM2S) Path Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Example Write (S2MM) Path Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com2
Appendix A: MigratingAppendix B: DebuggingFinding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Vivado Lab Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Appendix C: Additional Design InformationAppendix D: Frame Pointers Grey Code OutputsAppendix E: Additional ResourcesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Notice of Disclaimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com686869703
IP FactsIntroductionThe Advanced eXtensible Interface Video DirectMemory Access (AXI VDMA) core is a soft XilinxIntellectual Property (IP) core. It provideshigh-bandwidth direct memory access betweenmemory and AXI4-Stream video type targetperipherals including peripherals whichsupport AXI4-Stream Video Protocol asdescribed in the Video IP: AXI Feature Adoptionsection of the AXI Reference Guide (UG761).LogiCORE IP Facts TableCore SpecificsSupportedDeviceFamily (1)SupportedUser InterfacesResourcesTest Bench Primary AXI4 data width support of 32, 64,128, 256, 512, and 1024 bitsConstraintsFile Primary AXI4-Stream data width support ofmultiples of 8 up to 1024 bitsOptional Genlock Synchronization Independent, asynchronous channeloperation Dynamic clock frequency change ofAXI4-Stream interface clocksVHDLExampleDesignAXI4 Compliant See Table 2-4, Table 2-5, and Table 2-6Provided with Core Optional Data Re-Alignment EngineAXI4, AXI4-Lite, AXI4-StreamDesign Files (2)Features Zynq -7000, Virtex -7, Kintex -7, Artix -7,Not ApplicableNot ProvidedProvidedSimulationModelNot ProvidedSupportedS/W Drivers (3)Standalone and LinuxTested Design Flows (4)Design EntrySimulationVivado Design SuiteMentor Graphics Questa SIMVivado SimulatorSynthesis Optional frame advance or repeat on error Supports up to 32 frame buffersVivado SynthesisSupportProvided by Xilinx @ www.xilinx.com/support1. For a complete list of supported devices, see Vivado IPcatalog.2. Contains few Verilog files. Top level is VHDL.3. Standalone driver information can be found in the SDKinstallation directory.See xilinx drivers.htm in install directory /doc/usenglish. Linux OS and driversupport information is available from wiki.xilinx.com.4. For the supported versions of the tools, see the XilinxDesign Tools: Release Notes Guide .LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com4Product Specification
Chapter 1OverviewMany video applications require frame buffers to handle frame rate changes or changes tothe image dimensions (scaling or cropping). The AXI VDMA is designed to allow for efficienthigh-bandwidth access between AXI4-Stream video interface and AXI4 interface.Figure 1-1 illustrates the AXI VDMA Block Diagram.X-Ref Target - Figure 1-1&RQWURO DQG 6WDWXV ;, 0HPRU\ 0DS'DWD0RYHU5HJLVWHUV/LQH %XIIHU ;, /LWH ;, 6WUHDP; Figure 1‐1:AXI VDMA Block DiagramAfter registers are programmed through the AXI4-Lite interface, Control/ Status logic blockgenerates appropriate commands to the Datamover to initiate Write and Read commandson the AXI4 Master interface.A configurable asynchronous line buffer is used to temporarily hold the pixel data prior towriting it out to AXI4-Memory Map interface or AXI4-Stream interface.In the Write path, the AXI VDMA accepts frames on the AXI4-Stream Slave interface andwrites it to system memory using the AXI4 Master interface.In the Read path, the AXI VDMA uses the AXI4 Master interface for reading frames fromsystem memory and outputs it on the AXI4-Stream Master interface.Both write and read paths operate independently. The AXI VDMA also provides an option tosynchronize the incoming/outgoing frames with external synchronization signal.LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com5
Chapter 1: OverviewFeature SummaryAXI4 CompliantThe AXI VDMA core is fully compliant with the AXI4 interface, AXI4-Stream interface andAXI4-Lite interface. The AXI4-Stream also supports the Video Protocol as described in the“Video IP: AXI Feature Adoption” section of the AXI Reference Guide (UG761).AXI4 Data WidthThe AXI VDMA core supports the primary AXI4 data bus width of 32, 64, 128, 256, 512, and1024 bits.AXI4‐Stream Data WidthThe AXI VDMA core supports the primary AXI4-Stream data bus width of multiples of 8 bitsup to 1024 bits. The AXI4-Stream data width must be less than or equal to the AXI4 datawidth for the respective channel.Data Realignment EngineThe AXI VDMA core supports the optional Data Realignment Engine (DRE). The DRE letsunaligned access to memory, allowing the frame buffer to start at any address in memory.There is no restriction on the hsize and stride as well. This feature is supported for theAXI4-Stream interface width up to 64 bits.Genlock SynchronizationThe AXI VDMA supports a mechanism to synchronize writing and reading of frames in theframe buffer through genlock synchronization. Each channel of the AXI VDMA can bedesigned to operate as either a Genlock Master/Slave or Dynamic Genlock Master/Slave. Byusing this feature, the master and slave are kept in sync by not allowing both to use thesame buffer at the same time.The AXI VDMA core supports internal Genlock Bus by default when both read and writechannels are selected. This eliminates the need for an external connection between thewrite and read channels. See Genlock Synchronization in Chapter 2 for more details.Asynchronous ChannelsThe AXI VDMA core supports asynchronous clock domains for AXI4-Lite, S2MMAXI4-Stream interface, MM2S AXI4-Stream interface, S2MM AXI4 interface and MM2S AXI4interface.LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com6
Chapter 1: OverviewFrame Sync OptionsThe AXI VDMA core supports the following 3 sources for frame synchronization. AXI4-Stream based frame synchronization using tuser(0) port Drives start-of-frame on m axis mm2s tuser(0) output for read path Synchronizes the incoming frame with start-of-frame on s axis s2mm tuser(0)input for write path Streaming to Memory Mapped frame sync port (s2mm fsync) Memory Mapped to Streaming frame sync port (mm2s fsync)32 Frame BuffersThe AXI VDMA core supports addressing up to 32 frame buffers. They are divided into 2banks of 16 buffers each.Dynamic Clock Frequency Change on AXI4‐Stream InterfaceThe AXI VDMA core allows changing the AXI4-Stream interface clock dynamically tosupport different video frame resolution and frame rates.Frame Advance or Repeat on ErrorWhen an error is detected in a particular frame, this optional feature allows you to let theframe number advance on the next frame sync or not advance and reuse the errored framenumber. It is controlled by VDMACR bit15.ApplicationsThe AXI VDMA core provides high-speed data movement between system memory andAXI4-Stream Video Protocol Video IP. See Triple Frame Buffer Example in Chapter 6 forquick bring up of AXI VDMA.LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com7
Chapter 1: OverviewUnsupported FeaturesThe following AXI4 features are not supported by the AXI VDMA design. User signals on AXI4 Interface Locked transfers Exclusive transfers FIXED and WRAP Burst transfersLicensing and Ordering InformationThis Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado Design Suite under the terms of the Xilinx End User License. Information about this andother Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. Forinformation about pricing and availability of other Xilinx LogiCORE IP modules and tools,contact your local Xilinx sales representative.LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com8
Chapter 2Product SpecificationPerformanceThe AXI VDMA is characterized as per the benchmarking methodology described inAppendix A, IP Characterization and fMAX Margin System Methodology, Vivado DesignSuite User Guide: Designing with IP (UG896). Table 2-1 shows the results of thecharacterization runs.Table 2‐1:Maximum FrequenciesFamilySpeed GradeFmax iCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com9
Chapter 2: Product SpecificationLatencyTable 2-2 shows the AXI VDMA core latency cycles measured on write (s2mm) and read(mm2s) paths. It does not include system dependent latency or throttling.Table 2‐2:AXI VDMA LatencyDescriptionClocksRead (MM2S) ChannelFrame Sync out to AXI4 Address Valid14AXI4 Read Valid to AXI4-Stream Data Valid4Current Frame AXI4-Stream TLAST to Next Frame Sync out8Write (S2MM) ChannelAXI4-Stream Data Valid to AXI4 Write Address Valid14m axi s2mm awvalild and m axi s2mm awready 1 to m axi s2mm wvalid2Current AXI4 Write Last to next Frame Sync out11ThroughputTable 2-3 shows the AXI VDMA throughput measured for different data widths. It wasmeasured using standard HD frames on hardware.Table 2‐3:AXI VDMA ThroughputMemory Map & Streaming Data Widths(in bits)Throughput (frames/sec)329664192128384256500512680LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com10
Chapter 2: Product SpecificationResource UtilizationThe AXI VDMA resource utilization for various parameter combinations measured withVirtex -7 FPGA (Table 2-4), Kintex -7 FPGA (Table 2-5), and Artix -7 FPGA (Table 2-6)target device.Note: Resource numbers for Zynq -7000 devices are expected to be similar to 7 series devicenumbers.Table 2‐4:Resource Estimations for Virtex‐7 FPGAsRead ChannelWrite ChannelMemory MapData WidthStreamMemory MapData Width Data WidthStreamData WidthRegistersLUTsSlicesBlock 6412864363825001254425664256644254280314438Table 2‐5:Resource Estimations for Kintex‐7 FPGAsRead ChannelWrite ChannelMemory MapData WidthStreamData WidthMemory Map StreamData WidthData WidthRegisters LUTsSlicesBlock 412864363824981146425664256644274280913398Table 2‐6:Resource Estimations for Artix‐7 FPGAsRead ChannelWrite ChannelMemory MapData WidthStream DataWidthMemory MapData WidthStream DataWidthRegistersLUTsSlicesBlock E IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com11
Chapter 2: Product SpecificationPort DescriptionsThis section describes the details for each interface. In addition, detailed information aboutconfiguration and control registers is included.The AXI VDMA signals are described in Table 2-7.Table 2‐7:AXI VDMA I/O Signal DescriptionSignal NameSignal InitType StatusInterfaceDescriptionClock, Reset and Interrupt Interface Signalss axi lite aclkClockIAXI VDMA AXI4-Lite interface clockm axi mm2s aclkClockIAXI VDMA MM2S clockm axi s2mm aclkClockIAXI VDMA S2MM clockm axis mm2s aclkClockIAXI VDMA MM2S AXIS clocks axis s2mm aclkClockIAXI VDMA S2MM AXIS clockAXI VDMA Reset. Active-Low reset. Whenasserted low, resets entire AXI VDMA core.Must be synchronous to s axi lite aclk andasserted for a minimum eight clock cycles.axi resetnResetImm2s introutInterruptO0Interrupt Out for Memory Map to StreamChannelInterruptO0Interrupt Out for Stream to Memory MapChannels2mm introutAXI4‐Lite Interface Signalss axi lite*S AXI LITE--See Appendix A of the AXI Reference Guide(UG761) for the description of AXI4 Signals.AXI4 Read Interface Signalsm axi mm2s*M AXI MM2S--See Appendix A of the AXI Reference Guide(UG761) for the description of AXI4 Signals.AXI4 Write Interface Signalsm axi s2mm*M AXI S2MM--See Appendix A of the AXI Reference Guide(UG761) for the description of AXI4 Signals.AXI4‐Stream Master Interface Signalsm axis mm2s*M AXIS MM2S--See Appendix A of the AXI Reference Guide(UG761) for the description of AXI4 Signals.AXI4‐Stream Slave Interface Signalss axis s2mm*LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013S AXIS S2MM--www.xilinx.comSee Appendix A of the AXI Reference Guide(UG761) for the description of AXI4 Signals.12
Chapter 2: Product SpecificationTable 2‐7:AXI VDMA I/O Signal Description (Cont’d)Signal NameInterfaceSignal InitType StatusDescriptionVideo Synchronization Interface Signalsmm2s fsyncs2mm fsyncFrame SyncFrame SyncIMM2S Frame Sync Input. When enabled,VDMA Operations begin on each falling edgeof fsync. AXI VDMA expects this signal to beasserted for one m axis mm2s aclk cycle.IS2MM Frame Sync Input. When enabled,VDMA operations begin on each falling edgeof fsync. AXI VDMA expects this signal to beasserted for one s axis s2mm aclk cycle.Genlock Interface Signalsmm2s frame ptr in(5: 0)GenlockImm2s frame ptr out(5:0)GenlockOs2mm frame ptr in(5:0)GenlockIs2mm frame ptr out(5:0)GenlockOLogiCORE IP AXI VDMA v6.0PG020 March 20, 2013Read (MM2S) Channel Frame Pointer Input.See Genlock Synchronization for more detailson different Genlock modes.zerosRead (MM2S) Channel Frame Pointer Output.See Genlock Synchronization for more detailson different Genlock modes.Write (S2MM) Channel Frame Pointer Input.See Genlock Synchronization for more detailson different Genlock modes.zeroswww.xilinx.comWrite (S2MM) Channel Frame Pointer Output.See Genlock Synchronization for more detailson different Genlock modes.13
Chapter 2: Product SpecificationRegister SpaceThe AXI VDMA core register space is shown in Table 2-8. The AXI VDMA Registers arememory-mapped into non-cacheable memory space. This memory space must be alignedon a AXI word (32-bit) boundary.EndianessAll registers are in Little Endian format, as shown in Figure 2-1.X-Ref Target - Figure 2-1LSBMSBAddr Offset 0x0331BYTE3Addr Offset 0x0224 2316 15BYTE2Figure 2‐1:Addr Offset 0x01BYTE 1Addr Offset 0x008 7BYTE 0032‐bit Little Endian ExampleAXI VDMA Register Address MapTable 2‐8:Register Address MapAddress Space OffsetNameDescription00hMM2S VDMACRMM2S VDMA Control Register04hMM2S VDMASRMM2S VDMA Status Register08 to 10hReservedN/A14hMM2S REG INDEXMM2S Register Index18h to 24hReservedN/A28hPARK PTR REGMM2S and S2MM Park Pointer Register2ChVDMA VERSIONVideo DMA Version Register30hS2MM VDMACRS2MM VDMA Control Register34hS2MM VDMASRS2MM VDMA Status Register38h to 40hReservedN/A44hS2MM REG INDEXS2MM Register Index48h to 4ChReservedN/A50hMM2S VSIZEMM2S Vertical Size Register54hMM2S HSIZEMM2S Horizontal Size Register58hMM2S FRMDLY STRIDEMM2S Frame Delay and Stride Register5Ch to 98hMM2S START ADDRESS(1 to 16) (1)MM2S Start Address (1 to 16)9ChReservedN/AA0hS2MM VSIZES2MM Vertical Size RegisterLogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com14
Chapter 2: Product SpecificationTable 2‐8:Register Address Map (Cont’d)Address Space OffsetNameDescriptionA4hS2MM HSIZES2MM Horizontal Size RegisterA8hS2MM FRMDLY STRIDES2MM Frame Delay and Stride RegisterACh to E8hS2MM START ADDRESS (1 to 16)ECh to F4hReserved(1)S2MM Start Address (1 to 16)N/A1. Start Addresses 2 to 32 for MM2S and S2MM depend on Frame Buffers parameter. Start address registers greater than FrameBuffers setting are reserved. See the MM2S REG INDEX and S2MM REG INDEX register definitions for accessing 32 startaddress registers.Memory Map to Stream Register DetailsRegister Access Type Description RO Read Only. Writing has no effect R/W Read and Write Accessible R/WC Read / Write to ClearMM2S VDMACR (MM2S VDMA Control Register – Offset 00h)This register provides control for the Memory Map to Stream VDMA Channel.X-Ref Target - Figure 2-2Repeat En RSVD3116 15 14 13 12 11 10 9 824 23RSVDRdPtrNmbr(Mstr in Control)RSVD76GenlockSrcRSVDCircular ParkGenlockEnRSVD543 2 10RSVDResetRSRSVDFigure 2‐2:LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013MM2S VDMACR Registerwww.xilinx.com15
Chapter 2: Product SpecificationTable 2‐9:BitsMM2S VDMACR Register DetailsField NameDefault AccessDescriptionValueTypeWrite has no effect and read as default.31-161514ReservedRepeat EnErr IrqEn0001h1h0hNote: Bits [31:24] are used as delay counter and BitsRO[23:16] are used as frame counter for generatingcorresponding interrupts when enabled. See Appendix C,Additional Design Information to enable these features .R/WEnables repeat or advance frame when AXI VDMAencounters frame error. This is applicable when AXI VDMAis configured in Genlock Master or Dynamic GenlockMaster.0 - Advance to next frame on frame errors1 - Repeat previous frame on frame errorsR/WInterrupt on Error Interrupt Enable. When set to 1, allowsVDMASR.Err Irq to generate an interrupt out.0 Error Interrupt disabled1 Error Interrupt enabledWriting has no effect on AXI VDMA.13-1211-8ReservedRdPntrNum0h0hR/WNote: Bit 13 is used to enable delay count interruptand bit 12 is used to enable frame count interrupt. SeeAppendix C, Additional Design Information to enablethese features.R/WIndicates the master in control when MM2S channel isconfigured for Genlock slave/Dynamic GenlockMaster/Dynamic Genlock Slave or reserved otherwise.0000b Controlling entity is Entity 10001b Controller entity is Entity 20010b Controller entity is Entity 3and so on.7GenlockSrc1hR/WSelects internal or external genlock bus. This bit is set bydefault when both channels are enabled and areconfigured as a valid Genlock pair.0 External Genlock1 Internal Genlock6-5Reserved0hR/WWrite has no effect on AXI VDMA.Writing has no effect on AXI VDMA.4ReservedLogiCORE IP AXI VDMA v6.0PG020 March 20, 20130hR/WNote: This bit is used to enable frame counter. SeeAppendix C, Additional Design Information to enablethese features.www.xilinx.com16
Chapter 2: Product SpecificationTable 2‐9:BitsMM2S VDMACR Register Details (Cont’d)Field NameDefault AccessDescriptionValueTypeEnables Genlock or Dynamic Genlock Synchronization.0 Genlock or Dynamic Genlock Synchronization disabled.Genlock input is ignored by MM2S.1 Genlock or Dynamic Genlock Synchronization enabled.MM2S synchronized to Genlock frame input.3GenlockEn0hR/WNote: This value is valid only when the channel isconfigured as Genlock Slave or Dynamic Genlock Master orDynamic Genlock Slave. If configured for Genlock Mastermode, this bit is reserved and always reads as zero.See Genlock Synchronization for more details on differentGenlock modes.210ResetCircular ParkRS0h1h0hR/WSoft reset for AXI VDMA MM2S channel. Setting this bit toa 1 causes the AXI VDMA MM2S channel to be reset. Resetis accomplished gracefully. Pending commands/transfersare flushed or completed. AXI4-Stream reset output isasserted. Setting VDMACR.Reset 1 only resets the MM2Schannel. After completion of a soft reset all MM2Sregisters and bits are in the default state. This bit will bezero at the end of the reset cycle.0 Normal operation1 Reset in progressR/WIndicates frame buffer Circular mode or frame buffer Parkmode.0 Park Mode – Engine will park on frame bufferreferenced by PARK PTR REG.RdFrmPntrRef.1 Circular Mode – Engine continuously circles throughframe buffers.R/WRun / Stop controls running and stopping of the VDMAchannel. For any VDMA operations to commence, the AXIVDMA engine must be running (VDMACR.RS 1).0 Stop – VDMA stops when current (if any) VDMAoperations are complete. The halted bit in the VDMAStatus Register asserts to 1 when the VDMA engine ishalted. This bit gets cleared by AXI VDMA hardware whenan AXI4 Slave response error occurs. The CPU can alsochoose to clear this bit to stop VDMA operations.1 Run – Start VDMA operations. The halted bit in theVDMA Status Register deasserts to 0 when the VDMAengine begins operations.Note: On Run/Stop clear, in-progress stream transfersmight terminate early.LogiCORE IP AXI VDMA v6.0PG020 March 20, 2013www.xilinx.com17
Chapter 2: Product SpecificationMM2S VDMASR (MM2S VDMA Status Register – Offset 04h)This register provides the status for the Memory Map to Stream VDMA Channel.X-Ref Target - Figure 2-3DMAIntErrRSVD31RSVDRSVD16 15 14 13 12 11 10 924 23RSVDRSVDRSVDRSVDErr IrqRSVDFigure 2‐3:Table SOFEarlyErr10RSVDMM2S VDMASR RegisterMM2S VDMASR Register DetailsField NameDefault AccessDescriptionValueTypeWrite has no effect and read as default.lt.31-16Reserved0001hRONote: Bits [31:24] are used as delay counter15Reserved0ROAlways read as zero.R/WCInterrupt on Error.0 No error Interrupt.1 Error interrupt detected.If enabled (VDMACR.Err IrqEn 1), an interruptout is generated when error is detected.14Err Irq0and Bits [23:16] are used as frame counterwhen corresponding counters are enabled.Refer Appendix C to enable these features.Write has no effect and read as zero.Note: This bit captures the Delay Interrupt13Reserved0ROStatus. It is set to 1 when the delay interrupt isdetected. It is write 1 to clear. SeeAppendix C, Additional Design Information toenable Delay Interrupt feature.Write has no effect and read as zero.Note: This bit captures Frame Count12Reserved0RO11-8Reserved0ROLogiCORE IP AXI VDMA v6.0PG020 March 20, 2013Interrupt Status. It is set to 1 when framecount interrupt is detected. It is write 1 toclear. See Appendix C, Additional DesignInformation to enable Frame Count Interruptfeature.www.xilinx.comWriting has no effect and read as zero.18
Chapter 2: Product SpecificationTable 2‐10:Bits765MM2S VDMASR Register Details (Cont’d)Field NameSOFEarlyErrVDMADecErrVDMASlvErrDefault AccessDescriptionValueType000RO orR/WCStart of Frame Early Error0 No Start of Frame Error1 Start of Frame Early Error detectedThis error occurs if mm2s fsync is receivedbefore the completion of frame on streaminginterface.ROVDMA Decode Error. This error occurs if theaddress request is to an invalid address.0 No VDMA Decode Errors.1 VDMA Decode Error detected. VDMAchannel halts.ROVDMA Slave Error.0 No VDMA Slave Errors.1 VDMA Slave Error detected. VDMA Enginehalts.This error occurs if the slave read from theMemory Map interface issues a Slave Error.4VDMAIntErr0R/WCVDMA Internal Error.0 No VDMA Internal Errors.1 VDMA Internal Error detected. VDMAchannel halts.This error occurs during one of the followingconditions:HSIZE or VSIZE register were written zeros.Transferred frame size is lesser than vsize values.3-2Reserved0ROWriting to these bits has no effect, and they arealways read as zeros.1Reserved0ROWrite has no effect and read as zero.ROVDMA Channel Halted.Indicates the run/stop state of the VDMAchannel.0 VDMA channel running1 VDMA channel halted. This bit gets set whenVDMACR.RS 0. There can be a lag of timebetween when VDMACR.RS 0 and whenVDMASR.Halted 1.0HaltedLogiCORE IP AXI VDMA v6.0PG020 March 20, 20131www.xilinx.com19
Chapter 2: Product SpecificationMM2S REG INDEX (MM2S Register Index ‐ Offset 14h)This register is reserved if Frame Buffers selected in the Vivado Integrated DesignEnvironment (IDE) is less than 17 (writing has no effect, read returns 0).X-Ref Target - Figure 2-4 3FTFSWFE . 4@3&(@*/%&9Figure 2‐4:Table 2‐11:MM2S Register IndexMM2S Register Index (MM2S REG INDEX – Offset 0x14)BitsField Name31-1Default/AccessReset StateReserved0MM2S Reg IndexzeroesROAlways read as zeroR/WWhen Frame Buffers is greater than 160 Any write or read access between 0x5C to 0x98accesses the Start Address 1 to 16.1 Any write or read access between 0x5C to 0x98accesses the Start Address 17 to 32.PARK PTR REG (Park Pointer Register – Offset 28h)This register provides Park Pointer Registers for the Memory Map to Stream and Stream toMemory Map VDMA transfer Management.X-Ref Target - Figure 2-53129 28Rsvd21 2024 23WrFrmStoreRsvd16 15RdFrmStoreFigure 2‐5:LogiCORE IP AXI VDMA v6.0PG020 March 20, 201313 12Rsvd8WrFrmPtrRef75Rsvd410RdFrmPtrRefPARK PTR REG Registerwww.xilinx.com20
Chapter 2: Product SpecificationTable 2‐12:PARK PTR REG Register DetailsBitsField NameDefault AccessValueTypeDescription31-29Reserved0ROWriting to these bits has no effect, and they are always readas zeros.ROWrite Frame Store. Indicates current frame being operatedon by S2MM channel. During VDMA operations this valuecontinually updates as each frame is processed. Duringerror conditions, the value is updated with the currentframe being operated on when the error occurred. It willagain start tracking frames when all errors are cleared.ROWriting to these bits has no effect, and they are always readas zeros.RORead Frame Store. Indicates current frame being operatedon by MM2S channel. During VDMA operations this valuecontinually updates as each frame is processed. Duringerror conditions, the value is updated with the currentframe being operated on when the error occurred. It willagain start tracking frames when all errors are cleared.ROWriting to these bits has no effect, and they are always readas zeros.R/WWrite Frame Pointer Reference. When Parked(VDMACR.Circular Park 0), references the S2MM Frame topark on.ROWriting to these bits has no effect, and they are always readas zeros.R/WRead Frame Pointer Reference. When Parked(VDMACR.Circular Park 0) references the MM2S Frame topark 00VDMA VERSION (AXI VDMA Version Register – Offset 2Ch)This register provides the AXI VDMA Version.X-Ref Target - Figure 2-63128 27Major Version20 19Minor Version16 15RevisionFigure 2‐6:LogiCORE IP AXI VDMA v6.0PG020 March 20, 20130Xilinx InternalVDMA VERSION Registerwww.xilinx.com21
Chapter 2: Product SpecificationTable 2‐13:VDMA VERSION Register DetailsBitsField NameDefaultValueAccessTypeDescription31-28Major Version6hROSingle 4-bit hexadecimal value. v1 1h, v2 2h, v3 3h, andso on.27-20Minor Version00hROTwo separate 4-bit hexadecimal values. 00 00h, 01 01h,and so on.19-16Revision0hROReserved for Internal Use Only.15-0Xilinx InternalvariousROReserved for Internal Use Only. Integer value from 0 to9999.Stream to Memory Map Register DetailS2MM VDMACR (S2MM VDMA Control Register – Offset 30h)This register provides control for the Stream to Memory Map VDMA Channel.X-Ref Target - Figure 2-7R epeat En RSVD3116 15 14 13 12 11 10 9 824 23RSVDWrPntrNmbr(Mstr in Control)RSVDRSVD7 6GenlockSrcERR I
“Video IP: AXI Feature Adoption” section of the AXI Reference Guide (UG761). AXI4 Data Width The AXI VDMA core supports the primary AXI4 data bus width of 32, 64, 128, 256, 512, and 1024 bits. AXI4‐Stream Data Width The AXI VDMA core supports the primary AXI4-S tre
AXI4 Memory Map and AXI4-Lite interfaces Supports connection to AXI3 Protocol Cores LogiCORE IP ChipScope AXI Monitor (v3.02.a) DS810 January 18, 2012 Product Specification LogiCORE IP Facts Table Core Specifics Supported Device Family (1) Virtex -7, Kintex -7(6), Virtex-6(3), Spartan -6(4) Supported User Interfaces AXI4, AXI4-Lite .
AXI Reference Guide www.xilinx.com 5 UG761 (v13.1) March 7, 2011 Chapter 1 Introducing AXI for Xilinx System Development Introduction Xilinx has adopted the Advanced eXtensible Interface (AXI) protocol for Intellectual Property (IP) cores beginning with the Sparta
AXI Bridge for PCI Express v2.5 www.xilinx.com 8 PG055 November 19, 2014 Chapter 2 Product Specification Figure 2-1 shows the architecture of the AXI Bridge for PCI Express core. The Register block contains registers used in the AXI Bridge for PCI Express core for dynamically mapping the AXI4 memory mapped (MM) address range provided using the
memory-mapped master devices to one or more memory-mapped slave devices. Note: The AXI SmartConnect core is intended for memory-mapped transfers only. For AXI4-Stream transfers, see the LogiCORE IP AXI4-Stream InterConnect Product Guide (PG085) [Ref 1]. The AXI SmartConnect is a Hierarchical IP block that is added to a Vivado IP integrator block
The Xilinx Video Direct Memory Access (Video DMA) LogiCORE IP allows video cores to access external memory via the Video Frame Buffer Controller (VFBC) port on the Multi-Port Memory Controller (MPMC). The Video DMA is highly programmable through registers coupled with a wide range of interrupts, allowing for easy control of the various .
The AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its optional scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor-based systems. Initialization, status, and management registers are
AXI EMC v3.0 www.xilinx.com 7 PG100 April 5, 2017 Chapter 1: Overview AXI4-Lite Interface AXI EMC core provides AXI4-Lite slave interface to allow access to Internal Control and Status registers of the c
additif a en fait des effets secondaires nocifs pour notre santé. De plus, ce n’est pas parce qu’un additif est d’origine naturelle qu’il est forcément sans danger. Car si l’on prend l’exemple d’un champignon ou d’une plante toxique pour l’homme, bien qu’ils soient naturels, ils ne sont pas sans effets secondaires.
