Circuit Sizing W/ Corner Models Challenges & Applications
Improve Design Performance & YieldCircuit Sizing w/ Corner ModelsChallenges & ApplicationsMatthias SylvesterApril 11th, 2013 Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Improve Design Performance & YieldAgenda IntroductionCorners & Process Monte CarloApplication: Performance TuningApplication: Customer Cases Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Improve Design Performance & YieldMunEDA Corporate Overview EDA Software Vendor – Design Tool Suite WiCkeDTMfor Porting, Analysis, Modeling & Sizing of nanometer IC designs Founded in 2001 – Headquarters in Munich Germany Worldwide Sales & Support Offices in USA, Korea, Taiwan, Japan,UK, Ireland, Scandinavia, South America Worldwide Customer Base of Semiconductor IDMs,Fabless Design Houses & Foundries Copyright by MunEDA GmbH - All rights reserved - www.muneda.com3
Improve Design Performance & YieldMunEDA WiCkeDTM Circuit Design & Sizing Environment Copyright by MunEDA GmbH - All rights reserved - www.muneda.com4
Improve Design Performance & YieldChallenges of advanced node design Circuit sizing: Designers have to carefully set circuitparameters like W, L, R, C, – to meet performance targets– to reduce sensitivities vs. Vdd, temperature, process, LDE, mismatch Creating a robust design becomesmore challenging in advanced nodes––––––higher sensitivity vs. supply voltagehigher sensitivity vs. temperaturereduced voltage headroomwider corner spreadincreased local variationlayout dependent effects (LDE)SpeedFFTTSS28nm40nm65nmTechnologySee Beacham et al. (Synopsys Inc.): “Mixed-Signal IP DesignChallenges in 28 nm and Beyond”. www.design-reuse.com Copyright by MunEDA GmbH - All rights reserved - www.muneda.com5
Improve Design Performance & YieldProcess corner support Process variation is usually modeled in two ways1. Process corners (ss/ff/sf/fs/ )2. Process Monte Carlovth N(µvth, σ²vth)tox N(µtox, σ²tox) Most foundry PDKs contain both models.Local variation (mismatch) is always modeled by MC statistics. What‘s the advantages / disadvantages of using corners orprocess MC? Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Improve Design Performance & YieldCorners & Process Monte Carlo Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Improve Design Performance & YieldComparison: Corners vs Process Monte CarloCornersProcess MCSimulation effort for pure CMOSlowmediumSimulation effort for large # of device types(MOS/BJT/res/cap/ ) per designhighmediumCheck timing for full-custom digital designsyesnoCorrect device correlationnoyesCheck operating conditions of analogdesignsyesyesCheck analog performance variabilitynoyesEstimate yieldnoyesProcess parameter sensitivitiesnoyes Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Improve Design Performance & YieldAnalog performance variability Compare ss/ff/fs/sf corner results with global MC for a popular 65nm process that’sused by analog designers worldwide:Red line connects corners (ff,ss,fs,sf).Green dots: global MC samplesIsat: realistic cornerresults, fits very wellCgs: analog feature,error 80%.Gain: analog feature,error 30%. Good estimate for Isat, Vth; difference at analog small signal parameters. Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Improve Design Performance & YieldTools of WiCkeD – Analysis & Verfication – WCO Worst-Case OperationCircuitAnalysis &Verification Find worst-case operating condition & corner Includes structural constraints Can handle non-linear dependency ( worst-case not inthe corner) Copyright by MunEDA GmbH - All rights reserved - www.muneda.com10
Improve Design Performance & YieldTools of WiCkeD- Analysis & Verification — CRN Corner Run AnalysisCircuitAnalysis &Verification Check all corners, show corner overview and summary Distributed simulation in a network of hosts Copyright by MunEDA GmbH - All rights reserved - www.muneda.com11
Improve Design Performance & YieldFinding worst-case conditionsTemperatureIf you simulated all but onecorner, is there a reliableway to guess its value?A(Vdd,T)125 C80dB81dBUnfortunately, no.81.5dB83dB–20dB?-40 C1.65V2.0 VVddNo matter what kind of model you use and nomatter how many parameters there are,extrapolating models over a large distance isunreliable.WiCkeD uses methods to build models over operating parameters to guesswhere’s the worst-case condition before simulating it.This is very useful to speed up optimization inside the optimizer’s loop.But for verification, better don’t skip corners just because they are OK in a model. Copyright by MunEDA GmbH - All rights reserved - www.muneda.com12
Improve Design Performance & YieldWiCkeD WCO modelingTemperatureFor continuous operating parameters: Star Box DOE Quadratic model to detect non-linearities,resimulating estimated minima Checking corners125 C-40 C1.65V2.0 VVddDutyCycleFor larger # of operating parameters: Option to run only Star DOE, create quadraticmodel and re-simulateFor enumerated corners: Full run, no short-cuts1.65V2.0 VVdd Copyright by MunEDA GmbH - All rights reserved - www.muneda.com13
Improve Design Performance & YieldPVT corners and parameters (1)Statistical parametersoperating parametertemp., Vdd, Cload, process parametertox, vth, u0, PVT Cornersmismatch parametervth(m1), vth(m2), mismatch parametervth(m1), vth(m2), Most usual case: instead of operating parameters and processparameters, corners are defined. But there are alternatives Copyright by MunEDA GmbH - All rights reserved - www.muneda.com14
Improve Design Performance & YieldPVT corners and parameters (2)Statistical parametersoperating parametertemp., Vdd, Cload, process parametertox, vth, u0, mismatch parametervth(m1), vth(m2), operating parametertemp., Vdd, Cload, Process Cornersmismatch parametervth(m1), vth(m2), WCO can handle continuous operating parameter together withcorners Allows temperature sweeps at corners Copyright by MunEDA GmbH - All rights reserved - www.muneda.com15
Improve Design Performance & YieldPVT corners and parameters (3)Statistical parametersoperating parametertemp., Vdd, Cload, process parametertox, vth, u0, mismatch parametervth(m1), vth(m2), Operating Cornersprocess parametertox, vth, u0, mismatch parametervth(m1), vth(m2), MCA can vary process parameters also if there are corners defined Enables running process MC for selected corner conditions Copyright by MunEDA GmbH - All rights reserved - www.muneda.com16
Improve Design Performance & YieldPerformance Tuning Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Improve Design Performance & YieldPerformance Tuning Many circuits require precise tuning of fast transient signals, noise,transfer characteristics, Designers have to find good values for all transistors‘ W and L thatfulfill all specs considering– Operating conditions– Process variation (global Monte Carlo statistics, or corners)– Mismatch (on-chip variation) Designers re-size the circuit whenever––––specs get updatedmodel files get updatedmultiple versions are to be generated (low-leakage, high-speed, )IP is ported to a new process (IP reuse, design migration) Designers spend much time with iterative simulation-based sizing. Copyright by MunEDA GmbH - All rights reserved - www.muneda.com18
Improve Design Performance & YieldNumerical Sizing in Advanced Circuit DesignTopologydesignSizingby formulaSimulationLayout(sweeps, MC,corners, )NumericalSizing adjusting deviceparameters(W,L,R, ) basedon simulationresultsTraditional analog design method:Simulation is used as a verification toolonly, but not as a design tool.Good for small low-speed analog design.CircuitSizing &OptimizationParasiticExtractionDoneNumerical sizing:Modify device geometries iterativelybased on simulation results (aftertraditional initial design).Needed for high-speed design, RF,custom digital. Copyright by MunEDA GmbH - All rights reserved - www.muneda.com19
Improve Design Performance & YieldWhat makes sizing difficult? Manual sizing is easy, as long as– symbolic small-signal approximations are sufficiently accurate– there are no tough trade-offs between multiple hard specs– process variation and mismatch can be compensated by safety margins andstructural solutions (feedback, symmetry, trimming, )– there are only few design variables, best case with a 1:1 relationship to specs Reality is not as easy as an analog textbook example –––––Large impact of second order effects, parasitics, noise, Non-linear specs with no good symbolic estimateImpact of PVT variation and mismatch to be compensated by sizingTight specs, multiple trade-offsMany design variables, m:n dependency to specs Copyright by MunEDA GmbH - All rights reserved - www.muneda.com20
Improve Design Performance & YieldWhat makes sizing difficult? Trade-offs :The optimum of one spec violates another spec Copyright by MunEDA GmbH - All rights reserved - www.muneda.com21
Improve Design Performance & YieldWhat makes sizing difficult? Non-linear parameter dependency with mixed effectsThe optimum of one parameter depends on the value of other parameters Copyright by MunEDA GmbH - All rights reserved - www.muneda.com22
Improve Design Performance & YieldWhat makes sizing difficult?Different worst-cases regarding temperature / Vdd / load / falltime worst-case: 80 C, delay fall worst-case: 0 C Copyright by MunEDA GmbH - All rights reserved - www.muneda.com23
Improve Design Performance & YieldWhat makes sizing difficult? Sensitivities have to be minimized.For some specs, it’s not enough to shift the nominal value;you can reduce sensitivities, too. Copyright by MunEDA GmbH - All rights reserved - www.muneda.com24
Improve Design Performance & YieldWhat makes sizing difficult? Local variation (mismatch) has asignificant influence200% Scaling trend– Absolute Vth variation of theminimum device grows– Vth shrinks, Vdd shrinks fasterRelative impact of local variationσVT / (Vdd-Vth)growsσVT100%0.18u90n65n32n10Vdd1VthWe have to size the circuits forrobustness vs. local variationin addition to PVT corners0.10.010.11Lgate [um] Copyright by MunEDA GmbH - All rights reserved - www.muneda.com25
Improve Design Performance & YieldTypical WiCkeD Applications in I/O designs and Libraries Common tasks: sizing, statistical analysis, performance optimization,modeling, robustness optimization, reduce area, reduce powerconsumption, initial design (low voltage), Libraries, I/O Circuits: Transmitter, PCIe equalizer, LVDS drivers, level shifter, bandgap,voltage regulators, impedance control, short/overload detector, power-onreset, SerDes, Performance metrics: jitter, eye diagram opening, duty cycle, temperaturestability, voltage levels, delays, PSRR, stability, Copyright by MunEDA GmbH - All rights reserved - www.muneda.com26
Improve Design Performance & YieldSoftware: Data flowInputOutputSchematics Design Centering Yield & RobustnessOR- file 1 .cir file 2 .cir . file n .cir ModelingSized & OptimizedCircuit Schematic orNetlist(s)NetlistsSPICE Copyright by MunEDA GmbH - All rights reserved - www.muneda.com27
Improve Design Performance & YieldThree Optimization Steps1. Feasibility Optimization– Fulfills constraints on DC operating conditions (saturation, inversion, currentsymmetries, overdrive, )– Is optional (some circuits don’t have such constraints)– May include constraints on SOA (aging), becoming more important in 28nm2. Nominal Optimization– Optimizes performance (delays, eye diagram, jitter, power ) over PVTcorners– Keeps constraints on DC operating conditions fulfilled– Not considering local variation (mismatch), therefore “nominal” optimization3. Yield Optimization– Optimizes design yield (robustness) considering local variation (mismatch)– Should start from a design point after nominal optimization to save time Copyright by MunEDA GmbH - All rights reserved - www.muneda.com28
Improve Design Performance & YieldOptimization Steps (Vastly Simplified Flow Chart)Initial SizingRe-think topologyand ESNOYESYield goalfulfilled?NOYield OptimizationYield goalfulfilled?YESNOYESOptimized Sizing Copyright by MunEDA GmbH - All rights reserved - www.muneda.com29
Improve Design Performance & YieldSolution Searchall possibledesignsFeasibilityOptimizationall designs withconstraints fulfilledNominalOptimizationall designs withspecificationsfulfilled at TTYieldOptimizationall designs with highenough parametric yield Copyright by MunEDA GmbH - All rights reserved - www.muneda.com30
Improve Design Performance & YieldTools of WiCkeD – Sizing & Optimization— DNO & GNO Nominal Optimization CircuitSizing &OptimizationFast and efficient. Scales well also for larger circuits.Multiple parameters, goals, corners & test benches optimized simultaneouslyPre- and post-layoutBroad simulator support, scriptable. Copyright by MunEDA GmbH - All rights reserved - www.muneda.com31
Improve Design Performance & YieldTools of WiCkeD – Sizing & Optimization — Design Centering (Yield Optimization)CircuitSizing &OptimizationThe unique flagship:Automated Yield Optimization Improve robustness vs processvariation and mismatch Multiple performances simultaneously Based on worst-case distanceand sigma measures Copyright by MunEDA GmbH - All rights reserved - www.muneda.com32
Improve Design Performance & YieldCustomer Cases Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Improve Design Performance & YieldCustomer Example – Faraday – Batch-mode optimization of standard cellsSolution:Standard cell: Clock buffers MunEDA Nominal Optimization inBatch ModeTask: Balance slopesChallenge: many cell & process variants,multiple slews and output loads,frequent model updateComplete automation reduces design time significantly.Equal or better results than manual design.Results published by Faraday at MTF Anaheim 2008 Copyright by MunEDA GmbH - All rights reserved - www.muneda.com34
Improve Design Performance & YieldCustomer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization ToolsSTMicroelectronics - Optimization of High-Speed I/O circuits in 28nmSolution:28nm DDRx High-Speed I/O Use MunEDA Sensitivity Analysisand Corner OptimizationTask: Reduce jitter and duty cycleChallenge: Manual tuningtakes 2 weeksDesign Time reduced from 2 weeks to only 3 hoursCorner spread reduced by 50%Easy analysis of circuit sensitivitiesResults published by STMicroelectronics at MUGM 2011 Copyright by MunEDA GmbH - All rights reserved - www.muneda.com35
Improve Design Performance & YieldCustomer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization ToolsTOP Microprocessor Company - Using MunEDA tools to optimize AMS/RF IP in 65nmTOP Microprocessor Company - RF receiver path in advanced node– Task: reduce power consumption while keeping noise low– To see the noise vs power trade-off, the complete path has to be considered– Circuit size: 2000 MOS, 8000 parasitics.Simulation time: 40min. for a single run (dc pss pnoise)– Optimization complexity: 80 specs, 50 design parametersThree process corners temperature VddpowerBlock 1Block 2Block 3Block 4Noise matching between blocksResults: Power consumption significantlyreduced. Sizing task performed completelyautomatically. Designer attention time is reducedfrom 4 weeks to a few hours. Copyright by MunEDA GmbH - All rights reserved - www.muneda.com36
Improve Design Performance & YieldThank You37 Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Sizing by formula Topology design Numerical Sizing adjusting device parameters (W,L,R, ) based on simulation results Done Traditional analog design method: based Simulation is used as a verification tool only, but not as a design tool. Needed Good for small low-speed analog design. Numerical sizing: Modify device geometries iteratively
ch-1 sp, ch1) repeat to next corner; if the next corner is a corner unit (2dc, ch1, 2dc) in next ch-1 corner sp. If the next corner is a corner join, you will have to work double crochet decreases. When you encounter a corner join for the first border, you will work a decrease by: yo, insert hook into the ch-1 sp before the corner join,
2.4 Other types of control valves 40 2.5 Control valve selection summary 42 2.6 Summary 46 3 Valve Sizing for Liquid Flow 47 3.1 Principles of the full sizing equation 48 3.2 Formulae for sizing control valves for Liquids 51 3.3 Practical example of Cv sizing calculation 52 3.4 Summary 54 4 Valve Sizing for Gas and Vapor Flow 55
Battery Sizing Example 4. Sizing with Software 5. Battery Charger Sizing Saft Battery 2 Sizing. The Art and Science of Battery Sizing Saft Battery . 2-8 hr. battery backup normal Time (hh:mm:ss) Current (A) Paralleling Switchgear 8 120V to 600V (typical) DC bus 24, 48 or 125Vdc
SPECIFICATION DATA SHEET 74 Control Valve Data Sheet (Excel format) 75 CALCULATION SPREADSHEET Excel Format (British & SI unit) Sizing Spreadsheet for Liquid 75 Sizing Spreadsheet for Vapor 76 Example 1: Sizing a Control Valve in Liquid –Hydrocarbon 77 Example 2: Sizing a Control Valve in Liquid –Water 78
The challenge to building an FEA sizing model from a mesh of quadrilaterals and some triangles is how to develop user interfaces for easy setup of the sizing model and how to manage the inter-related data to generate the correct NASTRAN input file for sizing. The key ideas in this paper for automation of panel thickness sizing of aircraft
2008 (Ref. D), a sizing system and design were developed and optimized to accommodate the most individuals in the fewest sizes. The sizing system uses a three inch sizing interval for Chest Circumference in order to provide a better fit than the 4 inch interval currently used. For length, a two inch sizing interval for Torso Length is used.
circuit protection component which cars he a fusible link, a fuse, or a circuit breaker. Then the circuit goes to the circuit controller which can be a switch or a relay. From the circuit controller the circuit goes into the circuit load. The circuit load can be one light or many lights in parallel, an electric motor or a solenoid.
REGISTER OF LEGISLATION ISO 14001 Doc. Ref. Version Date Template Author Page ROL-SAMPLE-14001 1.0 24/08/2004 Mark Helm 2 of 10 Sovereign Certification Limited
