Section 4. IC Technology And Packaging Trends - Smithsonian Institution

IC Technology and Packaging Trends Driver Year of first DRAM shipment Minimum feature (µm) 1995 0.35 1998 0.25 2001 0.18 2004 0.13 2007 0.10 2010 0.07 Memory Bits/chip (DRAM/flash) Cost/bit @ volume (millicents) 64M 0.017 256M 0.007 1G 0.003 4G 0.001 16G 0.0005 64G 0.0002 4M 2M 1 7M 6M 0.5 13M 20M 0.2 25M 50M 0.1 50M 2100M 0.05 90M 300M 0.02 2M 0.3 4M 0.1 7M 0.05 12M 0.03 25M 0.02 40M 0.01 Number of Chip I/Os Chip to package (pads) high perf. 900 1350 2000 2600 3600 4800 L,A Number of package pins/balls Microprocessor/controller ASIC (high performance) Package cost (cents/pin) 512 750 1.4 512 1100 1.3 512 1700 1.1 512 2200 1.0 800 3000 0.9 1024 4000 0.8 A Chip frequency (MHz) On-chip clock, cost-performance On-chip clock, high-performance Chip-to-board speed, high performance 150 300 150 200 450 200 300 600 250 400 800 300 500 1000 375 625 1100 475 Chip size (mm2) DRAM Microprocessor ASIC 190 250 450 280 300 660 420 360 750 640 430 900 960 520 1100 1400 620 1400 Maximum number wiring levels (logic) On-chip 4–5 5 5–6 6 6–7 7–8 µP Defect density (d/cm2) 0.75 0.45 0.35 0.25 0.2 0.15 D Minimum mask count Cycle time days (theoretical) 18 9 20 10 20 10 22 11 22 11 24 12 L L Maximum substrate diameter (mm) Bulk or epitaxial or SOI† wafer 200 200 300 300 400 400 D Power supply voltage (V) Desktop Battery 3.3 2.5 1.5 0.9 1.2 0.9 0.9 0.9 µP A Maximum power High performance with heatsink (W) Logic without heatsink (W/cm2) Battery 80 5 2.5 100 7 2.5 120 10 3.0 140 10 3.5 160 10 4.0 180 10 4.5 µP A L 3.3 16–32 25 1.7 16–32 40 1.3 16–32 50 0.7 8–16 70 0.5 4–8 90 0.4 4 90 L L L Logic (High volume: Microprocessor) Logic transistors/cm2 (packed) Bits/cm2 (cache SRAM) Cost transistor @ volume (millicents) D L(µP) L(A) Logic (Low volume: ASIC) Transistors/cm2 (auto layout) Nonrecurring engineering cost/transistor (millicents) Design and test Volume tester cost/pin ( K) Number of test vectors (µP/M) % IC function with BIST/DFT# † silicon-on-insulator 1.8 2.5 1.8–2.5 0.9–1.8 µP L A ASIC D DRAM L Logic µP Microprocessor * built-in self test # design for testability Source: Solid State Technology/ICE, "Status 1996" 20286A Figure 4-13. The 15-Year SIA Roadmap INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-9

IC Technology and Packaging Trends Parameter NMOS PMOS 10Ωcm p-type (100) 10Ωcm p-type (100) Twin Well Twin Well 350nm LOCOS 350nm LOCOS B 40keV 7 x 1012 As 180keV 5 x 1012 Gate Oxide 3.9nm (800 C) 3.9nm (800 C) Gate Stack Poly-Si 160nm SiO2 50nm Poly-Si 160nm SiO2 50nm As 10keV 4 x 1013 BF2 5keV 1 x 1014 SiN 60nm SiN 60nm As 30keV 3.2 x 1015 BF2 20keV 5 x 1015 850 C, 5 minutes 850 C, 5 minutes Starting Material Well Isolation Channel Implant Shallow Junction Implant Spacer Deep Junction Implant Anneal Source: Fujitsu/IEDM/ICE, "Status 1996" 19214 45 100 80 0.25µm 60 0.20µm 40 Unloaded 51-stage CMOS inverter Delay Time (ps/gate) Delay (ps) Figure 4-14. Process Parameters of 0.1µm CMOS 0.15µm 20 0.10µm 40 Lg 0.15µm 35 30 Lg 0.1µm Lg 0.075µm 25 20 15 10 1.0 1.5 2.0 2.5 1.5 2.0 2.5 3.0 Supply Voltage (V) Supply Voltage (V) Unloaded gate delay as a function of power supply voltage and gate length CMOS inverter gate delay versus power supply voltage Source: AT&T/ICE, "Status 1996" 3.5 Source: Fujitsu/ICE, "Status 1996" Gate Delay/Stage (ps) 200 100 80 60 Leff (n/p) (0.25µm CMOS) 0.14/0.12µm 0.12/0.10µm 0.12/0.10µm (simulation) 40 20 300K 10 0.5 1.0 1.5 2.0 Supply Voltage (V) 2.5 Measured (points) and simulated (dashed) CMOS-inverter delay versus supply voltage Source: IBM/ICE, "Status 1996" 19215 Figure 4-15. IEDM 0.25µ CMOS Performance Results 4-10 INTEGRATED CIRCUIT ENGINEERING CORPORATION

IC Technology and Packaging Trends 350 315 280 245 1.0 0.9 0.8 0.7 210 Speed Doubles Every 2 Generations 0.5 175 0.4 140 105 0.3 3.3V 2.2V 1.5V 5V 0.2 (Low Power) 70 Unloaded Inverter Delay (ps) Gate Delay (Arbitrary Units) 0.6 3.3V Speed Doubles Every 4 Generations (High Speed) 2.2V 0.1 2µm 1µm 0.5µm 0.25µm 35 0.13µm Technology Generation Source: ISSCC94/UC Berkeley/ICE, "Status 1996" 19499 Figure 4-16. Low-Power Speed Lag Primary Feature Feature Driver Continued requirements for higher integration density Products DRAMs Pros and Cons Slowest Voltage versus Time evolution SRAMs Device Physics Not a driver for revolutionary device technology changes Integration density drives scaling Scaling drives device physics Not a good test bed for nondevice power reduction techniques Device physics limit operating voltage, resulting in lower power High Performance Portable Products High integration density circuits operating at maximum performance bump against package power constraint MPUs DSPs Basic cell performance may start to diminish; power limited performance not compensated by scaling ASICs Increased performance will require non-device and nonscaling solutions: systems circuits, . . . . Reduced power achieved by lower operating voltage or design modifications Full custom Battery life as key operator MCUs Fastest Voltage versus Time driver May compromise integration density DSPs Non-traditional technology driver Frequency Control Drives revolutionary device technologies: GaAs, modified CMOS, mixed technologies May not require peak performance (frequency, delays, MIPS,. . . .) Some specialized products RF/An./Dig Lacks industry infrastructure and volume support base Source: Motorola/ICE, "Status 1996" 20287 Figure 4-17. Voltage Reduction Drivers INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-11

IC Technology and Packaging Trends As the composition of most digital systems changes from TTL to CMOS, the use of the 5V power supply may no longer be an asset, but a liability. Since power consumption is proportional to the square of the supply voltage, lowering the voltage from 5V to 3.3V can reduce the power as much as 70 percent. This means less heat has to be removed from the package. CMOS is the current technology of choice in all but the fastest systems. CMOS can be designed to operate from very high voltage supplies down to the 0.7V found in watches. Each end of this range has its own problems. If the supply voltage were very high, the power consumption would be very high but the ICs would not be susceptible to noise voltage and incorrect states. At the other extreme, the opposite is true. As has been touched upon, CMOS’ primary attribute is the ability to operate at low-power and low-voltage levels. These characteristics have become especially important in the emerging 3.3V portable, laptop, notebook, etc., PC markets (Figure 4-18). With the continuing trend toward finer IC feature sizes and compact portable systems, the increased availability of low-voltage CMOS ICs helped pure 2.7V-3.3V systems proliferate beginning in the early 1990’s. It is estimated that most of the 2000 IC market will be served by 3.3V ICs (up from about 12 percent in 1995).* Power (W) at 5V Notebook Computer System Components Typical 5V Power (W) Power at 3.3V Logic (W) Expected 3.3V Power (W) Logic Other Functions CPU Plus Core Logic 2.20 0.00 2.20 0.95 0.95 System Memory 0.50 0.00 0.50 0.22 0.22 Display Controller Subsystem 1.50 0.00 1.50 0.65 0.65 LCD Panel Plus Backlight 0.30 3.20 3.50 0.13 3.33 Hard-Disk Drive* 0.20 0.30 0.50 0.09 0.39 Miscellaneous Circuits 0.50 0.00 0.50 0.21 0.21 DC/DC Conversion 0.00 1.70 1.70 0.00 1.20 Total System Power 10.40 6.95 *Hard-disk drive power estimates reflect a mix of active and idle time. Source: Cirrus Logic/Electronic Products/ICE, "Status 1996" 19217 Figure 4-18. 3.3V Logic Power Savings in a Typical Notebook Computer The demand for low-voltage ICs came on so fast that it caught most IC producers by surprise. Many companies initially tried to satisfy this surging demand by offering screened 5V parts that would also operate at lower voltages. However, this “derating” oftentimes caused problems in the system under certain operating conditions. Thus, almost all IC producers have aggressively introduced fully characterized devices that are specifically designed for low-voltage operation. * In 1995 about 10 percent of 4M DRAMs, 25 percent of 16M DRAMs, and 90 percent of the 64M DRAMs used a 3.3V power supply. 4-12 INTEGRATED CIRCUIT ENGINEERING CORPORATION

IC Technology and Packaging Trends In the transition period from 5V to low-voltage systems, system designers will be using both 5V and low-voltage ICs on the same printed circuit board (Figure 4-19). Targeting such systems, AT&T offers a standard cell library that allows the user to mix and match 5V and 3V cells on the same chip. Other companies that are helping bridge the 5V to low-voltage gap with “mixed-voltage” ICs include Oki, TI, Toshiba, Atmel, and NCR. 100 90 Percentage of Design Starts 80 70 5V 60 50 3V 40 30 20 5/3V 10 2.xV 0 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 Year Source: VLSI Technology/ICE, "Status 1996" 19179A Figure 4-19. Transition from 5V to 3V Systems ECL Inherently, ECL devices are very uniform, stable, and generate low noise. Also, ECL requires only a 1V swing in 3-4ns compared with a typical TTL chip that requires a 5V swing in the same timeframe. Even though the tradeoffs of ECL’s high speed versus CMOS’ low cost and low power are well known, there is a trend that is beginning to blur those distinctions — convergence. Many new high-end, high-performance systems are mixing ECL or TTL with CMOS to optimize the designs for both high speed and low cost (e.g., BiCMOS). INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-13

IC Technology and Packaging Trends The ECL IC market was about 965 million in 1995 and is made up of ASIC, standard and special purpose logic, and memory devices (Figure 4-20). ASICs held 55 percent of the total ECL market in 1995 and that is expected to decrease to 48 percent in 2000. Logic devices held 29 percent of the ECL market in 1995 with 41 percent forecast for 2000. As is shown in Figure 4-20, the 2000 ECL IC market is forecast to be about half of what it was in 1995. Product 1991 ( M) 1991 percent of total 1994 ( M) 1994 percent of total 1995 (EST) ( M) 1995 percent of total 2000 (FCST) ( M) 2000 percent of total Memory 305 19 150 17 150 16 55 11 Total Logic* 280 18 275 32 285 29 195 41 ASIC 965 63 435 51 530 55 230 48 Total 1,550 100 860 100 965 100 480 100 *Includes General and Special Purpose Logic. Source: ICE, "Status 1996" 18110F Figure 4-20. ECL IC Market Forecast One of the reasons for the forecasted steep decline in the ECL market is the use of GaAs, BiCMOS, and even CMOS technologies in what were the bastions of ECL ICs—mainframes and supercomputers. For example, in Fujitsu’s minisupercomputers (VPP300 and VX), Fujitsu is using only CMOS ICs. These minisupercomputers are air-cooled and use vector parallel processing to achieve up to 35.2Gflops performance. Moreover, in mid-1993 Fujitsu announced it was suspending future development of ECL gate arrays. A Fujitsu spokesman was quoted as saying that ECL designs are disappearing very rapidly in the marketplace. The movement to using other technologies besides ECL for high-speed systems is especially devastating to the large military ECL IC market. The lackluster military IC market coupled with the increasing use of CMOS, GaAs, and BiCMOS ICs will heavily contribute to the declining ECL IC industry in the mid-to-late 1990’s. It now appears unlikely that future improvements in ECL technology will come from the purely merchant IC vendors. This is due in some part to the relatively small ECL IC market (less than one percent of the total 1995 merchant IC market) and the low volume of research money being spent on ECL technology by the open-market vendors. The major ECL IC manufacturers are shown in Figure 4-21. These producers accounted for about 98 percent of the merchant ECL IC market in 1995. The Japanese companies have traditionally had the largest ECL IC marketshare primarily because of their emphasis on mainframe computers. It is interesting to note that at the 1995 ISSCC conference there was only one paper (given on “low-power” ECL by Toshiba) delivered (out of 123 total) 4-14 INTEGRATED CIRCUIT ENGINEERING CORPORATION

IC Technology and Packaging Trends that dealt with strictly ECL technology. Typically, if ECL technology was described in a paper it was usually coupled with CMOS circuitry in a BiCMOS process. As has been discussed, the trend of replacing ECL circuitry in most new systems with CMOS, BiCMOS, and GaAs technologies is well on its way. 1995 Sales ( M, EST) Marketshare (Percent) Major Emphasis Fujitsu 270 28 ASICs, SRAMs Motorola 225 23 ASICs, Logic Hitachi 185 19 ASICs, SRAMs NEC ASICs, SRAMs Company 140 15 AMCC 40 4 ASICs Synergy 30 3 SRAMs, Logic Siemens 25 3 ASICs GEC Plessey 20 2 Logic National 10 1 ASICs 20 2 — 965 100 — Others Total Source: ICE, "Status 1996" 17130H Figure 4-21. 1995 Major ECL IC Suppliers BiCMOS Because BiCMOS offers advantages over both bipolar digital and CMOS, it will eventually replace a small portion of the high-end market held by pure ECL and CMOS ICs. Some BiCMOS devices now produced include: MPUs (e.g., the Pentium), smart-power ICs, bus drivers, analog-to-digital converters, track/hold amplifiers, disk-drive controllers, memory controllers, SRAMs, PLDs, gate arrays, and standard cells. BiCMOS technology has been considered a high-speed replacement for pure CMOS because it offers a performance edge by implementing both CMOS and bipolar transistors on the same chip. Through the selective use of CMOS and bipolar circuitry, high-performance paths can be created with ECL (bipolar) while lower-performance, high-density paths can be created with CMOS gates. BiCMOS architecture that consists of a small percentage of bipolar transistors is called CMOSbased. For this architecture, non-critical paths (the majority of the chip) consist of CMOS gates, while bipolar transistors are used mainly for driving long metal lines and as output buffers (critical paths). This is the most common type of BiCMOS technology. ECL-based BiCMOS architectures consist of predominantly ECL technology with CMOS transistors available for the implementation of large storage elements. The resulting IC offers excellent performance and density with a high level of programmability. INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-15

IC Technology and Packaging Trends Figure 4-22 provides a list of advantages BiCMOS technology offers over bipolar digital and CMOS technologies. The main disadvantage of BiCMOS is the cost penalty created by the complicated process of building both bipolar and MOS transistors into a single device.* It is because of this increased complexity that Intel has stated it intends to move the Pentium MPU from a 20mask BiCMOS process to a 16-mask pure CMOS technology. DISADVANTAGES ADVANTAGES High drive capability with large loads Designers lack experience and awareness –Ability to optimize critical path Design tools and macro library are needed –Improved skew Cost penalty High input impedance Process complexity Improved performance by a factor of 2 or 3 Difficult to achieve performance advantage using low-voltage sub-0.5 µ processes High CMOS-equivalent density Low power dissipation Mixed ECL, TTL, and CMOS interfaces Mixed analog-digital capability Improved noise margin and noise immunity Broad product base Ease of optimal product design Worthy replacement for TTL gate arrays Extends CMOS process lifetime Source: National Semiconductor/ICE, "Status 1996" 17839A Figure 4-22. BiCMOS Pros and Cons Since many of the current BiCMOS processes lose their performance advantage when using less than a 5.0V power supply, the BiCMOS manufacturers are faced with a dilemma as power supply voltages for high-density, sub-0.5µm devices move to 3.3V. Toshiba’s 0.5µm 500K-gate array addresses this problem with an innovative cell and circuit design called BipnMOS. Although the device operates at 3.3V, the bipolar circuitry is not inhibited and the BipnMOS process offers a significant performance advantage over a pure CMOS array. Because of the decreased performance in many current sub-5V BiCMOS technologies, the future of BiCMOS in the systems of the late-1990’s depends on the ability to economically produce specialized BiCMOS processes. Toshiba’s BipnMOS process described above is one example of a specialized complementary BiCMOS process. Motorola also has specialized BiCMOS processes that target ASIC, very high-speed, and low-voltage applications. The supply voltage sub-0.5µm BiCMOS triangle will especially challenge the BiCMOS producers in the mid- to late-1990’s. * In 3Q95 NEC introduced its QB-8 0.35µm BiCMOS ASIC technology. This process eliminates the typically used epitaxial layer for the bipolar devices in an attempt to “simplify” the inherently complex BiCMOS technology. 4-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION

IC Technology and Packaging Trends At the 1995 ISSCC, AT&T discussed its BiCMOS technology targeting high-performance analog applications (e.g., communications systems) in three papers (Figure 4-23). As shown in Figure 424, besides the Pentium-dominated microcomponent area, the analog segment is a strong market for BiCMOS ICs. AT&T – BiCMOS optical preamplifier AT&T – BiCMOS sample-and-hold amplifier Intel – 0.6µ BiCMOS processor with dynamic execution AT&T – BiCMOS frequency synthesizer IBM – SCI link in 0.8µ BiCMOS Source: ICE, "Status 1996" 20292 Figure 4-23. Sampling of 1995 ISSCC BiCMOS Papers Standard Logic 2% Gate Arrays 4% Standard Cell 2% Other 1% SRAMs 5% Analog 11% Microcomponents 75% 1995 10,700M Microcomponents 6% Other 3% Standard Cell 9% Standard Logic 10% 2000 8,425M Gate Arrays 12% Source: ICE, "Status 1996" Analog 37% SRAMs 23% 13643N Figure 4-24. Worldwide BiCMOS Market Forecast BiCMOS has also become popular for very high-speed SRAMs (Figure 4-25). The access times of some BiCMOS SRAMs are half those of most CMOS SRAMs of the same density, and ECL SRAMs can’t match BiCMOS densities. At the leading edge, NEC introduced a 3ns access time BiCMOS 1M SRAM in 1995. As shown in Figure 4-26, the BiCMOS market was led by microcomponent (i.e., Pentium) products in 1995. The total BiCMOS IC market is forecast to decline at a 5 percent CAGR from 19952000, and only represent three percent of the total IC market in 2000. This decline is due to the expectation that Intel will move its advanced MPU products from BiCMOS to CMOS i

IC technology, non-CMOS processes have become a luxury that most IC producers cannot afford. IC Technology and Packaging Trends INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-3 Introduction Growth Maturity Saturation Decline Obsolete Source: ICE, "Status 1996" 16809G ECL S/LS TTL HMOS NMOS TTL PMOS BIPOLAR ANALOG CMOS GaAs BiCMOS Diamond SiGe .