The MIPS Instruction Set Architecture - Duke University
The MIPS Instruction Set Architecture Computer Science 104 Lectures 7 8
Admin Homework Homework 1 due tonight Homework 2 available tonight Reading: Finish up Chapter 2 Appendix B: reference on MIPS Skim: B.7, Fig B.10.2, Insn listing Midterm 1 Wed Feb 15 (just over a week) Material: Lecture through Wed Feb 8 (rec Fri Feb 10) Homework 1 / Homework 2 Reading Chapters 1, 2. Appendix B Can bring one page of notes Andrew Hilton / Alvin R. Lebeck CPS 104 2
Last time What did we talk about last time? Andrew Hilton / Alvin R. Lebeck CPS 104 3
Last time What did we talk about last time? Instruction Set Architecture (ISA) Contract between HW and SW RISC/CISC Accumulator, Stack, 2-address, 3-address Registers Instructions encoded as numbers MIPS Andrew Hilton / Alvin R. Lebeck CPS 104 4
MIPS: A "Typical" RISC 32-bit fixed format instruction (3 formats) 32 general purpose (R0 contains zero) 3-address, reg-reg arithmetic instruction Single address mode for load/store: base displacement no indirection See Also: SPARC, MC88100, AMD2900, i960, i860 PARisc, POWERPC, DEC Alpha, Clipper, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3 Andrew Hilton / Alvin R. Lebeck CPS 104 5
MIPS Assembly Diving into MIPS Specific example of an ISA (now) Do some assembly programming (now) Concrete reference point for hw discussion (later) Andrew Hilton / Alvin R. Lebeck CPS 104 6
But I don’t have a MIPS computer? We’ll be using SPIM (on linux.cs) Command line version: spim Graphical version: xspim Edit in emacs, run in SPIM Andrew Hilton / Alvin R. Lebeck CPS 104 7
Assembly Assembly programming: 1 (sometimes two) machine instructions at a time Still in “human readable form” add r1, r2, r3 Much “lower level” than any other programming Limited number of registers vs unlimited variables Flat scope (who can remind us what scope is? Hint: not mouthwash) Andrew Hilton / Alvin R. Lebeck CPS 104 8
Assembly too high level for machine Human readable is not (easily) machine executable add r1, r2, r3 Instructions are numbers too! Bit fields (like FP numbers) Instruction Format establishes a mapping from “instruction” to binary values which bit positions correspond to which parts of the instruction (operation, operands, etc.) Assembler does this translation Humans don’t typically need to write raw bits Andrew Hilton / Alvin R. Lebeck CPS 104 9
What Must be Specified? Instruction “opcode” What should this operation do? (add, subtract, ) Location of operands and result Registers (which ones?) Memory (what address?) Immediates (what value?) Data type and Size Usually included in opcode What instruction comes next? Sequentially next instruction, or jump elsewhere Andrew Hilton / Alvin R. Lebeck CPS 104 10
Example: MIPS Register-Register 31 26 25 Op 21 20 Rs1 16 15 Rs2 11 10 6 5 Rd 0 Opx Register-Immediate 31 26 25 Op 21 20 Rs1 16 15 0 immediate Rd Branch 31 26 25 Op Rs1 21 20 16 15 0 immediate Rs2/Opx Jump / Call 31 26 25 Op Andrew Hilton / Alvin R. Lebeck 0 target CPS 104 11
Stored Program Computer 2n-1 Instructions: a fixed set of built-in operations Stack Instructions and data are stored in memory Allows general purpose computation! Fetch-Execute Cycle Heap while (!done) fetch instruction execute instruction This is done by the hardware for speed This is what the SPIM Simulator does Andrew Hilton / Alvin R. Lebeck CPS 104 Data Text 0 Reserved 12
How are Instructions Executed? Instruction Fetch Instruction Fetch: Read instruction bits from memory Instruction Decode Operand Fetch Execute Result Store Next Instruction Andrew Hilton / Alvin R. Lebeck CPS 104 13
How are Instructions Executed? Instruction Fetch Instruction Decode Instruction Fetch: Read instruction bits from memory Decode: Figure out what those bits mean Operand Fetch Execute Result Store Next Instruction Andrew Hilton / Alvin R. Lebeck CPS 104 14
How are Instructions Executed? Instruction Fetch Instruction Decode Operand Fetch Instruction Fetch: Read instruction bits from memory Decode: Figure out what those bits mean Operand Fetch: Read registers mem to get sources Execute Result Store Next Instruction Andrew Hilton / Alvin R. Lebeck CPS 104 15
How are Instructions Executed? Instruction Fetch Instruction Decode Operand Fetch Execute Instruction Fetch: Read instruction bits from memory Decode: Figure out what those bits mean Operand Fetch: Read registers mem to get sources Execute: Do the actual operation (e.g., add the #s) Result Store Next Instruction Andrew Hilton / Alvin R. Lebeck CPS 104 16
How are Instructions Executed? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Instruction Fetch: Read instruction bits from memory Decode: Figure out what those bits mean Operand Fetch: Read registers mem to get sources Execute: Do the actual operation (e.g., add the #s) Result Store: Write result to register or memory Next Instruction Andrew Hilton / Alvin R. Lebeck CPS 104 17
How are Instructions Executed? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Andrew Hilton / Alvin R. Lebeck Instruction Fetch: Read instruction bits from memory Decode: Figure out what those bits mean Operand Fetch: Read registers mem to get sources Execute: Do the actual operation (e.g., add the #s) Result Store: Write result to register or memory Next Instruction: Figure out mem addr of next insn, repeat CPS 104 18
More Details on Execution? Previous slides high level overview More details: How hardware works Everything after Midterm 1 Now, diving into assembly programming/MIPS Andrew Hilton / Alvin R. Lebeck CPS 104 19
Programming How do you write an assembly program? How do you write a program (in general)? Andrew Hilton / Alvin R. Lebeck CPS 104 20
How to Write a Program How I teach programming: 1. Work an example yourself 2. 3. 4. 5. Write down what you did Generalize steps from 2 Test generalized steps on different example Translate generalized steps to code Andrew Hilton / Alvin R. Lebeck CPS 104 21
How to Write a Program How I teach programming: 1. Work an example yourself 2. 3. 4. 5. Write down what you did Generalize steps from 2 Test generalized steps on different example Translate generalized steps to code Develop Algorithm In (Familiar) Higher Level Language Then translate to lower level language Andrew Hilton / Alvin R. Lebeck CPS 104 22
Why do I bring this up? Very Hard: Correctly Working Assembly Problem Easier: Problem Andrew Hilton / Alvin R. Lebeck C Implementation Algorithm CPS 104 Correctly Working Assembly 23
Our focus We will focus on the C assembly step Assume you know how to devise an algorithm for a problem (Intro programming classes) And have been learning how to implement algorithm in C (Last few weeks, hwk1) Problem Andrew Hilton / Alvin R. Lebeck C Implementation Algorithm CPS 104 Correctly Working Assembly 24
Simplest Operations We Might Want? What is the simplest computation we might do? Andrew Hilton / Alvin R. Lebeck CPS 104 25
Simplest Operations We Might Want? What is the simplest computation we might do? Add two numbers: x a b; Andrew Hilton / Alvin R. Lebeck CPS 104 26
Simplest Operations We Might Want? What is the simplest computation we might do? Add two numbers: x a b; add r1, r2, r3 “Add r2 r3, and store it in r1” Note: when writing assembly, basically pick reg for a, reg for b, reg for x Not enough regs for all variables? We’ll talk about that later Andrew Hilton / Alvin R. Lebeck CPS 104 27
MIPS Integer Registers Recall: registers Fast In CPU Directly compute on them 31 x 32-bit GPRs (R0 0) Also FP registers A few special purpose regs too PC Address of next insn Andrew Hilton / Alvin R. Lebeck CPS 104 28
Executing Add Address Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Instruction 1000 add r8, r4, r6 1004 add r5, r8, r7 1008 add r6, r6, r6 100C 1010 PC tells us where to execute next Andrew Hilton / Alvin R. Lebeck CPS 104 Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 ABAB ABAB 0000 0001 0000 0002 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 29
Executing Add Address Instruction 1000 add r8, r4, r6 1004 add r5, r8, r7 1008 add r6, r6, r6 100C 1010 Add reads its source registers, and uses their values directly (“register direct”) 9999 9999 0000 0001 9999 999A Andrew Hilton / Alvin R. Lebeck CPS 104 Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 ABAB ABAB 0000 0001 0000 0002 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 30
Executing Add Address Instruction 1000 add r8, r4, r6 1004 add r5, r8, r7 1008 add r6, r6, r6 100C 1010 Add writes its result to its destination register Andrew Hilton / Alvin R. Lebeck CPS 104 Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 ABAB ABAB 0000 0001 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 31
Executing Add Address Instruction 1000 add r8, r4, r6 1004 add r5, r8, r7 1008 add r6, r6, r6 100C 1010 And goes to the sequentially next instruction (PC PC 4) Andrew Hilton / Alvin R. Lebeck CPS 104 Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 ABAB ABAB 0000 0001 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1004 32
Executing Add Address Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Instruction 1000 add r8, r4, r6 1004 add r5, r8, r7 1008 add r6, r6, r6 100C 1010 You all do the next instruction! Andrew Hilton / Alvin R. Lebeck CPS 104 Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 ABAB ABAB 0000 0001 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1004 33
Executing Add Address Instruction 1000 add r8, r4, r6 1004 add r5, r8, r7 1008 add r6, r6, r6 100C 1010 We set r5 equal to r8 (9999 999A) r7 (2) 9999 999C and PC PC 4 Andrew Hilton / Alvin R. Lebeck CPS 104 Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 9999 999C 0000 0001 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1008 34
Executing Add Address Instruction 1000 add r8, r4, r6 1004 add r5, r8, r7 1008 add r6, r6, r6 100C 1010 Its perfectly fine to have r6 as a src and a dst This is just like x x x; in C, Java, etc: 1 1 2 Andrew Hilton / Alvin R. Lebeck CPS 104 Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 9999 999C 0000 0001 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1008 35
Executing Add Address Instruction 1000 add r8, r4, r6 1004 add r5, r8, r7 1008 add r6, r6, r6 100C 1010 Its perfectly fine to have r6 as a src and a dst This is just like x x x; in C, Java, etc: 1 1 2 Andrew Hilton / Alvin R. Lebeck CPS 104 Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 9999 999C 0000 0002 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 100C 36
MIPS Instruction Formats R-type: Register-Register 31 26 25 Op 21 20 Rs 16 15 Rt 11 10 6 5 shamt Rd 0 func I-type: Register-Immediate 31 26 25 Op 21 20 Rs 16 15 0 immediate Rt J-type: Jump / Call 31 26 25 0 target Op Terminology Op opcode Rs, Rt, Rd register specifier Andrew Hilton / Alvin R. Lebeck CPS 104 37
R Type: OP rd, rs, rt 31 26 25 Op 21 20 Rs op rs rt rd shmt func 16 15 Rt 11 10 Rd 6 5 shmt 0 func a 6-bit operation code. a 5-bit source register. a 5-bit target (source) register. a 5-bit destination register. a 5-bit shift amount. a 6-bit function field. Example: add 1, 2, 3 op 000000 rs rt rd shmt 00010 00011 00001 00000 Andrew Hilton / Alvin R. Lebeck CPS 104 func 100000 38
Executing Add Address Instruction Insn Val 1000 add r8, r4, r6 0086 4020 1004 add r5, r8, r7 0107 2820 1008 add r6, r6, r6 00C6 3020 100C 1010 Andrew Hilton / Alvin R. Lebeck CPS 104 Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 0000 0000 1234 5678 C001 D00D 1BAD F00D 9999 9999 9999 999C 0000 0002 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 100C 39
Xspim: Shows you similar state Register Values Insn Memory Andrew Hilton / Alvin R. Lebeck CPS 104 40
Other Similar Instructions sub rDest, rSrc1, rSrc2 mul rDest, rSrc1, rSrc2 div and or xor rDest, rDest, rDest, rDest, rSrc1, rSrc1, rSrc1, rSrc1, rSrc2 rSrc2 rSrc2 rSrc2 (pseudo-insn) (pseudo-insn) End of Appendix B: listing of all instructions Andrew Hilton / Alvin R. Lebeck CPS 104 41
Pseudo Instructions Some “instructions” are pseudo-instructions Actually assemble into 2 instructions: mul r1, r2, r3 is really mul r2, r3 mflo r1 mul takes two srcs, writes special regs lo and hi mflo moves from lo into dst reg Andrew Hilton / Alvin R. Lebeck CPS 104 42
What if I want to add a constant? Suppose I need to do x x 1 Idea one: Put 1 in a register, use add Problem: How to put 1 in a register? Idea two: Have instruction that adds immediate Note: also solves problem in idea one Andrew Hilton / Alvin R. Lebeck CPS 104 43
I-Type op rt, rs, immediate 31 26 25 Op 21 20 Rs 16 15 0 Rt Immediate Immediate: 16 bit value Operand Addressing: Register Direct and Immediate Add Immediate Example addi 1, 2, 100 op 001000 rs rt 00010 00001 Andrew Hilton / Alvin R. Lebeck immediate 0000 0000 0110 0100 CPS 104 44
Using addi to put a const in register Can use addi to put a constant into a register: x 42; Can be done with addi r7, r0, 42 Because r0 is always 0. Common enough it has its own pseudo-insn: li r7, 42 Stands for load immediate, works for 16-bit immediate Andrew Hilton / Alvin R. Lebeck CPS 104 45
Many insns have Immediate Forms Add is not the only one with an immediate form andi, ori, xori,sll,sr,sra, No subi Why not? No muli or divi Though some ISAs have them Andrew Hilton / Alvin R. Lebeck CPS 104 46
Assembly programming something “useful” Consider the following C fragment: int int a int tempF 87; a tempF – 32; a * 5; tempC a / 9; Lets write assembly for it Andrew Hilton / Alvin R. Lebeck CPS 104 47
Assembly programming something “useful” Consider the following C fragment: int int a int tempF 87; a tempF – 32; a * 5; tempC a / 9; Lets write assembly for it First, need registers for our variables: tempF r3 a r4 tempC r5 Now, give it a try (use r6, r7, as temps if you need) Andrew Hilton / Alvin R. Lebeck CPS 104 48
Assembly programming something “useful” Consider the following C fragment: int int a int tempF 87; a tempF – 32; a * 5; tempC a / 9; Lets write assembly for it li addi li mul r3, r4, r6, r4, 87 r3, -32 5 r4, r6 li r6, 9 div r5, r4, r6 First, need registers for our variables: tempF r3 a r4 tempC r5 Now, give it a try (use r6, r7, as temps if you need) Andrew Hilton / Alvin R. Lebeck CPS 104 49
Accessing Memory MIPS is a “load-store” ISA Who can remind us what that means? Andrew Hilton / Alvin R. Lebeck CPS 104 50
Accessing Memory MIPS is a “load-store” ISA Who can remind us what that means? Only load and store insns access memory (and that is all those isns do) Contrast to x86, which allows add reg (memory location) reg Or even add (memory location) (memory location) reg Andrew Hilton / Alvin R. Lebeck CPS 104 51
I-Type op rt, rs, immediate 31 26 25 Op 21 20 Rs 16 15 0 Rt Immediate Memory Register Base index Register Load Word Example lw 1, 100( 2) # 1 Mem[ 2 100] op 100011 rs rt 00010 00001 Andrew Hilton / Alvin R. Lebeck immediate 0000 0000 0110 0100 CPS 104 52
I-Type op rt, rs, immediate 31 26 25 Op 21 20 Rs 16 15 0 Rt Immediate Memory Register Base index Register Store Word Example sw 1, 100( 2) # Mem[ 2 100] 1 op 100011 rs rt 00010 00001 Andrew Hilton / Alvin R. Lebeck immediate 0000 0000 0110 0100 CPS 104 53
Data sizes / types Loads and Stores come in multiple sizes Reflect different data types The w in lw/sw stands for “word” ( 32 bits) Can also load bytes (8 bits), half words (16 bits) Smaller sizes have signed/unsigned forms See Appendix B for all variants Andrew Hilton / Alvin R. Lebeck CPS 104 54
C and assembly: loads/stores int x int * p int ** q # in r1 # in r2 # in r3 x *p; **q x; p *q; p[4] x; Andrew Hilton / Alvin R. Lebeck CPS 104 55
C and assembly: loads/stores int x int * p int ** q # in r1 # in r2 # in r3 x *p; **q x; lw r1, 0( r2) p *q; p[4] x; Andrew Hilton / Alvin R. Lebeck CPS 104 56
C and assembly: loads/stores int x int * p int ** q # in r1 # in r2 # in r3 x *p; **q x; lw r1, 0( r2) lw r4, 0( r3) sw r1, 0( r4) p *q; p[4] x; Andrew Hilton / Alvin R. Lebeck CPS 104 57
C and assembly: loads/stores int x int * p int ** q # in r1 # in r2 # in r3 x *p; **q x; lw r1, 0( r2) lw r4, 0( r3) p *q; p[4] x; sw r1, 0( r4) lw r2, 0( r3) sw r1, 16( r2) Andrew Hilton / Alvin R. Lebeck CPS 104 58
Executing Memory Ops Address Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 1000 lw r1, 0( r2) 1004 lw r4, 4( r3) 1008 sw r1, 8( r4) 100C lw r2, 0( r3) 1010 8000 F00D F00D 8004 C001 D00D 8008 1234 4321 8010 4242 4242 8014 0000 8000 Andrew Hilton / Alvin R. Lebeck CPS 104 Value 0000 0000 1234 5678 0000 8004 0000 8010 9999 9999 9999 999C 0000 0002 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 59
Executing Memory Ops Address Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 1000 lw r1, 0( r2) 1004 lw r4, 4( r3) 1008 sw r1, 8( r4) 100C lw r2, 0( r3) 1010 8000 F00D F00D 8004 C001 D00D 8008 1234 4321 8010 4242 4242 8014 0000 8000 Andrew Hilton / Alvin R. Lebeck CPS 104 Value 0000 0000 1234 5678 0000 8004 0000 8010 9999 9999 9999 999C 0000 0002 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 60
Executing Memory Ops Address Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 1000 lw r1, 0( r2) 1004 lw r4, 4( r3) 1008 sw r1, 8( r4) 100C lw r2, 0( r3) 1010 8000 F00D F00D 8004 C001 D00D 8008 1234 4321 8010 4242 4242 8014 0000 8000 Andrew Hilton / Alvin R. Lebeck CPS 104 Value 0000 0000 C001 D00D 0000 8004 0000 8010 9999 9999 9999 999C 0000 0002 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1004 61
Executing Memory Ops Address Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 1000 lw r1, 0( r2) 1004 lw r4, 4( r3) 1008 sw r1, 8( r4) 100C lw r2, 0( r3) 1010 8000 F00D F00D 8004 C001 D00D 8008 1234 4321 8010 4242 4242 8014 0000 8000 Andrew Hilton / Alvin R. Lebeck CPS 104 Value 0000 0000 C001 D00D 0000 8004 0000 8010 0000 8000 9999 999C 0000 0002 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1008 62
Executing Memory Ops Address Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 1000 lw r1, 0( r2) 1004 lw r4, 4( r3) 1008 sw r1, 8( r4) 100C lw r2, 0( r3) 1010 8000 F00D F00D 8004 C001 D00D 8008 C001 D00D 8010 4242 4242 8014 0000 8000 Andrew Hilton / Alvin R. Lebeck CPS 104 Value 0000 0000 C001 D00D 0000 8004 0000 8010 0000 8000 9999 999C 0000 0002 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 100C 63
Executing Memory Ops Address Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PC Value 1000 lw r1, 0( r2) 1004 lw r4, 4( r3) 1008 sw r1, 8( r4) 100C lw r2, 0( r3) 1010 8000 F00D F00D 8004 C001 D00D 8008 C001 D00D 8010 4242 4242 8014 0000 8000 Andrew Hilton / Alvin R. Lebeck CPS 104 Value 0000 0000 C001 D00D 4242 4242 0000 8010 0000 8000 9999 999C 0000 0002 0000 0002 9999 999A 0000 0000 0000 0000 0000 0000 0000 0000 0000 1010 64
Making control decision Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Control constructs decide what to do next: if (x y) { } else { } while (z q) { } Next Instruction Andrew Hilton / Alvin R. Lebeck CPS 104 65
The Program Counter (PC) Special register (PC) that points to instructions Contains memory address (like a pointer) Instruction fetch is inst mem[pc] So far, have fetched sequentially: PC PC 4 Assumes 4 byte insns True for MIPS X86: variable size (nasty) May want to specify non-sequential fetch Change PC in other ways Andrew Hilton / Alvin R. Lebeck CPS 104 66
I-Type op rt, rs, immediate 31 26 25 Op 21 20 Rs 16 15 0 Rt Immediate 00 PC 4 PC relative addressing Branch Not Equal Example bne 1, 2, 100 # If ( 1! 2) goto [PC 4 400] //why 400? 4 because by default we increment for sequential more detailed discussion later in semester op 000101 rs rt 00001 00010 Andrew Hilton / Alvin R. Lebeck immediate 0000 0000 0110 0100 CPS 104 67
MIPS Compare and Branch Compare and Branch beq rs, rt, offset if R[rs] R[rt] then PC-relative branch bne rs, rt, offset Compare to zero and Branch blez rs, offset bgtz rs, offset bltz rs, offset bgez rs, offset bltzal rs, offset bgeal rs, offset if R[rs] 0 then PC-relative branch if R[rs] 0 then branch and link (into R 31) Also pseudo-insns for unconditional branch (b) Andrew Hilton / Alvin R. Lebeck CPS 104 68
MIPS jump, branch, compare instructions Other compare: require 2 insns Conditionally set reg, branch if not zero or if zero Instruction set on less than Example slt 1, 2, 3 set less than imm. slti 1, 2,100 set less than uns. sltu 1, 2, 3 set l. t. imm. uns. sltiu 1, 2,100 Branch if zero beqz 1,100 Branch if not zero bnez 1,100 Andrew Hilton / Alvin R. Lebeck Meaning 1 ( 2 3) ? 1 : 0 Compare less than; signed 2’s comp. 1 ( 2 100) ? 1 : 0 Compare constant; signed 2’s comp. 1 ( 2 3) ? 1 : 0 Compare less than; unsigned 1 ( 2 3) ? 1 : 0 1 0 Compare constant; unsigned if ( 1 2) go to PC 4 400 if ( 1! 2) go to PC 4 400 CPS 104 69
Signed v.s. Unsigned Comparison R1 0 00 0000 0000 0000 0001 R2 0 00 0000 0000 0000 0010 R3 1 11 1111 1111 1111 1111 After executing these instructions: slt r4,r2,r1 slt r5,r3,r1 sltu r6,r2,r1 sltu r7,r3,r1 What are values of registers r4 - r7? Why? r4 ; r5 ; r6 ; r7 ; Andrew Hilton / Alvin R. Lebeck CPS 104 70
Signed v.s. Unsigned Comparison R1 0 00 0000 0000 0000 0001 R2 0 00 0000 0000 0000 0010 R3 1 11 1111 1111 1111 1111 After executing these instructions: slt r4,r2,r1 slt r5,r3,r1 sltu r6,r2,r1 sltu r7,r3,r1 What are values of registers r4 - r7? Why? r4 0 ; r5 1 ; r6 0 ; r7 0 ; Andrew Hilton / Alvin R. Lebeck CPS 104 71
C and Assembly with branches int x; int y; //assume x in r1 //assume y in r2 int z; if (x ! y) { z z 2; //assume z in r3 bne r1, r2, 2 addi r3, r3, 2 } else { Z z -4; b 1 addi r3, r3, -4 } Andrew Hilton / Alvin R. Lebeck CPS 104 72
Labels Counting insns? Error prone Tricky: pseudo-insns Un-maintainable Better: let assembler count Use a label Symbolic name for target Assembler computes offset //assume x in r1 //assume y in r2 //assume z in r3 bne r1, r2, L else addi r3, r3, 2 b L end L else: addi r3, r3, -4 L end: Andrew Hilton / Alvin R. Lebeck CPS 104 73
J-Type op immediate 31 26 25 Op 21 20 Rs 16 15 Rt 0 Immediate 16-bit imm limits to /- 32K insns Usually fine, but sometimes need more J-type insns provide long range, unconditional jump: 31 0 26 Op Target Address Specifies lowest 28 bits of PC Upper 4 bits unchanged Range: 64 Million instruction (256 MB) Can jump anywhere with jr reg (jump register) Andrew Hilton / Alvin R. Lebeck CPS 104 74
Remember our F2C program fragment? Consider the following C fragment: int int a int tempF 87; a tempF – 32; a * 5; tempC a / 9; li addi li mul r3, r4, r6, r4, 87 r3, -32 5 r4, r6 li r6, 9 If we were really doing this div r5, r4, r6 We would write a function to convert f2c and call it Andrew Hilton / Alvin R. Lebeck CPS 104 75
More likely: a function to convert Like this: int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; } int tempC f2c (87); Andrew Hilton / Alvin R. Lebeck CPS 104 76
Need a way to call f2c and return Call: Jump but also remember where to go back May be many calls to f2c() in the program Need some way to know where we were Return: Jump back to wherever we were Andrew Hilton / Alvin R. Lebeck CPS 104 77
J-Type: 31 op target 26 Op Target Address 00 PC 31 4 Jump and Link (“Call”) Example JAL 1000 # 31 -PC 4, PC - 4000 31 set as side effect, used for returning, implicit operand op 000011 Target 00 0000 0000 0000 0011 1110 1000 Andrew Hilton / Alvin R. Lebeck CPS 104 78
R Type: OP rd, rs, rt 31 26 25 Op 21 20 Rs 16 15 Rt 11 10 Rd 6 5 shamt 0 func Jump Register Example jr 31 # PC - 31 op 000000 rs rt rd shmt 11111 00000 00000 00000 Andrew Hilton / Alvin R. Lebeck CPS 104 func 001000 79
More likely: a function to convert Like this: int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; } int tempC f2c (87); //jr 31 //jal f2c But that’s not all Andrew Hilton / Alvin R. Lebeck CPS 104 80
More likely: a function to convert Like this: int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; } int tempC f2c (87); //jr 31 //jal f2c Need to pass 87 as tempF argument Andrew Hilton / Alvin R. Lebeck CPS 104 81
More likely: a function to convert Like this: int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; } int tempC f2c (87); //jr 31 //jal f2c Need return tempC properly Remember no scope in assembly Andrew Hilton / Alvin R. Lebeck CPS 104 82
More likely: a function to convert Like this: int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; } int tempC f2c (87); //jr 31 //jal f2c Also: may want to use same registers in different functions Andrew Hilton / Alvin R. Lebeck CPS 104 83
Calling Convention All of these are reasons for a calling convention Agreement of how registers are used Where arguments are passed, results returned Who must save what if they want to use it Etc. Alternative: inter-procedural register allocation More work for compiler Only know one real compiler that does this Andrew Hilton / Alvin R. Lebeck CPS 104 84
MIPS Register Naming Conventions 0 zero constant 0 16 s0 callee saves 1 at . 2 v0 expression evaluation & 23 s7 3 v1 function results 24 t8 4 a0 arguments 25 t9 5 a1 26 k0 reserved for OS kernel 6 a2 27 k1 7 a3 28 gp Pointer to global area 8 t0 reserved for assembler temporary: caller saves temporary (cont’d) 29 sp Stack pointer . 30 fp frame pointer 15 t7 31 ra Return Address (HW) Andrew Hilton / Alvin R. Lebeck CPS 104 85
More likely: a function to convert int f2c (int tempF) { int a tempF – 32; f2c: addi t0, a0, -32 a a * 5; int tempC a / 9; return tempC; } tempF is in a0 by calling convention Andrew Hilton / Alvin R. Lebeck CPS 104 86
More likely: a function to convert int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; f2c: addi t0, a0, -32 } We can use t0 for a temp (like a) without saving it Andrew Hilton / Alvin R. Lebeck CPS 104 87
More likely: a function to convert int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; f2c: addi t0, a0, -32 li t1, 5 mul t0, t0, t1 } Andrew Hilton / Alvin R. Lebeck CPS 104 88
More likely: a function to convert int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; f2c: addi t0, a0, -32 li t1, 5 mul t0, t0, t1 li t1, 9 div t2, t0, t1 } Andrew Hilton / Alvin R. Lebeck CPS 104 89
More likely: a function to convert int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; f2c: addi t0, a0, -32 li t1, 5 mul t0, t0, t1 li t1, 9 div t2, t0, t1 addi v0, t2, 0 jr ra } A smart compiler would just do div v0, t0, t1 Andrew Hilton / Alvin R. Lebeck CPS 104 90
More likely: a function to convert int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; f2c: addi t0, a0, -32 li t1, 5 mul t0, t0, t1 li t1, 9 div t2, t0, t1 addi v0, t2, 0 jr ra } int tempC f2c(87) Andrew Hilton / Alvin R. Lebeck addi a0, r0, 87 CPS 104 91
More likely: a function to convert int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; f2c: addi t0, a0, -32 li t1, 5 mul t0, t0, t1 li t1, 9 div t2, t0, t1 addi v0, t2, 0 jr ra } int tempC f2c(87) Andrew Hilton / Alvin R. Lebeck addi a0, r0, 87 jal f2c CPS 104 92
More likely: a function to convert int f2c (int tempF) { int a tempF – 32; a a * 5; int tempC a / 9; return tempC; f2c: addi t0, a0, -32 li t1, 5 mul t0, t0, t1 li t1, 9 div t2, t0, t1 addi v0, t2, 0 jr ra } int tempC f2c(87) Andrew Hilton / Alvin R. Lebeck addi a0, r0, 87 jal f2c addi t0, v0, 0 # assume tempC in t0 CPS 104 93
What it would take to make SPIM happy .globl f2c .ent f2c .text f2c: addi t0, a0, -32 li t1, 5 mul t0, t0, t1 # f2c can be called from any file # en
Instruction How are Instructions Executed? Instruction Fetch: Read instruction bits from memory Decode: Figure out what those bits mean Operand Fetch: Read registers mem to get sources Execute: Do the actual operation (e.g., add the #s) Result Store: Write result to register or memory Next Instruction:
May 02, 2018 · D. Program Evaluation ͟The organization has provided a description of the framework for how each program will be evaluated. The framework should include all the elements below: ͟The evaluation methods are cost-effective for the organization ͟Quantitative and qualitative data is being collected (at Basics tier, data collection must have begun)
Silat is a combative art of self-defense and survival rooted from Matay archipelago. It was traced at thé early of Langkasuka Kingdom (2nd century CE) till thé reign of Melaka (Malaysia) Sultanate era (13th century). Silat has now evolved to become part of social culture and tradition with thé appearance of a fine physical and spiritual .
bits, gọi là MIPS-64. MIPS xem xét trong môn học này là MIPS làm việc với các thanh ghi chỉ 32 bit, gọi là MIPS-32. ÞTrong phạm vi môn học này, MIPS dùng chung sẽ hiểu là MIPS-32 Tóm lại, chỉ có 3 loại toán hạng trong một lệnh của MIPS 1. Toán hạng thanh ghi (Register Operands) 2.
On an exceptional basis, Member States may request UNESCO to provide thé candidates with access to thé platform so they can complète thé form by themselves. Thèse requests must be addressed to esd rize unesco. or by 15 A ril 2021 UNESCO will provide thé nomineewith accessto thé platform via their émail address.
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Dr. Sunita Bharatwal** Dr. Pawan Garga*** Abstract Customer satisfaction is derived from thè functionalities and values, a product or Service can provide. The current study aims to segregate thè dimensions of ordine Service quality and gather insights on its impact on web shopping. The trends of purchases have
The MIPS Instruction Set This section brie y describes the MIPS assembly language instruction set. In the description of the instructions, the following notation isused: If an instruction description begins with an, then the instruction is not a member of the native MIPS instruction set, but is available as a pseudoin-
Performance on EEMBC benchmarks aggregate for Consumer, Telecom, Office, Network, based on ARM1136J-S (Freescale i.MX31), ARM1026EJ-S, Tensilica Diamond 570T, T1050 and T1030, MIPS 20K, NECVR5000). MIPS M4K, MIPS 4Ke, MIPS 4Ks, MIPS 24K, ARM 968E-S, ARM 966E-S, ARM926EJ-S, ARM7TDMI-S scaled by ratio of Dhrystone MIPS within architecture family.
