Chip And System-level Integration Technologies For Silicon Photonics
IBM Research - Zurich Chip and system-level integration technologies for silicon photonics Bert Jan Offrein 5th International Symposium for Optical Interconnect in Data Centres 2017 IBM Corporation
IBM Research - Zurich Outline The need for integration at component and system level – CMOS silicon photonics with embedded III-V materials – High channel count silicon photonics packaging Summary 2 2017 IBM Corporation
IBM Research - Zurich Communication between two processors Electrical V laser Optical driver modulator Optical communication: V 1000 x Larger bandwidth 1000 x Lower loss 100 x Larger distance amplifier Scalability & Power efficiency !!! Optical communication requires many more components and assembly steps !!! 3 2017 IBM Corporation
IBM Research - Zurich Photonics technologies for system-level integration 1 Chip-level: CMOS silicon photonics Active photonics devices Si photonics provides all required buliding blocks (except lasers) on chip-level: - Modulators - Drivers - Detectors - Amplifiers - WDM filters CMOS electronics 2 System-level: Scalable chip-to-fiber connectivity One step mating of numerous optical interfaces Provide electrical and optical signal routing capability Enable a simultaneous interfacing of electrical and optical connections 2017 IBM Corporation
IBM Research - Zurich Photonics technologies for system-level integration 1 Chip-level: CMOS silicon photonics Active photonics devices Si photonics provides all required buliding blocks (except lasers) on chip-level: - Modulators - Drivers - Detectors - Amplifiers - WDM filters CMOS electronics 2 System-level: Scalable chip-to-fiber connectivity One step mating of numerous optical interfaces Provide electrical and optical signal routing capability Enable a simultaneous interfacing of electrical and optical connections 2017 IBM Corporation
IBM Research - Zurich CMOS Embedded III-V on silicon technology BEOL SiO2 Electrical contacts III-V FEOL Front-end CMOS Si Photonics Si SiO2 Si wafer III-V functionality Ultra-thin III-V layer stack (300 nm) enables embedding in between FEOL and BEOL Integration of III-V functionality in the CMOS processing flow Power efficient lasers for silicon photonics by high modal overlap concept Flexible design, on-chip control and cost-effective source integration 6 2017 IBM Corporation
IBM Research - Zurich Challenges for III-V laser integration in CMOS III-V mesa Si waveguide Adiabatic taper – top view III-V to silicon optical coupler Oxide cladding CMP Contact resistvity ( cm2) Silicon photonics Current confinement 1E-4 Without Au With Au T 1E-5 1E-6 1E-7 IBM Au-free v1 IBM Au-free v2 Doping Level III-V pattering BEOL Bonding of III-V epi wafer Optimized process flow CMOS-compatible Ohmic contacts on n and p-InP 2017 IBM Corporation
IBM Research - Zurich Processing scheme 5 InAlGaAs quantum wells (MOCVD) SiO2 III-V epi layer epi layer SiO2 SiPh wafer SiPh wafer Wafer bonding Feedback grating SiO2 SiO2 Substrate removal III-V structuring MQW section SiO2 Metallization 8 2017 IBM Corporation
IBM Research - Zurich Optically pumped ring laser Measured FSR: 0.194 nm Estimated FSR from ring: 0.203 nm Estimated FSR from III-V: 0.266 nm Lasing with feedback from silicon photonics Directional coupler output Gain section 9 2017 IBM Corporation
IBM Research - Zurich Electrically pumped LED p-InGaAs/p-InP 4.5 InAlGaAs V-I measurement 4.0 3.5 Voltage (V) 3.0 n-InP 2.5 2.0 Cross-section SEM 1.5 1.0 0.5 IR camera photograph 0.0 0 2000 4000 6000 8000 10000 12000 14000 Current density (A/cm2) LED test-device for process optimization Good V-I characteristic Electro-luminescence emission visible with IR-camera 16000 DuT S G Electrical probe 10 2017 IBM Corporation
IBM Research - Zurich Electrically pumped lasers Optical spectrum at 100 K 5000 Lasing modes Counts (a.u.) 4000 3000 2000 Spontaneous emission 1000 0 1160 1180 1200 1220 1240 1260 Wavelength (nm) Laser devices: 10 dB optical loss at room temperature Cooling down increases gain Increased gain can overcome loss Work in progress ! Pulsed electrical pumping 11 2017 IBM Corporation
IBM Research - Zurich H2020 EU project L3MATRIX Integration: SiPh optical interconnect (8x16) with 16nm CMOS switching ASIC Scaling chip I/O towards Pb/s Silicon photonics (single-mode) Increased reach Reducing network layers: less latency, more servers & memory more throughput High level of integration: Need on-chip lasers 12 2017 IBM Corporation
IBM Research - Zurich H2020 EU project DIMENSION 13 2017 IBM Corporation
IBM Research - Zurich Photonics technologies for system-level integration 1 Chip-level: CMOS silicon photonics Active photonics devices Si photonics provides all required buliding blocks (except lasers) on chip-level: - Modulators - Drivers - Detectors - Amplifiers - WDM filters CMOS electronics 2 System-level: Scalable chip-to-fiber connectivity One step mating of numerous optical interfaces Provide electrical and optical signal routing capability Enable a simultaneous interfacing of electrical and optical connections 2017 IBM Corporation
IBM Research - Zurich Adiabatic optical coupling using polymer waveguides Principle: – Contact between the silicon waveguide taper and the polymer waveguide (PWG), achieved by flip-chip bonding, enables adiabatic optical coupling Schematic view of Si- photonics chip assembled by flip-chip bonding Compatible with established electrical assembly Simultaneous E/O interfacing Scalable to many optical channels - J. Shu, et al. "Efficient coupler between chip-level and board-level optical waveguides." Optics letters 36.18 (2011): 3614-3616. - I. M. Soganci, et al. "Flip-chip optical couplers with scalable I/O count for silicon photonics." Optics express 21.13 (2013): 16075-16085. - T. Barwicz, et al. "Low-cost interfacing of fibers to nanophotonic waveguides: design for fabrication and assembly tolerances.“, Photonics Journal, IEEE 6.4 (2014): 1-18. 15 2017 IBM Corporation
IBM Research - Zurich Single-mode polymer waveguide technology SM polymer waveguides on chips (e.g. Si photonics chips) Panel-size Chip-size SM polymer waveguides on panel-size flexible substrates 50 mm SM waveguide Wafer- size SM polymer waveguides on wafer-size flexible substrates R. Dangel, et al. Optics Express, 2015 16 2017 IBM Corporation
IBM Research - Zurich Insertion loss characterization (1) IL/2 of reference PWG (dB) Insertion loss measurement: Wavelength sweep over O-band – Full path vs ref. PWG path Wavelength dependency mainly in the PWG 5 TE, LPWG 3.0 cm 4 TM, LPWG 3.0 cm 3 2 1 0 1260 1280 1300 1320 1340 1360 1380 Wavelength (nm) 5 TE, LC 1.5 mm IL/facet (dB) 4 Schematic view of Siphotonics chip assembled by flip-chip bonding TM, LC 1.5 mm 3 2 1 0 1260 1280 1300 1320 1340 1360 1380 Wavelength (nm) 17 2017 IBM Corporation
IBM Research - Zurich Adiabatic coupler loss characterization Coupler loss measurement: Direct-process vs Flip-chip bonding approach For Lc 1.0 mm: Coupler loss 1.5 dB, PDL 0.7 dB Operating in the O and C-band Polymer waveguides processed on chip 18 Polymer waveguides attached by flip-chip bonding 2017 IBM Corporation
IBM Research - Zurich H2020 EU project ICT-STREAMS 19 2017 IBM Corporation
IBM Research - Zurich From Si photonics transceivers to chip-level assembly Today Next integration step Silicon photonics co-packaging with the ASIC chip – Less components and assembly steps – Improved electrical signal path, reduce # interfaces and length – High density, scalable optical IO – Minimum overhead, lowest cost Ultra-short electrical line. Overcome CDR and FEC 50% reduction of total link power anticipated 20 2017 IBM Corporation
IBM Research - Zurich Summary Miniaturized Photonic Packaging – Chip level integration CMOS Passive Active photonics – System-level integration Adiabatic optical coupling as a scalable, efficient, broadband and polarization independent fiber-to-chip interfacing solution Path towards high level of electro-optical integration & scalability 21 2017 IBM Corporation
IBM Research - Zurich Acknowledgements 22 Collaborators in IBM – Marc Seifried, Herwig Hahn, Gustavo Villares, Lukas Czornomaz, Folkert Horst, Daniele Caimi, Charles Caer, Yannick Baumgartner Daniel Jubin, Norbert Meier, Roger Dangel, Antonio La Porta, Jonas Weiss, Jean Fompeyrine, Ute Drechsler – And many others Co-funded by the European Union Horizon 2020 Programme and the Swiss National Secretariat for Education, Research and Innovation (SERI) The opinion expressed and arguments employed herein do not necessarily reflect the official views of the Swiss Government. Agreement No 688003 Contract No 15.0313 Agreement No 688172 Contract No 15.0339 Agreement No 688544 Contract No 15.0346 Agreement No 688572 Contract No 15.0309 2017 IBM Corporation
IBM Research - Zurich Thank you for your attention 23 Bert Jan Offrein ofb@zurich.ibm.com 2017 IBM Corporation
Photonics technologies for system-level integration System-level: Scalable chip-to-fiber connectivity Chip-level: CMOS silicon photonics Active photonics devices Si photonics provides all required buliding blocks (except lasers) on chip-level: - Modulators - Drivers - Detectors - Amplifiers - WDM filters CMOS electronics 2 1
10.3.5 Connecting ADC and DAC IPs into a Cortex-M system 242 10.4 243Bring an SoC to life – Beetle test chip case study 10.4.1 Beetle test chip overview 243 10.4.2 Beetle test chip challenges 245 10.4.3 Beetle test chip system design 246 10.4.4 Implementation of the Beetle test chip 24
stair pressurization fan condensing units, typ. of (3) elevator overrun stair pressurization fan november 2, 2016. nadaaa perkins will ]mit ]] ]site 4 october 21 2016 10 7'-3" hayward level 1 level 2 level 3 level 4 level 5 level 6 level 7 level 1 level 2 level 3 level 4 level 5 level 6 level 7 level 8 level 9 level 10 level 11 level 12
and processing unit in a single chip have been reported [7]-[13]. These architectures are proposed for a photo-image sensing chip. Fig. 1 shows the conventional photo-image-sensing chip architecture. In the architecture for a sensor-embedded chip, the sensor and processing unit are integrated on a single chip by placing them side by side, as .
The parallel chip breaker, that the figure N 1 shows an example, is mainly used in finishing operations. Figure N 1 - Parallel chip breaker Inclined chip breaker The angular type is suitable for most machining operations and is the most difficult to do. The chip is flexed towards the area of the workpiece where is broken without damaging .
1.1 Chip breaker A chip breaker is the tool which has a groove or an obstacle placed on the incline face of the tool. A chip breaker can be used for increasing chip breakability which results in efficient chip control and improved productivity. It also decreases cutting resistance, and gives a better surface finish to the workpiece.
NEW CHIP BREAKER FGS TYPE FGS type chip breaker The FGS chip breaker is a positive ground type insert. Its sharp cutting edge generates low cutting resistance while guarantee-ing high precision machining. The chip breaker minimizes heat when machining heat resistant super alloys and the small dot located in the corner is effective for chip control.
Nomenclature bch Chip width (mm), (in) bγ1 Insert/chip restricted contact length (mm), (in) Ch Cutting ratio (the ratio of the undeformed chip thickness to the chip thickness) d Depth of cut (mm), (in) d0 The standard critical depth of cut under pre-defined standard cutting condition (mm), (in) dmax Maximum depth of cut in extra region of chip-breaking chart (mm), (in)
Am I My Brother's Keeper? is a project by British artist Kate Daudy, who has transformed a large UNHCR tent; previously home to a Syrian refugee family in Jordan’s Za’atari camp into a participatory art installation focussing on the concepts of home and identity. During the year and a half she spent researching the project, Daudy visited refugee camps in Jordan. There and across Europe and .
