ECEN 665 (ESS) : RF Communication Circuits And Systems
ECEN 665 (ESS) : RF Communication Circuits and Systems Low Noise Amplifiers Prepared by: Heng Zhang Part of the material here provided is based on Dr. Chunyu Xin’s and Dr. Xiaohua Fan’s dissertation Analog and Mixed-Signal Center, TAMU 1
What is an LNA? s11 s21 S [ ] s s 12 22 Amplifier S matrix: Source reflection coefficient: Load reflection coefficient: Γ L Input reflection coefficient: ΓS Γin s11 s12 s21Γ L 1 s22 Γ L s12 s21Γ S s Γ 22 Output reflection coefficient: out 1 s Γ 11 Analog and Mixed-Signal Center, TAMU S 2
LNA Requirements Gain(10-20dB) to amplify the received signal; to reduce the input referred noise of the subsequent stages Good linearity Handling large undesired signals without much distortion Low noise for high sensitivity Input matching Max power gain Preceding filters require 50Ω termination for proper operation Can route the LNA to the antenna which is located an unknown distance away without worrying about the length of the transmission line Analog and Mixed-Signal Center, TAMU 3
LNA Metrics: Gain Defines small signal amplification capability of LNA For IC implementation, LNA input is interfaced off-chip and usually matched to specific impedance (50Ω or 75Ω). Its output is not necessary matched if directly drive the on-chip block such as mixer. This is characterized by voltage gain or transducer power gain by knowing the load impedance level. Transducer power gain: Power delivered to the load divided by power available from2 source. 2 GT For unilateral device: (i.e. s12 0) 1 ΓS 1 s11Γ S 2 s21 2 Analog and Mixed-Signal Center, TAMU 1 ΓL 1 s22 Γ L 2 4
LNA Metrics: Nonlinearity Model off-band signal f1 f2 f 1- f 2 2 f 1- f 2 f 1 f 2 2 f 2- f 1 2f1 Output signal spectrum with f1 and f2 Nonlinear System (up to 3rd order): Yt a0 a1 X t a2 X t 2 a3 X t 3 2f 2 f 1 2f2 in-band signal f 1 f2 f f Two tone input signal: X t A cos( w1t ) A cos( w2t ) Usually distortion term: 2f1-f2, 2f2-f1 fall in band. This is characterized by 3rd order non-linearity. Large in-band blocker can desensitize the circuit. It is measured by 1-dB compression point. Analog and Mixed-Signal Center, TAMU 5
LNA Metrics: Linearity measurement 1dB compression: Measure gain compression for large input signal IIP3/IIP2: Measure inter-modulation behavior Relationship between IIP3 and P1dB: For one tone test: IIP3-P1dB 10dB For two tone test: IIP3-P1dB 15dB Analog and Mixed-Signal Center, TAMU 6
LNA Metrics: Noise Figure Noise factor is defined by the ratio of output SNR and input SNR. Noise figure is the dB form of noise factor. Noise figure shows the degradation of signal’s SNR due to the circuits that the signal passes. Sensitivity Noisefloor (dBm) SNR NFtot 1442443 174 dBm 10log BW Noise factor of cascaded system: LNA’s noise factor directly appears in the total noise factor of the system. LNA’s gain suppress the noise coming from following stages Analog and Mixed-Signal Center, TAMU 7
MOS Amp Noise Figure Calculation the current gain of the MOS amp is given by: io g m vgs g m vs Rs Rg 1 jωCgs 1 jωCgs gm gm gm vs vs ; ωT Cgs jωCgs ( Rs Rg ) 1 jωCgs ( Rs Rg ) Analog and Mixed-Signal Center, TAMU 8
Noise Figure by Current Gain ωT 1 Gm (ω ) j ω Rs Rg io Gm (ω ) vs the total output noise current is given by: ( ) io2,T Gm 2 vg2 vs2 id2 the noise figure can be easily computed: F io2,T 2 o i io2,T 2 2 m s G v 1 vg2 2 s v id2 2 2 m s , G v γ v 4kTRg , v 4kTRs , i 4kT g m α 2 g 2 s 2 d Analog and Mixed-Signal Center, TAMU 9
Noise Figure Calculation(cont.) Substitution of the the various noise sources leads to : γ 2 gm Rg α ω 2 F 1 ( Rs Rg ) Rs Rs ωT 2 γ ω 1 g m Rs Rs α ωT Rg This expression contains both the channel noise and the gate induced noise 1 is a good approximation Rg R poly 5gm Analog and Mixed-Signal Center, TAMU 10
Minimum Noise for MOS Amp the optimal value of Rs : 2 Rg γ ω F 2 gm 0 Rs α ωT Rs Rs ,opt ωT Rs ω Rg γ gm α Thus the minimum Noise Figure is: Fmin ω γ 1 2 g m Rg ωT α Analog and Mixed-Signal Center, TAMU 11
F vs. Rs For an LNA operating at 5.2GHz in 0.18 μm CMOS process, according to experience and published literatures, we can choose Rg 2Ω, γ 3, α 0.75, ωT 2π*56GHz, gm 50mA/V and plot F vs. Rs: 2 γ ω F 1 g m Rs Rs α ωT Rg Analog and Mixed-Signal Center, TAMU 12
MOS Amp Example Find Rs ,opt for a typical amplifier. Assume fT 75GHz f 5GHz , ( γ α ) 2 , R poly is minimized by proper layout, thus intrinsic gate resistance is given by: 1 1 Rg R poly 5gm 5gm To make the noise contribution from this term 0.1: Rg 10 0.1 g m 40mS Rs ,opt 119Ω, Fmin 1.08 5Rs Rs In practice, it’ll be difficult to get such a low Noise figure and get useful gain with the simple common source due to the bad power match Conflict of minimum noise vs. optimum matching That’s why we need input matching schemes for LNA! Analog and Mixed-Signal Center, TAMU 13
LNA Metrics: Input Matching Why do we need it? We have learned how to choose optimum source impedance for minimum noise figure One important requirement for LNA is 50 ohm matching The input of a common source amplifier is primarily capacitive and provides very poor power match! * Maximum power transfer: Z in Z s Pin LNA max Vs 2 Z in V12 Z in ( Z in Z s ) 2 Vs 2 P in 2 Re( Z s ) 2 What should we do to have both good NF and good power match? Analog and Mixed-Signal Center, TAMU 14
LNA Input Matching Topologies Wideband LNA: ¾Resistive termination ¾Common Gate ¾Resistive shunt-feedback Narrowband LNA: ¾ Inductive degenerated ¾ Resistive terminated Analog and Mixed-Signal Center, TAMU 15
Resistive Termination LNA VDD Since the input of a CS MOS devices is primarily capacitive then we can terminate the input with a resistor Rm Rs to match the input (at low frequencies) RD Zout M2 Vb It can be used in both narrowband and the wideband application. But its high NF(usually NF 6dB) characteristic limits its application. Vout V in Analog and Mixed-Signal Center, TAMU I dc M1 Rs Rm Z in 16
Noise Analysis Output noise due to source resistor Rs: Vn2, s KTRs Av2 KTRs ( g m1 RD ) 2 where Vout * Vn,D2 Av g m1 RD and RD Z out RD Z out 2 in,M2 ro2 - gm2Vx Output noise due to matching resistor Rm( Rs): Vgs2 Vn2,m KTRs ( g m1 RD ) 2 2 n,s Output noise due to thermal noise of M1: V in γ i 4 KT g m1 α Output noise due to the load resistor, RD: Vn2,s KTRD 2 n , m1 C gs2 Rs V * 2 2 * V n,m i g1 Z in Rm C gs1 V1 - gm1V1 ro1 2 i n,M1 Output noise due to thermal noise of M2: 2 2 sC sC g γ gs 2 gs 2 in2,m 2 4 KT g m 2 in2,m1 m 2 g sC g sC α g gs 2 m1 m 2 gs 2 m2 Analog and Mixed-Signal Center, TAMU 17
Noise Analysis The noise factor of the LNA is: V Vn , m Vn ,m1 Vn , D Vn ,m 2 total output noise F n,s noise due to the source resistor Vn2,s 2 2 2 2 2 Noise from RD is attenuated by LNA gain. The noise transfer function of M2 is smaller due to source degeneration. Both are ignored for simplicity: Rm2 4γ 4γ F 1 2 2 Rs α g m1 Rs α g m1 Rs Therefore, even when gmRs 4γ, Fmin 2 (NF 3dB) Resistor termination provides a good power match but greatly degrades the NF ¾The terminating resistor adds its own noise ¾ It also drops the gain by 6dB (compared to CS with no termination). As a result the input referred noise of the device and those of the following stages increase by the same factor Analog and Mixed-Signal Center, TAMU 18
Common Gate(CG) LNA Input impedance: 1 Z in g m jωCgs g 1 if ωCgs g m ω m ω ωT Z in gm Cgs Noise Figure: ignoring poly gate resistance, gate noise, and ro, the output current noise is: 2 2 2 ino ino i ,ind no , Rs ino2 ,ind : drain current noise ino2 , Rs : output noise current due to source resistance 2 ino , Rs 2 ens2 ( Rs Rin ) 2 gm 2 ens 1 g m Rs Analog and Mixed-Signal Center, TAMU 19
Noise Analysis io ind g m vgs ind Rs vgs ( ind g m vgs jωCgs vgs ) Rs vgs 1 g m vgs jωCgs vgs 1 jωCgs Rs 1 io ind ind , ( assume ωCgs Rs 1) 1 g m vgs jωCgs Rs 1 g m Rs Notice that if gm 1/Rs (power match) then only half of drain current noise goes to the output Analog and Mixed-Signal Center, TAMU 20
Noise Analysis Noise Factor: 2 1 i g R 1 γ gd 0 m s 1 2 F 1 2 g m Rs gm 2 ens g R 1 m s 2 nd Under the input matching condition: Rs 1/gm we have: F 1 γ gd 0 gm 5 γ 2.2dB Long channel 1 3 α 3 4.8dB Short channel Analog and Mixed-Signal Center, TAMU 21
Resistive Shunt-feedback LNA The negative feedback network is used to implement the input matching The input impedance is determined by open loop gain and the resistor values (Rf, RL), which are easily controlled. The resistor is a noise component and the LNA has moderate noise performance. Voltage gain: Av RL (1 g m1 R f Input impedance: Z in ) Vout R f RL R f RL 1 g m1 RL RL Rf // Output impedance: Z out RL / / 1 sC gs1 Cf RS M1 V in Rs R f Z out Z in Cgs1 1 g m1 Rs Analog and Mixed-Signal Center, TAMU 22
Noise Analysis Noise Factor: 2 2 4 iR2 f Z out Rs 4 iR2L Z out 4 id21 Z out F 1 2 2 2 2 Vn , Rs Av Vn , Rs Av Vn2, Rs Av2 2 R f 1 g m1 Rs 1 Rs 1 g m1 R f 2 1 R f Rs Rs RL 1 g m1 R f 2 γ g m1 R f Rs α Rs 1 g m1 R f Analog and Mixed-Signal Center, TAMU 2 23
Inductive degenerated LNA Input impedance behaves like a series RLC circuit, gate inductor Lg is added to tune the resonant frequency to align with the operating frequency: Z in s ( Lg Ls ) g L 1 m s sC gs C gs Matching occurs when: ωo2 Z in ( jω0 ) Rs g L 1 , and Rs m s ωT Ls C gs ( Lg Ls ) Cgs Rs L Ls can be selected by: s ωT if this value is too small to be practical, a capacitor can be inserted in shunt with Cgs to artificially reduce ωT Analog and Mixed-Signal Center, TAMU 24
Input impedance-non-idealities Z in s ( Lg Ls ) ωo 1 1 ωT Ls RLg Rg RLs Rg , NQS 1 sC gs s ωT RLs 1 ( Lg Ls ) Cgs / / ω 1R T Ls Rg R poly , shW 12n 2 L Rg , NQS 1 5gm Z in ( jω0 ) ωT Ls RLg Rg RLs Rg , NQS Inductance loss RLg : offset Zin RLs : offset Zin and w0 Gate resistance Rg : offset Zin NQS gate resistance Rg,NQS : offset Zin Analog and Mixed-Signal Center, TAMU 25
Q Boosting At resonance we get Q boosting effect: 1 1 Q ( Rs LsωT ) Cgsω0 2 Rs Cgsω0 vgs Q vs 1 ωT id g m vgs Qg m vs vs { 2 Rs ω0 Gm 14243 Gm Need to watch out for linearity as vgs is Q times larger than the input signal ¾ Short channel devices operating in velocity saturation regime (i.e., large overdrive voltage) are more forgiving as their gm is relatively constant. Analog and Mixed-Signal Center, TAMU 26
Equivalent input network From the source, the amplifier input(ignoring Cgd) is equivalent to: At resonance, the complete circuit is as follows: Analog and Mixed-Signal Center, TAMU 27
Noise Analysis The output noise current due to Rs and Rg is simply calculated by multiplying the voltage noise sources by Gm The calculation of output noise current due to drain noise is more involved: id2 flows partly into the source of the device, it activates the gm of the transistor which produces a correlated noise in shunt with id2 ( ) 1 2 2 2 2 2 i G v v i G , m Rs Rg d , out m Output noise current: no 2 Rs Analog and Mixed-Signal Center, TAMU ωT ω o 28
Noise Analysis: Drain Noise The noise component flowing into the source is given by the current divider: vgs ( g m vgs id ) ( g m vgs id ) jω Ls 1 1 jω Ls jω Lg Rs jωC gs jωC gs jω Ls 1 (at resonance) Rs jωC gs g m vgs id 2 Note that we are not including Rg in the small signal model Analog and Mixed-Signal Center, TAMU 29
Total Output Noise Let’s first ignore the correlation of the gate noise and drain current noise. Notice only ¼ of the drain noise flows to output i G 2 no 2 m (v F 2 Rs v 2 Rg 2 no i Gm2 vR2s ) 1 id2 4 1 Gm 2 Rs ωT ω o ωo γ 1 g m Rs Rs α ω T Rg 2 Note that the Noise figure at resonance is the same as CS amplifier w/o inductive degeneration. Inductive degeneration did not raise Fmin but matched the input ! Analog and Mixed-Signal Center, TAMU 30
Total Output Noise(cont.) If we consider the correlation of the gate noise and drain current noise then one can show (*) 2 Rg γ ω F 1 χ g m Rs o Rs α ωT χ 1 2 c QL QL QCgs δα 2 δα 2 1 QL2 ) ( 5γ 5γ ωo ( Lg Ls ) 1 ωo Rs Cgs Rs Optimal Noise figure happens for a particular QL. Possible to obtain a noise and power match * D.K. Shaeffer, T.H. Lee, “A 1.5V 1.5GHz CMOS Low Noise Amplifier”, JSSC, Vol. 32, No. 5. May 1997 Analog and Mixed-Signal Center, TAMU 31
Optimal QL If we try to optimize the noise figure while power dissipation is kept constant then: ¾ QL,opt will be independent from the frequency and around 4.5 ¾ Fmin is not too sensitive to QL and only changes by less than 0.1dB for QL between 3.5 and 5.5 ¾ Smaller QL results in larger bandwidth and smaller inductors, while a larger QL results in narrower bandwidth and larger inductors Analog and Mixed-Signal Center, TAMU 32
Linearity Linearity of a MOS transistor in saturation region: 4 Veff 8 Veff 2 θVeff )(1 θVeff ) ( 3 θ 3 θ 1 Vgs Vth θ Esat L 2 IIP 3, strong MOS V Veff Esat 1V/μm for L 0.35 μm-0.18 μm IIP3 is independent of W 2 2 VIIP 3, LNA (V ) ρ θVeff 2 D 2 2 o 16 P 3 Pθ ( 2 ρ ) 1 3 vsat Esat Po VDD 2 ωo Rs 1 ρ 3 MOS transistor’s IIP3 v.s. gate drive voltage Analog and Mixed-Signal Center, TAMU 33
Design Recipe for Inductive degenerated LNA Step 1: Choose QL for optimal NF Cgs Width(W) (Q L 1 ωo Rs Cgs ) Step 2: Determine the current(Id) from power budget Step 3: From W & Id gm and Veff Step 4: From gm and Veff ωT and Fmin Step 5: Select Ls and Lg for the input network Ls Rs ωT Lg (1/ ωo2C gs ) Ls Analog and Mixed-Signal Center, TAMU 34
Design Recipe: Iterations NF is not low enough? Linearity doesn’t meet spec? Increase ωT by increasing Id (with fixed device size) For fixed current density, increasing Q will reduce device size thus reduce total power - NF will increase Reduce Q (in short channel devices the improvement is limited) Burn more current (not gaining much due to velocity saturation) Apply proper linearization techniques Need to increase gain? Larger QL Larger gm Larger Load(ZL) Analog and Mixed-Signal Center, TAMU 35
Design Example: Specs: Step 1: Choose QL 4.5. then C gs 1 2QLωo Rs 147 fF Frequency 2.4GHz S11 -10dB S21 15dB NF 2dB IIP3 -10dBm Current 10mA Supply 1.8V Process 0.18μm CMOS Choose minimum length L 0.18μm Æ W 110μm Step 2: Choose the current Id 9mA Step 3: From W & Id Æ gm 52mA/V Step 4: From gm and Cgs Æ fT 56GHz Step 5: Select Ls and Lg for the input network: Ls Rs ωT 0.14nH Lg 1 ωo2Cgs Ls 31nH Step 6: S21 requirementÆ ZL 24Ω Analog and Mixed-Signal Center, TAMU 36
Simulation Results: S21, S11, NF Analog and Mixed-Signal Center, TAMU 37
Simulation Results: IIP3 Analog and Mixed-Signal Center, TAMU 38
Summary: Parameters: Calculated M1 110μm/0.18 110μm/0.18 M2 μm Performance: Simulated 110μm/0.18 μm 110μm/0.18 Specs Simulation Frequency 2.4GHz 2.4GHz S11 -10dB -32dB Lg μm 31nH μm 20nH S21 15dB 15.7dB Ls 0.14nH 0.28nH NF 2dB 0.62dB Id 9mA 8.6mA IIP3 -10dBm -6.85dBm ZL 24Ω 26Ω Current 10mA 8.6mA Supply 1.8V 1.8V Analog and Mixed-Signal Center, TAMU 39
Effect of RL on input match We ignored the effect of load impedance on input impedance in previous derivations. Let’s revisit it: It can be shown that: 2 Lsω ) ( ro 1 jLsω Z in LsωT jCgsω ro RL jLsω ro ro 1 jLsω [ LsωT ] jCgsω ro RL RL can be large and it can drop the real part of the input impedance when we use resonators at output Notice that the output impedance influenced the input impedance even in the absence of Cgd! Analog and Mixed-Signal Center, TAMU 40
Differential v.s. Single-ended LNA Differential Single-ended 9reject common mode noise and interferer 9shield the bond wire 9compact layout size 9less power for same NF and linearity x double area and current x susceptive to bond wire x need balun at input and PCB trace x common-mode stability x drive single-balance mixer; or x linearity limited by bias current use output balun to drive doublebalance mixer Analog and Mixed-Signal Center, TAMU 41
Differential LNA Common-mode Stability Issue Z in ,com jω ( Lg Ls ) C1 C2 jωC1C2 g m Ls gm 2 C1 ω C1C2 Real part: Rin ,com Typical differential LNA gm 1 L s ω 2 C2 C1 Common-mode half circuit For passive termination, the real part of the source impedance will always be positive. IF Rin,com happens to be negative and cancel the real part of source impedance, oscillation MAY occur. Analog and Mixed-Signal Center, TAMU 42
Variant of Inductive Degenerated LNA nMOS-pMOS shunt input Current reuse to save power Larger area due to two degeneration on chip inductor Single-ended version of current reuse LNA (bias not shown) NF: 2dB, Power gain: 17.5dB, IIP3: -6dBm, Id: 8mA from 2.7V power supply F. Gatta, E. Sacchi, et al, “A 2-dB Noise Figure 900MHz Differential CMOS LNA,” IJSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452 Analog and Mixed-Signal Center, TAMU 43
Variant of Inductive Degenerated LNA Inter-stage inductor with parasitic capacitance form impedance match network between input stage and cascoded stage boost gain lower noise figure. Input match condition will be affected Single-ended version of current reuse LNA (bias not shown) Chunyu Xin, and Edgar Sánchez-Sinencio, “A GSM LNA Using Mutual-Coupled Degeneration”, IEEE Microwave and Wireless Components Letters, VOL. 15, NO. 2, Feb 2005 Analog and Mixed-Signal Center, TAMU 44
Comparison of LNA Architectures Resistive Termination Common Gate Shunt Feedback Inductive Degeneration Noise Figure 6dB 3 5dB 2.8 5dB 2dB Gain 10 20dB 10 20dB 10 20dB 15 25dB Sensitivity to Parasitic Less Less Less Large Input Matching Easy Easy Easy Complex Linearity -10 10dBm -5 5dBm -5 5dBm -10 0dBm Power 1 50mW 5mW 15mW 10mW Highlight Effortless input matching Easy input matching Broadband input/out matching Good narrowband Matching, small NF Drawback Large NF Large NF Stability Large area Analog and Mixed-Signal Center, TAMU 45
Substrate Noise A MOS device is in fact a 4 terminal device. The 4th terminal is the substrate. The bulk-source potential modulates the drain current with a transconductance of gmb which has the same polarity as gm (i.e., increasing the bulk potential increases the drain current) The substrate has a finite (nonzero) resistance and therefore has thermal noise To reduce Rsub we should put many substrate contacts close to the device 4kTRsub 2 2 ino , sub 1 (ω RsubCb ) 2 Δf g mb Substrate noise characterization: John T. Colvin et.al: “Effects of Substrate Resistances on LNA Performance and a Bondpad”, JSSC Sep. 1999 Analog and Mixed-Signal Center, TAMU 46
Substrate Noise(cont.) Solution: Place as many substrate contact as possible! Pros: Reduces possibility of latch up issues Lowers Rsub and its associated noise(Impacts LNA through backgate effect (gmb) Absorbs stray electrons from other circuits that will otherwise inject noise into the LNA Cons: takes up a bit extra area Analog and Mixed-Signal Center, TAMU 47
Package Parasitics As interface to the external world, the LNA must transit from the silicon chip to the package and board environment, which involves bondwires, package leads, and PCB trace. Analog and Mixed-Signal Center, TAMU 48
Package Parasitics(cont.) Two effects from bondwire and package inductance: Value of degeneration inductor is altered Noise from other circuits couples into LNA Analog and Mixed-Signal Center, TAMU 49
Package Parasitics(cont.) Some or all of the degeneration inductor Ls can be absorbed into the bondwire inductance These parasitics must be absorbed into the LNA design. This requires a good model for the package and bondwires. It should be noted that the inductance of the input loop depends on the arrangement of the bondwires, and hence die size and pad locations. Many designs also require ESD protection, which manifests as increased capacitance on the pads. For more details, please read: 1. B. Razavi, “Design of Analog CMOS Integrated Circuits (chapter 18) ” McGraw-Hill, New York 2001. 2. Andrzej Szymañski et.al: “Effects of package and process variation on 2.4 GHz analog integrated circuits”, Microelectronics and Reliability, Jan. 2006 Analog and Mixed-Signal Center, TAMU 50
Cadence Simulation for LNA Characterization of the major Figure of merit of an LNA in Cadence S-parameter simulation input and output match noise figure gain Periodic steady state (pss) simulation/SPSS IIP2/IIP3, 1dB point Please refer to Lab 3 manual Analog and Mixed-Signal Center, TAMU 51
LNA Testing: S parameter Before doing the measurement: ¾ Calibrate two lines. ¾ Adjust the power level Analog and Mixed-Signal Center, TAMU 52
LNA Testing: Linearity(IIP3/IIP2) RF IN Output Signal Analog and Mixed-Signal Center, TAMU 53
LNA Testing: Noise Figure Spectrum Analyzer Noise Source Analog and Mixed-Signal Center, TAMU 54
7 LNA Metrics: Noise Figure Noise factor is defined by the ratio of output SNR and input SNR. Noise figure is the dB form of noise factor. Noise figure shows the degradation of signal's SNR due to the circuits that the signal passes. Noise factor of cascaded system: LNA's noise factor directly appears in the total noise factor of the system.
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