Solutions Manual Revised - Personal.psu.edu
Solutions ManualSILICON VLSI TECHNOLOGYFundamentals, Practice and ModelsSolutions Manual for InstructorsJames D. PlummerMichael D. DealPeter B. GriffinSILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin1 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualChapter 1 Problems1.1. Plot the NRTS roadmap data from Table 1.1 (feature size vs. time) on anexpanded scale version of Fig. 1.2. Do all the points lie exactly on a straightline? If not what reasons can you suggest for any deviations you Interestingly, the actual data seems to consist of two slopes, with a steeper slope forthe first 2 years of the roadmap. Apparently the writers of the roadmap are moreconfident of the industry's ability to make progress in the short term as opposed tothe long term.1.2. Assuming dopant atoms are uniformly distributed in a silicon crystal, how farapart are these atoms when the doping concentration is a). 1015 cm-3, b). 1018cm-3, c). 5x1020 cm-3.Answer:The average distance between the dopant atoms would just be one over the cuberoot of the dopant concentration:(b) x (1x10a) x 1x1015 cm 318cm)) 1 / 3 3 1 / 3x N A 1 / 3 1x10 5cm 0.1μm 100nm 1x10 6cm 0.01μm 10nmSILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin2 2000 by Prentice HallUpper Saddle River, NJ.
Solutions Manual(20 3c) x 5x10 cm) 1 / 3 1.3x10 7cm 0.0013μm 1.3nm1.3. Consider a piece of pure silicon 100 µm long with a cross-sectional area of 1µm2. How much current would flow through this “resistor” at roomtemperature in response to an applied voltage of 1 volt?Answer:If the silicon is pure, then the carrier concentration will be simply ni. At roomtemperature, ni 1.45 x 1010 cm-3. Under an applied field, the current will be due todrift and hence,()I I n I p qAn i μ n μ p ε( 1.6x10 19)(coul 10 8cm2)(1.45x1010carrierscm 3)(2000cm volt2 1sec 1) 101voltcm 2 4.64x10 12 amps or 4.64pA1.4. Estimate the resistivity of pure silicon in Ω ohm cm at a) room temperature, b)77K, and c) 1000 C. You may neglect the temperature dependence of thecarrier mobility in making this estimate.Answer:The resistivity of pure silicon is given by Eqn. 1.1 asρ 11 q μ n n μp pqni μ n μ p()()Thus the temperature dependence arises because of the change in ni with T. UsingEqn. 1.4 in the text, we can calculate values for ni at each of the temperatires ofinterest. Thus 0.603eV n i 3.1x1016 T 3/ 2 exp kT which gives values of 1.45 x 1010 cm-3 at room T, 7.34 x 10-21 cm-3 at 77K and 5.8x 1018 cm-3 at 1000 C. Taking room temperature values for the mobilities , µn 1500 cm2 volt-1 sec-1 and , µp 500 cm2 volt-1 sec-1, we have,SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin3 2000 by Prentice HallUpper Saddle River, NJ.
Solutions Manualρ 2.15x105 Ωcm at room T 4.26x10 35 Ωcm at 77K 5.39x10 4 Ωcm at 1000 ÞCNote that the actual resistivity at 77K would be much lower than this value becausetrace amounts of donors or acceptors in the silicon would produce carrierconcentrations much higher than the ni value calculated above.1.5. a). Show that the minimum conductivity of a semiconductor sample occursμpwhen n ni.μnb). What is the expression for the minimum conductivity?c). Is this value greatly different than the value calculated in problem 1.2 for theintrinsic conductivity?Answer:a).()1 q μ n n μp pρTo find the minimum we set the derivative equal to zero.σ σ q μnn μpp q μ n μ p n n n n{()}μp n 2 n 2iμn n 2i n2 q μ n μ p i2 0n n μpor n niμnb). Using the value for n derived above, we have: μpn2iσ min q μn n i μpμpμn niμn μpμn n μn qμ 2qn i μ nμ pnipi μnμp c). The intrinsic conductivity is given by(σ i qni μ n μ pSILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin4) 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualTaking values of ni 1.45 x 1010 cm-3, µn 1500 cm2 volt-1 sec-1 and , µp 500cm2 volt-1 sec-1, we have:σ i 4.64x10 6 Ωcm and σ min 4.02x10 6 ΩcmThus there are not large differences between the two.1.6. When a Au atom sits on a lattice site in a silicon crystal, it can act as either adonor or an acceptor. ED and EA levels both exist for the Au and both are closeto the middle of the silicon bandgap. If a small concentration of Au is placed inan N type silicon crystal, will the Au behave as a donor or an acceptor? Explain.Answer:In N type material, the Fermi level will be in the upper half of the bandgap as shownin the band diagram below. Allowed energy levels below EF will in general beoccupied by electrons. Thus the ED and EA levels will have electrons filling them.This means the donor level will not have donated its electron whereas the acceptorlevel will have accepted an electron. Thus the Au atoms will act as acceptors in Ntype material.FreeElectronsEC EFEAEDEVHoles1.7. Show that EF is approximately in the middle of the bandgap for intrinsic silicon.Answer:Starting with Eqn. 1.9 and 1.10 in the text, we have E EF E EV n N C exp Cand p NV exp F kTkT In intrinsic material, n p nI, so we haveSILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin5 2000 by Prentice HallUpper Saddle River, NJ.
Solutions Manual E EF EF EV N C exp Cexp NV kT kT N E EV EC EF ln C FkTkT NV Using the definition of NC and NV from Eqn. 1.13, we havem*e3 kT ln * 2E F E C E V4mhEC EV 3m*e E F kT ln *42mhThe second term on the right is negligible compared to the first term on the right, sowe have finally that E F EC EV Ei21.8. Construct a diagram similar to Figure 1-27b for P-type material. Explainphysically, using this diagram, why the capture of the minority carrier electronsin P-type material is the rate limiting step in recombination.Answer:ECETEFEVIn P type material (on the right), there are many more holes than electrons. Thus theprobability of capturing a hole by the trap is high compared to electrons. So thenormal state of occupancy of the trap level will be with a hole present. Therecombination rate will then be limited by the capture of the "scarce" species which isthe minority carrier or electron in this case.Stated another way, since EF is below the trap level in P type material, ET willnormally not be occupied by an electron. Thus the limiting process is the electroncapture.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin6 2000 by Prentice HallUpper Saddle River, NJ.
Solutions Manual1.9. A silicon diode has doping concentrations on the N and P sides of ND 1 x 1019cm-3 and of NA 1 x 1015 cm-3. Calculate the process temperature at which thetwo sides of the diode become intrinsic. (Intrinsic is defined as ni ND or NA.)Answer:Each side of the diode will become intrinsic at the temperature at which nI ND orNA. We can estimate these temperatures by looking at the graph in Fig. 1-16. Fromthe graph, the N side of the diode will become intrinsic around 1400K or 1100 C. TheP side will become intrinsic at a lower temperature since NA is smaller than ND. Fromthe figure, the P side becomes intrinsic at about 500K or 200 C.More accurately, we solve Eqn. 1.4 to find the exact temperature. Thus 0.603eV n i 3.1x1016 T3 / 2 exp kT Setting nI 1019 cm-3 and 1015 cm-3 respectively, we and solving by iteration, we findthat the N side becomes intrinsic at about 1380K or about 1110 C and the P sidebecomes intrinsic at about 545K or about 270 C.1.10. A state-of-the-art NMOS transistor might have a drain junction area of 0.5 x0.5 µm. Calculate the junction capacitance associated with this junction at anapplied reverse bias of 2 volts. Assume the drain region is very heavily dopedand the substrate doping is 1 x 1016 cm-3.Answer:The capacitance of the junction is given by Eqn. 1.25. 1C ε S qε S NA ND A xd 2 NA ND (φi V) The junction built-in voltage is given by Eqn. 1.24. ND is not specified except thatit is very large, so we take it to be 1020 cm-3 (roughly solid solubility). The exactchoice for ND doesn't make much difference in the answer.()( 10 20 cm 3 1016 cm 3kT N DN A (.0259volts )ln lnφi 10 3 2q n 2i 1.45x10 cm()) 0.934 voltsSince ND NA in this structure, the capacitance expression simplifies toSILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin7 2000 by Prentice HallUpper Saddle River, NJ.
Solutions Manual C ε S qεS1 NA )(A W 2(φ i V) ()()() 1.6x10 19 coul (11.7) 1016 cm 3 8.86x10 14 Fcm 1 8 2 1.68x10 Fcm(2)(2.934volts) Given the area of the junction (0.25 x 10-8 cm2, the junction capacitance is thus 4.2x 10-17 Farads.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin8 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualChapter 2 Problems2.1 Sketch a process flow that would result in the structure shown in Figure 1-34 bydrawing a series of drawings similar to those in this chapter. You only need todescribe the flow up through the stage at which active device formation startssince from that point on, the process is similar to that described in this chapter.Answer:The CMOS technology we need to realize is shown below, from Figure 1-34 in thetext.SPN PSDGN PDGP NP NWELLP-P We can follow many of the process steps used in the CMOS process flow inChapter 2. The major differences are that an epi layer is needed, only one well (Pwell) used, and the device structures are considerably simplified from those in thetext because there are no LDD regions etc.P-P The first step is to grow the blanket epi layer shown in the final cross-section. Aheavily doped P substrate is chosen and a lightly doped boron epitaxial layer isgrown uniformly on its surface.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin9 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualBoronBoronBoronP ImplantP-P Mask #1 patterns the photoresist. The Si3N4 layer is removed where it is notprotected by the photoresist by dry etching.Since the technology uses field implantsbelow the field oxide, a boron implant is used to dope these P regions.PPPP-P During the LOCOS oxidation, the boron implanted regions diffuse ahead of thegrowing oxide producing the P doped regions under the field oxide. The Si3N4 isstripped after the LOCOS process.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin10 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualPhosphorusN ImplantPPPP-P Mask #2 is used to form the N well. Photoresist is used to mask the regions whereNMOS devices will be built. A phosphorus implant provides the doping for the Nwells for the PMOS devicesPPPN wellP-P A high temperature drive-in completes the formation of the N well.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin11 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualBoronPPPPN wellP-P After spinning photoresist on the wafer, mask #3 is used to define the NMOStransistors. A boron implant adjusts the N channel VTH.PhosphorusPPNPPN wellP-P After spinning photoresist on the wafer, mask #4 is used to define the PMOStransistors. A phosphorus or arsenic implant adjusts the P channel VTH. (Dependingon the N well doping, a boron implant might actually be needed at this point insteadof an N type implant, to obtain the correct threshold voltage.)SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin12 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualPNPPPN wellP-P After etching back the thin oxide to bare silicon, the gate oxide is grown for theMOS transistors.PPNPPN wellP-P A layer of polysilicon is deposited. Ion implantation of phosphorus follows thedeposition to heavily dope the poly.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin13 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualPNPPPN wellP-P Photoresist is applied and mask #5 is used to define the regions where MOS gatesare located. The polysilicon layer is then etched using plasma etching.ArsenicN PN PNPPN wellP-P Photoresist is applied and mask #6 is used to protect the PMOS transistors. Anarsenic implant then forms the NMOS source and drain regions.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin14 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualBoronN PN PP NPP PN wellP-P After applying photoresist, mask #7 is used to protect the NMOS transistors. Aboron implant then forms the PMOS source and drain regions.At this point we have completed the formation of the active devices, except for afinal high temperature anneal to activate the dopants and drive in the junctions totheir final depth. The rest of the process flow would be similar to the CMOS flow inthe text.2.2. During the 1970s, the dominant logic technology was NMOS as describedbriefly in Chapter 1. A cross-sectional view of this technology is shown below(see also Figure 1-33). The depletion mode device is identical to theenhancement mode device except that a separate channel implant is done tocreate a negative threshold voltage. Design a plausible process flow to fabricatesuch a structure, following the ideas of the CMOS process flow in this chapter.You do not have to include any quantitative process parameters (times,temperatures, doses etc.) Your answer should be given in terms of a series ofsketches of the structure after each major process step, like the figures inChapter 2. Briefly explain your reasoning for each step and the order youchoose to do things.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin15 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualN PPN N NN PEnhancement TransistorDepletion TransistorPAnswer:We can follow many of the process steps used in the CMOS process flow inChapter 2. The major differences are that only NMOS devices are required (2different threshold voltages however), and there is a buried contact connecting thepoly gate of the depletion device to the source region of that device.PhotoresistSi3N4SiO2P-P Following initial cleaning, an SiO2 layer is thermally grown on the silicon substrate.A Si3N4 layer is then deposited by LPCVD. Photoresist is spun on the wafer toprepare for the first masking operation.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin16 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualPMask #1 patterns the photoresist. The Si3N4 layer is removed where it is notprotected by the photoresist by dry etching.BoronBoronP ImplantPA boron implant prior to LOCOS oxidation increases the substrate doping locallyunder the field oxide to minimize field inversion problems.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin17 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualPPPDuring the LOCOS oxidation, the boron implanted regions diffuse ahead of thegrowing oxide producing the P doped regions under the field oxide. The Si3N4 isstripped after the LOCOS process.As or PhosNPPPMask #2 is used for the the threshold shifting implant for the depletion transistors.An N type dopant is implanted.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin18 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualBPNPPPMask #3 is used to mask the threshold shifting implant for the enhancementtransistors. A P type dopant is implanted.PNPPPAfter etching back the thin oxide to bare silicon, the gate oxide is grown for theMOS transistors.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin19 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualPNPPPMask #4 is used to provide the buried contact. The gate oxide is etched where thepoly needs to contact the silicon.PNPPPA layer of polysilicon is deposited. Ion implantation of an N type dopant followsthe deposition to heavily dope the poly.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin20 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualPNPPPPhotoresist is applied and mask #5 is used to define the regions where MOS gatesare located. The polysilicon layer is then etched using plasma etching.ArsenicPNN ImplantPPPArsenic is implanted to form the source and drain regions. Note that this can beunmasked because there are only NMOS transistors on the chip.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin21 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualN PN N NN PPPA final high temperature drive-in activates all the implanted dopants and diffusesjunctions to their final depth. The N doping in the poly outdiffuses to provide theburied contact.N PN N NN PPPA conformal SiO2 layer is deposited by LPCVD.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin22 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualN PN N NN PPPMask #6 is used to define the contact holes.N PN N NN PPPAluminum is deposited on the wafer.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin23 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualN PN N NN PPPMask #7 is used to pattern the aluminum. After stripping the resist, the structure isfinished to the point shown in the cross-section we started with. In actual practicean additional deposition of a final passivation layer and an additional mask (#8)would be needed to open up the regions over the bonding pads.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin24 2000 by Prentice HallUpper Saddle River, NJ.
Solutions Manual2.3. The cross-section below illustrates a simple bipolar transistor fabricated as partof a silicon IC. (See also Figure 1-32.) Design a plausible process flow tofabricate such a structure, following the ideas of the CMOS process flow in thischapter. You do not have to include any quantitative process parameters (times,temperatures, doses etc.) Your answer should be given in terms of a series ofsketches of the structure after each major process step, like the figures in thischapter. Briefly explain your reasoning for each step and the order you chooseto do things.N N PP NP N PAnswer:PhotoresistSiO2SiFollowing initial cleaning, an SiO2 layer is thermally grown on the silicon substrate.Photoresist is spun on the wafer to prepare for the first masking operation.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin25 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualPMask #1 patterns the photoresist. The SiO2 layer is removed where it is notprotected by the photoresist by dry etching.N PAn N implant is performed to dope the buried layer region. As or Sb wouldtypically be used here because they have smaller diffusivities than P.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin26 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualN PThe buried layer is driven in using a high temperature furnace cycle.NN PThe SiO2 is etched off the surface and an N type epitaxial layer is grown. Note thatduring the epi growth, the buried layer diffuses upwards.SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal and Griffin27 2000 by Prentice HallUpper Saddle River, NJ.
Solutions ManualNN PSiO2 is thermally grown on the surface and photoresist is spun on. Mask #2 is usedto define the resist and then the SiO2 layer is e
Solutions Manual Fundamentals, Practice and Modeling Upper Saddle River, NJ. By Plummer, Deal and Griffin . Solutions Manual Fundamentals, Practice and Modeling Upper Saddle River, NJ. By Plummer, Deal and Griffin . Solutions Manual .
Student Training Manual/Workbook . 5 Law Enforcement/Criminal Justice Use Only Revised 5/23/2016 Revised By: Revised Date: Revised By: Revised Date: Revised By: Revised Date: Revised By: Revised Date: Revised By: Revised Date: Revised By: Revised Date: Revised By: Revised Date: Marie Jernigan Supervisor Training Unit SBI Criminal Information and Identification Section May 23, 2016 Jeannie .
turnitin@psu.edu to get started . doceri.psu.edu Use the Computer, Lose the Podium Make your teaching more engaging by moving about the room Control the classroom computer with just an iPad and your finger Mark It Up Annotate your slides or other presentation materials on the fly .
Installing the Power Supply Unit (PSU) 1. Hold the PSU handle and slide the PSU into the computer. 2. Fol
9. System management-M 4th Edition, April 2011 Server chassis 1. Consolidated PSU 2. Server chassis 3. Cooling fan box 4. Blank Panel 5. Cable Management kit 6. DC power cable Consolidated PSU 1. Consolidated PSU 2. Power supply modul
Yaesu FT-736R PSU repair Updated for DigiKey (North American) sources & data . PSU PCB with 105 C versions, but not necessarily the rectifier filter's 470 uF/200 V big caps, if they seem OK and you can measure their value or even better, the ESR too. b. Replace R17 and R18 (optional) with a pair of 5W, 33ohm resistors (DigiKey p/n
High School and College Credit through Liberty & PSU A student who completes the full Senior Inquiry course should receive the following credit from PSU transfer to other Oregon Universities i.e., Oregon State, University of Oregon, etc Freshman Inquiry Program (Senior Inquiry at LHS) UNST 100 level. The Academic
Relay output of PSU fuse strip can be used for remote control, e.g. external optical indication. Fuse modules and allow to connect 4 or 8 receivers to the PSU. Output state is indicated by green LEDs. Blown fuse signal is transmitted to the input of collective failure EXTi (ALARM) and saved in the internal memory of PSU. EN54C-LB4 EN54C-LB8
Hooks) g. Request the “Event Hooks” Early Access Feature by checking the box h. After the features are selected click the Save button 3. An API Token is required. This will be needed later in the setup of the Postman collections. To get an API Token do: a. Login to you Okta Org as described above and select the Classic UI b. Click on .
