VLSI Digital Signal Processing

VLSI DesignEEC 116Lecture 1Bevan M. BaasThursday, October 1, 2020EEC 116, B. Baas1

Today Administrative items– Syllabus and course overview– Course objective and strategies My backgroundChapter 1Read Chapter 1Read "Cramming more components onto integratedcircuits," Gordon Moore, Electronics, April 19, 1965. Homework 1 posted on web page; due nextThursdayEEC 116, B. Baas2

Teaching Assistants Ziyuan Dong Zhangfan Zhao Contact information is on the course web pageEEC 116, B. Baas3

Course Workload 4 unit course Upper division This course requires significant effort and time– Circuits– Layout– Tools Magic Irsim (Design Compiler, Innovus)– Major design projectEEC 116, B. Baas4

Course Communication Email list– Urgent announcements Web page– Primary source of course information Office hours– Tue 4:30 after lecture– Th 4:30 after lecture– Tentatively: Mon 2-3pm Please see me (or TA) in person with questions ratherthan emailEEC 116, B. Baas5

Lectures Ask questions at any time– Please raise your hand or in zoom speak out Be respectful of others– Hold conversations outside of class– Silence phones– Sit in the back if you come in late or need to leave earlyEEC 116, B. Baas6

My Teaching Philosophy Primary goal (mine and yours):Learn VLSI design well Achieve this through:–––––Reading textbookLecturesSolving problems on paperSolving problems in labDiscussions with other students, TA, myself Come to office hoursEEC 116, B. Baas7

My Grading Philosophy Grading serves two main purposes:– 1. Motivate you to do the work required to learn– 2. Give others an indication of how well youknow the material Requires honest work and fair gradingEEC 116, B. Baas8

Letter Grade Assignments I assign a letter grade only for the final course grade You can see score statistics for each graded item on Canvas I look at the final exams and course record of the class andassign two key dividing points: the A/A and D /C- boundaries,and assign course grades from there using equally-sizedintervals– No required numbers of any particularletter grades– Absolute scores are not important; theboundaries shift according to thedifficulty of the exams in any quarter– In fact, easy exams cause largegrade drops for small errors– Ignore any letter gradesFyou might see on canvasD /C-A/A D-D C-A A 9EEC 116, B. Baas(not actual grade data)

Working With Others Collaboration– Asking questions and explaining principles produces better workand dramatically increases learning– Working with others Do homework and prelabs with classmates nearby Ask each other questions, help each other—regarding principles, andgeneral approaches to solving only– See Course Collaboration Policy on web page Final Project: done individually– Groups of 2 Dishonesty– Copying produces similar work, stunts learning, is not fair tohonest students, and is not allowed in this courseEEC 116, B. Baas Students engaged in dishonest work will be referred to Student JudicialAffairs I will try to keep in-class exams honest Steps will be taken to keep out of class work honest10

Penalties for Violating the Policy onStudent Conduct and Discipline Penalties– Minimum penalty: meetings with SJA officer,zero grade on work, record with SJA– Permanent F grade on your transcript, no credit forthe class– One to three quarter suspension from the university– Permanent dismissal from all ten campuses of theUniversity of California. Permanent notation onyour transcript.EEC 116, B. Baas11

Penalties for Violating the Policy onStudent Conduct and Discipline Several perspectives– Personal– ECE and UCDobvious reasons(especially for those inclined to share workwith someone doing poorly in class)Cheating harms our major and university’sreputation among employers who interviewour graduates. In summary: The purpose of the penalties and thisdiscussion is so that no one will get the penalty!!!Don’t do anything that violates the Policy on StudentConduct!EEC 116, B. Baas12

Penalties for Violating the Policy onStudent Conduct and Discipline Typical scenario:– Someone shares code/design with another– They get caught– The “Copier” feels terrible guilt for causing a friendto get a zero– The “Sharer” deeply regrets sharing resulting in azero when he/she should have had a full scoreEEC 116, B. Baas13

Exam and Quiz Regrades Some number of exams and quizzes will bescanned before being returned Key take-away messages:– Do not change anything on your work if yourequest a regrade– One student did last year and got in big BIGtrouble!!!EEC 116, B. Baas14

Cheating Websiteschegg, coursehero, etc. The university has recently taken a very strong standagainst paying for work (2-quarter suspension for firstoffense last year) Key take-away messages:– Do not post assignments– Of course do not use any unpermitted outside material inwork you submit– Of course do not post solutions– Two students did last year and got caught!!!EEC 116, B. Baas15

Submitting Work Unless announced otherwise, materials due onlecture days are due at the beginning of class Submit work through canvas as instructed Homework drop box on the second floor of KemperEEC 116, B. Baas16

Course Web Pagehttp://www.ece.ucdavis.edu/ bbaas/116/EEC 116, B. Baas17

Colored pencils Buy colored pencils or pens whose colors matchmagic layout tool layer colors–––––greenbrown (orange next closest?)redbluepurple Used for “stick diagrams” Slightly transparent pencilsor pens work bestEEC 116, B. Baas18

Transistors(thousands)Number ofLogical CoresOriginal data up to the year 2010 collected and plotted by M. Horowitz, F. Labonte, O. Shacham, K. Olukotun, L. Hammond, and C. BattenNew plot and data collected for 2010-2015 by K. RuppNew data added by B. Baas B. Baas29

GC2: 16 nm, 23.6 billion transistorsEEC 116, B. Baas30

Processors Over TimeAcademicIndustry Number of processors on a single die vs. year Each processor capable of independent program execution31HotChips 2016

Processor Eras Transistor Era: the Intel 4004 wasthe first commercial single-chipmicroprocessor and it contained2300 hand-drawn transistors Single/Multi-Processor Era: focuson components of single processorsand multi-processors, whichgenerally scale well to only smallnumbers of processors 1000-Processor Era: focus onmaking systems scalable andworking with processors asbuilding blocks. The KiloCore designwould contain approximately 140,000 independent MIMD processors in 14 nmif its area were the same as the 12 nm 815 mm 2 Nvidia GV100 B. Baas32

MEMBACNvidia GV100KiloCoreIntel Broadwell-EXE7-8894not including 60 MB L3“processing block”Nearest neighbor centerto-center distance21x1x55xProcessors per mm 2in 14 nm CMOS0.381730.06 ALUDatapathExample operation:C A BEnergy dissipation:E K Capac Vdd2Processors drawn approximately to scale based on incomplete dataConsider for each processor tile: maximum wire length capacitance energyConsider for each processor tile: circuit overhead per operationNvidia GV100 12nm FF TSMC, 815 mm 2 28.5 mm 28.5 mm, 20.48MB RF, 10.75MB L1 Dcache, 6.144MB L284 Streaming Multiprocs (SM); each has L1 I , 128KB L1 D , 4 blocks (“processors”?) which each include:64KB RF, L0 I , 8 FP64, 16 INT, 16 FP32, 2 tensor cores.84 SMs are approx. 80% area [Fig. 4]: 7.76 mm 2 each or 1.94 mm 2 each “processor” 2.64 mm 2 1.63mm x 1.63mm in 14nm[“Nvidia Tesla V100 GPU Architecture,” Nvidia, August 2017]KiloCore 232 µm 239 µm in 32 nm. 75 µm 77 µm in 14 nm [Holt].0.0058 mm 2, 173/mm 2Xeon Broadwell-EP 14nm 456 mm 2 and 7.2 B trans. for 24 cores. (But no 24-core sold; 22-core 55MB L3) [wikipedia]Xeon Broadwell-EX 14nm E7-8894 v4, 24 cores, 24x256KB L2, 60MB L3, 165W TDP, 88980.0588 um 2 bitcell, 11.6 Mb/mm 2 68.2% of area is cells [Natarajan, IEDM, 2014]Guess same 456mm 2 area. 456mm 2 – 60MB/(11.6/8) 414.6mm 2 17.3mm 2/core 4.16x4.16mm for 24 cores

Undergraduate Research Talk to me if you are interested! I will say that there is a very strong correlation withGPA and success in researchEEC 180A, B. Baas39

Future Applications Very limited power budgets Require significant digital signal processingEEC 116, B. Baas40

Some Points on CourseCoverage Study of CMOS fabrication technology only Focus on digital circuits rather than analog circuits– Due to tremendous simplifications in circuit design, layoutextraction, and simulation Emphasis on low-level design (full custom layout,circuits). EEC 180B is higher-level Emphasis on VLSI-specific issues Limited coverage of digital circuits such as what iscovered in 118EEC 116, B. Baas41

EEC 116 Outline IntroductionCost, yieldCMOS fabricationCMOS VLSI layoutInverter characteristicsMOS resistance, capacitanceSequential circuitsOptimizing performanceComplex combinational gatesEEC 116, B. Baas Logic circuit stylesWiresChip-level structuresChip-level issuesArray memoriesPackagingStandard cell P&R overview42

Chapter 1—Introduction History of computing What is inside a processor How they are designedEEC 116, B. Baas43

The First ComputerThe BabbageDifference Engine(1832)25,000 partscost: 17,470EEC 116, B. BaasSource: Digital Integrated Circuits, 2nd 44

ENIAC - The first electronic computer (1946)EEC 116, B. BaasSource: Digital Integrated Circuits, 2nd 45

How Large Are Transistors? If a human hair werethis large A transistor that wasstate of the artaround the year 2002would be this long EEC 116, B. BaasSource: Richard Spencer56

The First Transistor Fabricated at Bell Labs onDecember 16, 1947. Theinventors won the Nobelprize in physics in 1956 forthe invention.EEC 116, B. BaasSource: Richard Spencer57

The First Integrated Circuit This is the first IC madeby Jack Kilby of TexasInstruments. It was builtin 1958.EEC 116, B. BaasSource: Richard Spencer58

An Early “Planar” IC This is an early planar IC fromFairchild.EEC 116, B. BaasSource: Richard Spencer59

Intel 4004 Micro-Processor19711000 transistors1 MHz operationEEC 116, B. BaasSource: Digital Integrated Circuits, 2nd 60

Intel Pentium 4Microprocessor Introduced in2000– 42 milliontransistors– 0.18 µm CMOSSource: Intelhttp://www.intel.com/museum/online/hist micro/hof/EEC 116, B. Baas61

NvidiaKeplerGK110 7.1 Billiontransistors 2880 CUDAdatapathsSource: xxxxxxxEEC 116, B. Baas62

Silicon Silicon is the secondmost common element inthe Earth’s crust. Semiconductor-grade Siis 99.999999 % pure. Ingots like this oneweigh several hundredpounds and cost 16,000 The ingot will be slicedinto very thin wafers.EEC 116, B. Baas63

A Silicon Wafer This 8-inch wafercontains about 200Pentium II chips(1997). Each chip containsmore than 20million transistors. More than 1 billionmicroprocessorsare made eachyear.EEC 116, B. BaasSource: Richard Spencer64

A State-of-the-art Wafer 300 mmdiameterwaferEEC 116, B. BaasSource: IBM65

Wires Four levels of wiresshown here Designers specifyeach layer andconnections betweenlayersEEC 116, B. BaasSource: IBM66

Chip Wires Modern chips haveup to 13 layers ofwiresEEC 116, B. BaasSource: IBM67

Chip WiresEEC 116, B. BaasSource: IBM68

MemoryArray Human hair on a256 Kbit memorychipEEC 116, B. BaasSource: Helmut Föll69

MemoryArray Human hair on a4 Mbit memorychip Note DRAMtrench capacitorsEEC 116, B. BaasSource: Helmut Föll70

Memory Array Red blood cells on a1 Mbit memory chipEEC 116, B. BaasSource: Helmut Föll71

Transistor Layout Drawing a transistor is thiseasy!DRAINPMOS transistorSOURCEGATEGATENMOS transistorDRAINSOURCESource: Mike LaiEEC 116, B. Baas72

AND Gate Layout Here is an AND gate(with an invertedoutput, which iscalled a NAND)POWER SUPPLYINPUT1OUTPUTINPUT2GROUNDSource: Mike LaiEEC 116, B. Baas73

OR Gate Layout Here is an OR gate (with aninverted output, which iscalled a NOR)POWER SUPPLYINPUT1INPUT2OUTPUTGROUNDSource: Mike LaiEEC 116, B. Baas74

Full Adder Layout Here is a Full AdderSource: Mike LaiEEC 116, B. Baas75