PSoC 5: CY8C52 Family Datasheet Programmable

PRELIMINARYIn addition to the flexibility of the UDB array, PSoC also providesconfigurable digital blocks targeted at specific functions. For theCY8C52 family these blocks can include four 16-bit timers,counters, and PWM blocks; I2C slave, master, and multimasterand Full-Speed USB.For more details on the peripherals see the “ExamplePeripherals” section on page 32 of this data sheet. Forinformation on UDBs, DSI, and other digital blocks, see the“Digital Subsystem” section on page 32 of this data sheet.PSoC’s analog subsystem is the second half of its uniqueconfigurability. All analog performance is based on a highlyaccurate absolute voltage reference with less than 1% error overtemperature and voltage. The configurable analog subsystemincludes: Analog muxes Comparators Voltage references ADC DACAll GPIO pins can route analog signals into and out of the deviceusing the internal analog bus. This allows the device to interfaceup to 62 discrete analog signals.The CY8C52 family offers a SAR ADC. Featuring 12-bitconversions at up to 700 k samples per second, it also offers lownonlinearity and offset errors. It is well suited for a variety ofhigher speed analog applications.A high-speed voltage or current DAC supports 8-bit outputsignals at an update rate of 5.5 Msps in IDAC and 1 Msps inVDAC. It can be routed out of any GPIO pin. You can createhigher resolution voltage PWM DAC outputs using the UDBarray. This can be used to create a pulse width modulated (PWM)DAC of up to 10 bits, at up to 48 kHz. The digital DACs in eachUDB support PWM, PRS, or delta-sigma algorithms withprogrammable widths.In addition to the ADC and DAC, the analog subsystem providesmultiple comparators. See the “Analog Subsystem” section onpage 43 of this data sheet for more details.PSoC’s CPU subsystem is built around a 32-bit three-stagepipelined ARM Cortex-M3 processor running at up to 40 MHz.The Cortex-M3 includes a tightly integrated nested vectoredinterrupt controller (NVIC) and various debug and trace modules.The overall CPU subsystem includes a DMA controller, cache,and interrupt controller. The NVIC provides low latency, nestedinterrupts, and tail-chaining of interrupts and other features toincrease the efficiency of interrupt handling. The DMA controllerenables peripherals to exchange data without CPU involvement.This allows the CPU to run slower (saving power) or use thoseCPU cycles to improve the performance of firmware algorithms.The presence of cache improves the access speed ofinstructions by the CPU.PSoC’s nonvolatile subsystem consists of flash andbyte-writeable EEPROM. It provides up to 256 KB of on-chipflash. The CPU can reprogram individual blocks of flash,enabling boot loaders. A powerful and flexible protection modelDocument Number: 001-66236 Rev. *CPSoC 5: CY8C52 Family Datasheetsecures the user's sensitive information, allowing selectivememory block locking for read and write protection. Two KB ofbyte-writable EEPROM is available on-chip to store applicationdata.The three types of PSoC I/O are extremely flexible. All I/Os havemany drive modes that are set at POR. PSoC also provides upto four I/O voltage domains through the VDDIO pins. Every GPIOhas analog I/O, LCD drive, flexible interrupt generation, slew ratecontrol, and digital I/O capability. The SIOs on PSoC allow VOHto be set independently of VDDIO when used as outputs. WhenSIOs are in input mode they are high impedance. This is trueeven when the device is not powered or when the pin voltagegoes above the supply voltage. This makes the SIO ideally suitedfor use on an I2C bus where the PSoC may not be powered whenother devices on the bus are. The SIO pins also have highcurrent sink capability for applications such as LED drives. Theprogrammable input threshold feature of the SIO can be used tomake the SIO function as a general purpose analog comparator.For devices with Full-Speed USB, the USB physical interface isalso provided (USBIO). When not using USB these pins mayalso be used for limited digital functionality and deviceprogramming. All the features of the PSoC I/Os are covered indetail in the “I/O System and Routing” section on page 25 of thisdata sheet.The PSoC device incorporates flexible internal clock generators,designed for high stability and factory trimmed for high accuracy.The internal main oscillator (IMO) is the master clock base forthe system and has 5% accuracy at 3 MHz. The IMO can beconfigured to run from 3 MHz up to 24 MHz. Multiple clockderivatives can be generated from the main clock frequency tomeet application needs. The device provides a PLL to generatesystem clock frequencies up to 40 MHz from the IMO, externalcrystal, or external reference clock. It also contains a separate,very low-power internal low-speed oscillator (ILO) for the sleepand watchdog timers. A 32.768 kHz external watch crystal is alsosupported for use in RTC applications. The clocks, together withprogrammable clock dividers, provide the flexibility to integratemost timing requirements.The CY8C52 family supports a wide supply operating range from2.7 to 5.5 V. This allows operation from regulated supplies suchas 3.3 V 10% or 5.0 V 10%, or directly from a wide range ofbattery types.PSoC supports a wide range of low-power modes. These includea 0.15-µA hibernate mode with RAM retention and a 1-µA sleepmode.Power to all major functional blocks, including the programmabledigital and analog peripherals, can be controlled independentlyby firmware. This allows low-power background processingwhen some peripherals are not in use. This, in turn, provides atotal device current of only 6 mA when the CPU is running at6 MHz.The details of the PSoC power modes are covered in the “PowerSystem” section on page 21 of this data sheet.Page 4 of 94

PRELIMINARYPSoC 5: CY8C52 Family Datasheet2. PinoutsPSoC uses a SWD interface for programming, debug, and test.Using this standard interface enables the designer to debug orprogram the PSoC with a variety of hardware solutions fromCypress or third party vendors. The Cortex-M3 debug and tracemodules include FPB, DWT, and ITM. These modules havemany features to help solve difficult debug and trace problems.Details of the programming, test, and debugging interfaces arediscussed in the “Programming, Debug Interfaces, Resources”section on page 49 of this data sheet.The VDDIO pin that supplies a particular set of pins is indicatedby the black lines drawn on the pinout diagrams in Figure 2-1 andFigure 2-2. Using the VDDIO pins, a single PSoC can supportmultiple interface voltage levels, eliminating the need for off-chiplevel shifters. Each VDDIO may sink up to 20 mA total to itsassociated I/O pins, and each set of VDDIO associated pins maysink up to 20 mA.55545352585756P15[5] (GPOI)P15[4] (GPIO)VdddVssdVccdP0[7] (GPIO, IDAC2)P0[6] (GPIO, IDAC0)P0[5] (GPIO)P0[4] (GPIO, SAR0ref)Vddio05150Lines show Vddioto I/O supplyassociationQFN28293031323334MHz XTAL: Xi(IDAC1, GPIO) P3[0](IDAC3, GPIO) P3[1](Extref1, GPIO) P3[2](GPIO) P3[3](GPIO) P3[4](GPIO) P3[5](Top (GPIO) P1[6](GPIO) P1[7](SIO) P12[6](SIO) P12[7][2](USBIO, D , SWDIO) P15[6][2](USBIO, D-, SWDCK) P15[7]VdddVssdVccdMHz XTAL: Xo(GPIO) P2[6](GPIO) P2[7](SIO) P12[4](SIO) P12[5]RSVDRSVDRSVDRSVDVssdXRES(SWDIO, GPIO) P1[0](SWDCK, GPIO) P1[1](GPIO) P1[2](SWV, GPIO) P1[3](GPIO) P1[4](GPIO) P1[5]Vddio166656463626160596867P2[5] (GPIO)Vddio2P2[4] (GPIO)P2[3] (GPIO)P2[2] (GPIO)P2[1] (GPIO)P2[0] (GPIO)Figure 2-1. 68-pin QFN Part Pinout[1]494847464544434241403938373635P0[3] (GPIO, Extref0)P0[2] (GPIO)P0[1] (GPIO)P0[0] (GPIO)P12[3] (SIO)P12[2] (SIO)VssdVddaVssaVccaP15[3] (GPIO, kHz XTAL: Xi)P15[2] (GPIO, kHz XTAL: Xo)P12[1] (SIO)P12[0] (SIO)P3[7] (GPIO)P3[6] (GPIO)Vddio3Notes1. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected toground, it should be electrically floated and not connected to any other signal.2. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.Document Number: 001-66236 Rev. *CPage 5 of 94

PRELIMINARYPSoC 5: CY8C52 Family DatasheetTQFP7776P4[5] (GPIO)P4[4] (GPIO)P4[3] (GPIO)P4[2] (GPIO)P0[7] (GPIO, IDAC2)P0[6] (GPIO, IDAC0)P0[5] (GPIO)P0[4] (GPIO, SAR0ref)87868584838281807978908988P15[4] (GPIO)P6[3] (GPIO)P6[2] (GPIO)P6[1] (GPIO)P6[0] (GPIO)VdddVssdVccdP4[7] (GPIO)P4[6] (GPIO)9897969594939291Lines show Vddioto I/O 958575655Vddio0P0[3] (GPIO, Extref0)P0[2] (GPIO)P0[1] (GPIO)P0[0] (GPIO)P4[1] (GPIO)P4[0] (GPIO)P12[3] (SIO)P12[2] (SIO)VssdVddaVssaVccaNCNCNCNCNCNCP15[3] (GPIO, kHz XTAL: Xi)P15[2] (GPIO, kHz XTAL: Xo)P12[1] (SIO, I2C1: SDA)P12[0] (SIO, I2C1: SCL)P3[7] (GPIO)P3[6] (GPIO)[3](GPIO) P3[5]Vddio3363738394041424344454647484950(USBIO, D-, SWDCK) P15[7]VdddVssdVccdNCNCMHz XTAL: XoMHz XTAL: Xi(IDAC1, GPIO) P3[0](IDAC3, GPIO) P3[1](Extref1, GPIO) P3[2](GPIO) P3[3](GPIO) 141516171819202122232425Vddio1(GPIO) P1[6](GPIO) P1[7](SIO) P12[6](SIO) P12[7](GPIO) P5[4](GPIO) P5[5](GPIO) P5[6](GPIO) P5[7][3](USBIO, D , SWDIO) P15[6](GPIO) P2[5](GPIO) P2[6](GPIO) P2[7](I2C0: SCL, SIO) P12[4](I2C0: SDA, SIO) P12[5](GPIO) P6[4](GPIO) P6[5](GPIO) P6[6](GPIO) P6[7]RSVDRSVDRSVDRSVDVssdXRES(GPIO) P5[0](GPIO) P5[1](GPIO) P5[2](GPIO) P5[3](SWDIO, GPIO) P1[0](SWDCK, GPIO) P1[1](GPIO) P1[2](SWV, GPIO) P1[3](GPIO) P1[4](GPIO) P1[5]10099Vddio2P2[4] (GPIO)P2[3] (GPIO)P2[2] (GPIO)P2[1] (GPIO)P2[0] (GPIO)P15[5] (GPIO)Figure 2-2. 100-pin TQFP Part PinoutFigure 2-3 and Figure 2-4 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analogperformance on a 2-layer board. The two pins labeled Vddd must be connected together. The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure 2-3 and Power System onpage 21. The trace between the two Vccd pins should be as short as possible. The two pins labeled Vssd must be connected together.For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit BoardLayout Considerations for PSoC 3 and PSoC 5.Note3. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.Document Number: 001-66236 Rev. *CPage 6 of 94

PRELIMINARYPSoC 5: CY8C52 Family DatasheetFigure 2-3. Example Schematic for 100-pin TQFP Part with Power ConnectionsVdddC11 uFVdddVdddVssdVdddVssdVssdVddio0REF0, P0[3]P0[2]P0[1]P0[0]P4[1]P4[0]SIO, P12[3]SIO, P12[2]VssdVddaVssaVccaNCNCNCNCNCNCkHzXin, P15[3]kHzXout, P15[2]SIO, P12[1]SIO, P12[0]P3[7]P3[6]Vddio1P1[6]P1[7]P12[6], SIOP12[7], SIOP5[4]P5[5]P5[6]P5[7]USB D , P15[6]USB D-, P15[7]VdddVssdVccdNCNCMHzXoutMHzXinP3[0], IDAC1P3[1], IDAC3P3[2], REF1P3[3]P3[4]P3[5]Vddio3P2[5]P2[6]P2[7]P12[4], SIOP12[5], 0]P5[1]P5[2]P5[3]P1[0], SWDIOP1[1], SWDCKP1[2]P1[3], 3626160595857565554535251C80.1 uFC171 uFVssdVssaVssdVddaVssdVddaVssaVccaC91 uFC100.1 uFVssaVdddVdddVccdC110.1 uFC120.1 [6]P4[5]P4[4]P4[3]P4[2]IDAC2, P0[7]IDAC0, P0[6]P0[5]SAR0ref, P0[4]VssdVssdC20.1 776C60.1 1 uFC160.1 uFVssdVssdNote The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, asshown in Figure 2-4.Document Number: 001-66236 Rev. *CPage 7 of 94

PRELIMINARYPSoC 5: CY8C52 Family DatasheetFigure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog PerformanceVssaVdddVssdPlane3. Pin DescriptionsIDAC0. Low resistance output pin for high IDAC.VssdVddaVssaPlaneof from a VDDIO. Pins are Do Not Use (DNU) on devices withoutUSB.SAR0ref. External reference for SAR ADC.USBIO, D-. Provides D- connection directly to a USB 2.0 bus.May be used as a digital I/O pin; it is powered from VDDD insteadof from a VDDIO. Pins are Do Not Use (DNU) on devices withoutUSB.GPIO. General purpose I/O pin provides interfaces to the CPU,digital peripherals, analog peripherals, interrupts, LCD segmentdrive, and CapSense.VCCA. Output of analog core regulator and input to analog core.Requires a 1 µF capacitor to VSSA. Regulator output not forexternal use.kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.VCCD. Output of digital core regulator and input to digital core.The two VCCD pins must be shorted together, with the tracebetween them as short as possible, and a 1-µF capacitor toVSSD; see Power System on page 21. Regulator output not forexternal use.Extref0, Extref1. External reference input to the analog system.MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillatorpin. If a crystal is not used, then Xi must be shorted to groundand Xo must be left floating.SIO. Special I/O provides interfaces to the CPU, digitalperipherals and interrupts with a programmable high thresholdvoltage, analog comparator, high sink current, and highimpedance state when the device is unpowered.SWDCK. Serial wire debug clock programming and debug portconnection. When programming and debugging using SWD isdone over USBIOs, the SWDCK pin of port P1[1] is not availablefor use as a general purpose I/O and should be externally pulleddown using a resistor of less than 100 K SWDIO. Serial wire debug Input and output programming anddebug port connection.SWV. Single wire viewer output.USBIO, D . Provides D connection directly to a USB 2.0 bus.May be used as a digital I/O pin; it is powered from VDDD insteadVDDA. Supply for all analog peripherals and analog coreregulator. VDDA must be the highest voltage present on thedevice. All other supply pins must be less than or equal toVDDA.[4]VDDD. Supply for all digital peripherals and digital core regulator.VDDD must be less than or equal to VDDA.[4]VSSA. Ground for all analog peripherals.VSSD. Ground for all digital logic and I/O pins.VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. EachVDDIO must be tied to a valid operating voltage (2.7 V to 5.5 V),and must be less than or equal to VDDA.XRES. External reset pin. Active low with internal pull-up.RSVD. Reserved pins.Note4. VDDD and VDDA must be brought up in synchronization with each other, that is, at the same rates and levels. VDDA must be greater than or equal to all other supplies.Document Number: 001-66236 Rev. *CPage 8 of 94

PRELIMINARYPSoC 5: CY8C52 Family Datasheet4. CPU4.1 ARM Cortex-M3 CPUThe CY8C52 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined Harvardarchitecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handlingfeatures.Figure 4-1. ARM Cortex-M3 Block DiagramInterrupt InputsNestedVectoredInterruptController(NVIC)Flash Patchand Breakpoint(FPB)I- BusSWDD-BusInstrumentationTrace Module(ITM)S- BusDebug Block(SWD)Trace PortInterface Unit(TPIU)SWVCortex M3 WrapperC- BusAHB32 KBSRAMDataWatchpoint andTrace (DWT)Cortex M3 CPU CoreAHBBusMatrixBusMatrixCache256 KBFlashAHB32 KBSRAMBusMatrixAHB Bridge and Bus MatrixDMAPHUBAHB eripheralsThe Cortex-M3 CPU subsystem includes these features: Cache controller with 128 bytes of memory ARM Cortex-M3 CPU Peripheral HUB (PHUB) Programmable nested vectored interrupt controller (NVIC), DMA controllertightly integrated with the CPU core Full-featured debug and trace module, tightly integrated withthe CPU core Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KBof SRAMDocument Number: 001-66236 Rev. *C4.1.1 Cortex-M3 FeaturesThe Cortex-M3 CPU features include: 4-GB address space. Predefined address regions for code,data, and peripherals. Multiple buses for efficient andsimultaneous accesses of instructions, data, and peripherals.Page 9 of 94

PRELIMINARY The Thumb -2 instruction set, which offers ARM-levelperformance at Thumb-level code density. This includes 16-bitand 32-bit instructions. Advanced instructions include: Bit-field control Hardware multiply and divide Saturation If-Then Wait for events and interrupts Exclusive access and barrier Special register accessThe Cortex-M3 does not support ARM instructions.PSoC 5: CY8C52 Family Datasheet4.1.3 CPU RegistersThe Cortex-M3 CPU registers are listed in Table 4-2. RegistersR0-R15 are all 32 bits wide.Table 4-2. Cortex M3 CPU RegistersRegisterR0-R12General purpose registers R0-R12 have nospecial architecturally defined uses. Mostinstructions that specify a general purposeregister specify R0-R12. Low Registers: Registers R0-R7 areaccessible by all instructions that specify ageneral purpose register. High Registers: Registers R8-R12 areaccessible by all 32-bit instructions that specifya general purpose register; they are notaccessible by all 16-bit instructions.R13R13 is the stack pointer register. It is a bankedregister that switches between two 32-bit stackpointers: the main stack pointer (MSP) and theprocess stack pointer (PSP). The PSP is usedonly when the CPU operates at the user level inthread mode. The MSP is used in all otherprivilege levels and modes. Bits[0:1] of the SPare ignored and considered to be 0, so the SP isalways aligned to a word (4 byte) boundary.R14R14 is the link register (LR). The LR stores thereturn address when a subroutine is called.R15R15 is the program counter (PC). Bit 0 of the PCis ignored and considered to be 0, soinstructions are always aligned to a half word (2byte) boundary.xPSRThe program status registers are divided intothree status registers, which are accessed eithertogether or separately: Application program status register (APSR)holds program execution status bits such aszero, carry, negative, in bits[27:31]. Interrupt program status register (IPSR) holdsthe current exception number in bits[0:8]. Execution program status register (EPSR)holds control bits for interrupt continuable andIF-THEN instructions

PSoC 5: CY8C52 Family Datasheet Document Number: 001-66236 Rev. *C Page 4 of 94 In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C52 family these blocks can include four 16-bit timers, cou