EE501 Lab 6 Layout And Post-layout Simulation
EE501 Lab 6 Layout and Post-layout SimulationReport due: Oct. 30, 2014Objective:1. Practice analog layout techniques2. Practice post-layout simulationTasks:1.Layout the two stage amplifier designed in Lab 4(As shown in Fig 1) Common centroid layout of the first-stage is highly recommended. Only 6 pins are allowed. An example is shown below.(Input pins: Vin , Vin-; Output pin: Vout; Current reference: Ib; Supply: avdd, avss)Suggestions for layout:a. Use large metal for vdd and vss connections for the purpose of currentcapability and noise.b. Make more substrate and well connection (to Vss and Vdd) instead of only afew contacts.c. Use common centroid layout for all pairs such as 1) input pairs 2) current mirrorload of the first stage.d. Use inter-digitized method for biasing transistors.e. N2 and N5 should be matched (in proportion). N4 and N5 also should bematched in proportion in layout (inter-digitized). In addition, N2 and N3 (N4and N5) should be matched.Fig 1 Two stage amplifier
2.DRC, LVS, and Extract using Diva (Appendix B).Refer “CapacitorLayout” on the webpage for capacitor layoutPost-Layout SimulationShow the comparisons between simulation results with schematic andpost-layout simulation results (DC gain, frequency response and phasemargin, etc.).Note: the layout view should be in the same cell as the amplifier symbolview.Report:1. Screen shot of the final layout with PIN name clearly shown2. Screen shot of DRC and LVS results3. Summarize the schematic- and post-layout simulation results in a Table andcompare them (DC current, DC gain, UGF, -3dB bandwidth Phase margin, and etc.)Appendix A:1. Basic layout asic Layout Techniques%5B1%5D.pdf2. Layout examples:NMOS: 2*2PMOS: 2*2
3. Capacitor Layouthttp://home.engineering.iastate.edu/ hmeng/EE501lab/TAHelp/Layout Capacitor.pdf4. Technology files (AMI0.6um or ON 0.5um)a. Layer maps (SCN3ME and SCN3ME s/lm-scmos gn/ee141 E: Scalable CMOS N-well, 3 metal, non-silicided, high resistancelayers available. Add a second poly-silicon layer (poly2) as the upper electrodeof a poly capacitor.SCN3ME SUBM: Uses revised layout rules for better fit to sub-micronprocesses (see MOSIS Scalable CMOS (SCMOS) Design Rules, Section 2.4).b. Design rule (MOSIS Scalable CMOS c. MOSIS Scalable CMOS (SCMOS) Design Rules, Section 2.4. Sheet resistance,contact resistance, and capacitance osis/swp/params/ami-c5/v23r-params.txt
Appendix B:1. Add corresponding pinsa. Open “Display” in “Options” (“e” for shortcut) as shown below. Choose “PinNames”b. Choose “Create”-“Pin ”. Fill the “Terminal name” and be careful of the “I/OType”. Then draw a rectangle and change the layer type to the correspondingone. Change the layer type of words to “text”.2. Find the capacitor’s value.According to the reference, draw the capacitance. Click “Verify”-“Extract”-“OK”
Open the “extracted” view in Library Manager and you can find the capacitancevalue.3. DRC & LVSa. To run DRC, click “Verify”-“DRC”Click “OK” and your results will be shown in the “CIW”.b. To run LVS, first run “Extract” in “Verify” and then run “LVS”.
Click “Run” and it will take some time to show whether your schematic andlayout are matched.4. Post-layout Simulationa. Open the test-bench used for originally schematic simulations.b. In the “Analog Design Environment”, select “Setup”-“Environment ”. Add“extracted” as shown in the “Switch View List”.c. Click “OK” and do your simulation.d. Whenever simulation with schematic is need, delete .edu/vlsi/index.php/Simulations using ADE %28G%29XL
Oct 30, 2014 · EE501 Lab 6 Layout and Post-layout Simulation Report due: Oct. 30, 2014 Objective: 1. Practice analog layout techniques 2. Practice post-layout simulation Tasks: 1. Layout the two stage amplifier designed in Lab 4(As shown in Fig 1) Common centroid layout of the fi
All 13 Layouts use White Daisy CS for bases, so you will need 26 sheets for your layouts. Whisper CS #3 4 x 12 Layout B 4 x 12 Layout B 4 x 12 Layout C Whisper CS #4 4 x 12 Layout C 4 x 12 Layout C 4 x 12 Layout C Saffron Letter B&T #1 (letters facing sideways) 6 x 10 ½ Layout A 6 x 8 Layout A 6 x 4 Layout K 6 x 1 ½ Cricut
1. Creating layout with Virtuoso layout XL (VXL) We will be using PCELLs developed by NCSU to layout a 2 inputs nand gate, denoted as nand2. If you are not running CDS tools, do so according to Lab 1. First we need to create a layout view of our nand2. Go to the library manager and execute
Contents Chapter 1 Lab Algorithms, Errors, and Testing 1 Chapter 2 Lab Java Fundamentals 9 Chapter 3 Lab Selection Control Structures 21 Chapter 4 Lab Loops and Files 31 Chapter 5 Lab Methods 41 Chapter 6 Lab Classes and Objects 51 Chapter 7 Lab GUI Applications 61 Chapter 8 Lab Arrays 67 Chapter 9 Lab More Classes and Objects 75 Chapter 10 Lab Text Processing and Wrapper Classes 87
Biology Lab Notebook Table of Contents: 1. General Lab Template 2. Lab Report Grading Rubric 3. Sample Lab Report 4. Graphing Lab 5. Personal Experiment 6. Enzymes Lab 7. The Importance of Water 8. Cell Membranes - How Do Small Materials Enter Cells? 9. Osmosis - Elodea Lab 10. Respiration - Yeast Lab 11. Cell Division - Egg Lab 12.
process or functional layout and combination or group layout. Each kind of layouts is explained with respective advantages, disadvantages and application as under. 1. Fixed or Position Layout Fixed or position layout is also known as project layout. A typical fixed layout is shown in Fig.1.1. In this
1 Layout Tutorial This tutorial will explain how create a layout template, send views to a layout page, then save the document in PDF format. In this tutorial you will learn about: Creating a Layout Template Creating a Border and Title Block Sending Floor Plan Views to Layout Sending Elevation Views to Layout
Creating a Border and Title Block 3 To use a custom layout template 1. Select File Open Layout and browse to your custom layout template file. 2. When the new layout file is open, select File Save As.In the Save Plan File dialog: Click the Save in drop-down and browse to the folder where the plan that you intend to send views to the layout is saved.
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