Spread-Spectrum Clock Generation In Spartan-6 FPGAs

Soft Spread SpectrumX-Ref Target - Figure 7SSTOPDCM CLKGENPLL BASEBUFGCLOCKPROGCLKRSTRESETPROGENPROGDATASS CLKCLKINRSTPROGCLKPROGCLKDFS LOCKED LKFX MULTIPLY IN(7)CLKFX DIVIDE FBINCLKFX180CLK 7XBUFGCLKOUT0CLKFBOUTLOCKEDFREEZEDCM PROGDONECLKFX MULTIPLY(7)CLKFX DIVIDE(2)SPREAD SPECTRUM[VIDEO LINK M1/VIDEO LINK M2]DIVCLK DIVIDE(1)CLKFBOUT MULT(2)CLK FEEDBACK(CLKFBOUT)DCM CLKGEN SOFTSPREADx1065 07 022810Figure 7:Reference Design Clock StructureTo create the modulation, the reference design programs different CLKFX frequencies using asmall state machine contained within SSTOP. When the modulation is at the lowest frequencywithin the expected modulation, CLKFX is increased. Similarly, when the modulation is at thepeak of the modulation range, CLKFX is decreased.As an example, if the input frequency is 85 MHz with the DCM CLKGEN primitive programmedusing CLKFX MULTIPLY 7 and CLKFX DIVIDE 2, then CLKFX is set to 297.5 MHz. Tospeed up, CLKFX is reprogrammed to CLKFX MULTIPLY 7 and CLKFX DIVIDE 1. An85 MHz input clock implies a CLKFX frequency of 595 MHz. However, this frequency can neveractually be reached. Because the frequencies are slowly changed, SSTOP is able to monitorthe frequencies. As the modulation reaches the fastest frequency within the expected range,SSTOP sets the direction of the modulation by programming a slower CLKFX frequency. Toslow down the modulated frequency, the DCM CLKGEN primitive is reprogrammed toCLKFX MULTIPLY 7 and CLKFX DIVIDE 3. Again, SSTOP reprograms CLKFX when thefrequency has slowed down to the frequency defined by SSTOP. Because the reference designis targeting video applications, both M and D must be taken into consideration. The referencedesign uses M 7 and D 2.To control how quickly the DCM CLKGEN primitive frequencies change after beingprogrammed, place the SPREAD SPECTRUM attribute into one of three modes for softspread-spectrum clocking: VIDEO LINK M0, VIDEO LINK M1, or VIDEO LINK M2. Whenthe SPREAD SPECTRUM attribute is set to VIDEO LINK M0, CLKFX changes thefrequencies at the fastest rate. Modulation frequencies are the fastest when usingVIDEO LINK M0 as shown in Figure 8.XAPP1065 (v1.0) March 22, 2010www.xilinx.com8

Soft Spread SpectrumFrequencyX-Ref Target - Figure 8VIDEO LINK M2FrequencyTimeVIDEO LINK M1FrequencyTimeVIDEO LINK M0TimeX1065 08 020910Figure 8:SPREAD SPECTRUM Effect on Modulation FrequencyExample: LVDS for Video Clock Frequencies of 30 To 105 MHzFocusing on a typical LVDS implementation commonly found in video designs, the SOFT SSstate machine is contained in the reference design. The reference design supports typicalvideo applications requiring 7:1 serialization using the DCM CLKGEN primitive with acascaded PLL (Figure 9). The DCM CLKGEN primitive generates the spread-spectrummodulation. The cascaded PLL provides the high-speed clock required for the BUFPLL as wellas providing additional filtering to reduce the cycle-to-cycle jitter.X-Ref Target - Figure 9BUFPLLDCM CLKGENPLL FXCLKINCLKOUT0CLKFX180CLKFBIN T4FREEZEDCM LK0CLK1IOCEDATA RATE OQ SDRCLKOUT5CLKFBOUTLOCKEDCLKFX MULTIPLY(7)CLKFX DIVIDE(2)SPREAD SPECTRUM[VIDEO LINK M0/VIDEO LINK M1/VIDEO LINK M2]DIVCLK DIVIDE(1)CLKFBOUT MULT(2)CLK FEEDBACK(CLKFBOUT)COMPENSATION(INTERNAL)x1065 09 031810Figure 9:Soft Spread-Spectrum Clocking Video Implementation (30 FIN 105 MHz) Support of OSERDES2XAPP1065 (v1.0) March 22, 2010www.xilinx.com9

Soft Spread SpectrumExample: LVDS for Video Clock Frequencies Beyond 105 MHzAs long as the pixel clock frequencies can be supported, the solution shown in Figure 9 works.However, it is limited by the maximum frequency for CLKFX and CLKOUT FREQ FX. As thepixel clock frequencies increase beyond 105 MHz, a higher divide setting must be used (shownin Figure 10). To compensate for the higher divide settings, the following changes are made inxapp ss m7d4.v and dcm clkgen softspread m7d4.v. Set .CLKFX DIVIDE(4) for DCM CLKGEN in dcm clkgen softspread m7d4.v Set .SPREADSPECTRUM VIDEO LINK M1 for DCM CLKGEN indcm clkgen softspread m7d4.v Set .CLKFX DIVIDE IN(4) for SSTOP in dcm clkgen softspread m7d4.v Set .CLKFBOUT MULT(4) for PLL BASE in xapp ss m7d4.vX-Ref Target - Figure 10BUFPLLDCM CLKGENPLL TACLKINCLKOUT0CLKFX180CLKFBIN T4FREEZEDCM LK0CLK1IOCECLKOUT5CLKFBOUTLOCKEDCLKFX MULTIPLY 7DIVCLK DIVIDE 1CLKFX DIVIDE 4CLKFBOUT MULT 4SPREAD SPECTRUM [VIDEO LINK M0 / VIDEO LINK M1 / VIDEO LINK M2]x1065 10 031810Figure 10:Soft Spread-Spectrum Clocking Video Implementation (FIN 105 MHz) Support of OSERDES2Within dcm clkgen softspread m7d4.v, after changing CLKFX DIVIDE to four forDCM CLKGEN, the modulation rates slow down. To compensate, the SPREAD SPECTRUMattribute must be set to VIDEO LINK M1 to speed up the modulation rate back into anacceptable range.Another change to dcm clkgen softspread m7d4.v requires a change to the statemachine. It can be adjusted by changing the parameter CLKFX DIVIDE IN 4 within theinstantiation for SSTOP. By setting CLKFX DIVIDE IN in the instantiation, the state machineswithin sstop.v and sscontrol.v adjust to target the new target frequencies. The referencedesign uses CLKFX MULTIPLY 7 and CLKFX DIVIDE 5 when speeding up themodulation, and CLKFX MULTIPLY 7 and CLKFX DIVIDE 3 when slowing it down.In xapp ss m7d4.v, because DCM CLKGEN is sending a 183.75 MHz clock frequency, theoriginal PLL BASE settings for DIVCLK DIVIDE and CLKFBOUT MULT must be increased tomeet the minimum acceptable VCO range, FVCOMIN. Set CLKFBOUT MULT to 4 whileDIVCLK DIVIDE remains unchanged.XAPP1065 (v1.0) March 22, 2010www.xilinx.com10

Soft Spread SpectrumSpread for Soft Spread-Spectrum ClockingThe soft spread-spectrum state machine controls the range to be used based on a set ofregisters. The reference design is setup to create a down-spread spread-spectrum modulation.sstop.v controls the size of the modulation through a series of counters. The size of themodulation is controlled by the variables, SLOW and FAST. The reference design setsFAST 7 and SLOW 5 to create the down-spread modulation. To further increase thespread, SLOW can be decreased (down to 0). As the spread increases, the modulationfrequency reduces. Check the spread and modulation frequency for values other thanFAST 7 and SLOW 5.Figure 11 shows the reference design's spread as the input frequencies are varied. However,by ignoring modulation frequencies, Figure 9 shows how spread varies across pixel clockfrequencies.X-Ref Target - Figure 1114%12%10%8%Spread (%)6%4%2%0%0.0E 06 20.0E 0640.0E 0660.0E 0680.0E 06100.0E 06140.0E 06120.0E 06160.0E 06FIN (Hz)VIDEO LINK M0VIDEO LINK M1VIDEO LINK M2VIDEO LINK M1x1065 11 031910Figure 11:Reference Design Spread Across Video FrequenciesModulation Frequencies for the SOFT SS State MachineWhen working with a spread-spectrum clock source, the modulation frequency also influenceshow the system responds to the modulation of the spread-spectrum clock.To effectively reduce the emitted noise using a spread-spectrum solution, keep the modulationfrequency higher than 20 KHz. If the modulation frequency is too low, the spread-spectrummodulation is too slow to efficiently reduce EMI.When the modulation is too high and with a large spread, spread spectrum modulation couldappear as system noise or could start affecting the ability of other PLL components to follow themodulation. The modulation frequency should be less than 120 kHz.When using the SOFT SS state machine for video applications, a number of factors affect themodulation frequency. The SPREAD SPECTRUM modulation is not proportional to the inputfrequencies and requires more analysis to estimate the modulation frequencies. When usingthe SOFT SS state machine, modulation frequency becomes dependent on input frequency,CLKFX MULTIPLY, CLKFX DIVIDE, and the SPREAD SPECTRUM settings(VIDEO LINK M0, VIDEO LINK M1, VIDEO LINK M2). To simplify the potential variables,XAPP1065 (v1.0) March 22, 2010www.xilinx.com11

Spread Spectrum Receivinguse Equation 3 to approximate the modulation frequency (FMOD) when using the referencedesigns.F MOD F IN2 CONSTEquation 3The modulation settings are defined using the equations from Table 3 and bounding themodulation frequencies between 20 to 120 KHz. For low frequencies, the VIDEO LINK M0speeds up the modulation to keep the modulation frequency above the audio rangefrequencies. As the input frequency increases, VIDEO LINK M1 and VIDEO LINK M2 areused to slow down the modulation rates down below 120 KHz.Table 3: Modulation Frequency CalculationCLKFX MULTIPLYCLKFX DIVIDECONSTVIDEO LINK M07240.0 x 10–12VIDEO LINK M17215.0 x 10–12VIDEO LINK M2725.0 x 10–12VIDEO LINK M3742.5 x 10–12As the input frequency continues to increase to 105 MHz, DCM CLKGEN can no longersupport M 7 and D 2. As described in the Example: LVDS for Video Clock FrequenciesBeyond 105 MHz section, the reference design can be adjusted to supportCLKFX MULTIPLY(7) and CLKFX DIVIDE(4). The increase in CLKFX DIVIDE causes themodulation frequency to slow down. To compensate, use VIDEO LINK M1. The result is theM1 74FMOD in Figure 12.X-Ref Target - Figure 12140.0E 3120.0E 3100.0E 3FMOD (Hz)80.0E 360.0E 340.0E 320.0E 320.0E 640.0E 660.0E 680.0E 6100.0E 6120.0E 6FIN (Hz)VIDEO LINK M0 (M 7, D 2)VIDEO LINK M1 (M 7, D 2)VIDEO LINK M2 (M 7, D 2)VIDEO LINK M1 (M 7, D 4)x1065 12 022810Figure 12:SpreadSpectrumReceivingModulation Frequency vs FINThe PLL BASE or DCM SP primitives can be used for designs where a spread-spectrum clockis externally created.Because the DCM CLKGEN primitive is designed to filter out input clock noise and will distortreceived spread spectrum clocks, do not use the DCM CLKGEN primitive withSPREAD SPECTRUM NONE for spread-spectrum clock receiving.When using the DCM SP primitive to receive spread-spectrum clocks, it is important tounderstand how DCM SP will follow the modulation. To maintain phase and frequencyXAPP1065 (v1.0) March 22, 2010www.xilinx.com12

Spread Spectrum Receivingalignment, the DCM must follow the spread-spectrum clock source as shown in Figure 3. Tostop distortion on the original spread-spectrum source, DCM SP must be able to update thedeskewing and phase shifting often.A rough approximation can be made to estimate the limits of the modulation frequency for agiven frequency deviation. Beyond these limits, the DCM SP phase and frequency alignmentdeteriorates, reducing the receiver's skew margin.Video display receiver designs require both the DCM's delay-locked loop (DLL) and digitalfrequency synthesizer (DFS) to be used together. The DLL provides a digital deskew circuit.Equation 4 estimates the maximum modulation frequency (FMDLL expressed in Hz) for aspread-spectrum clock source at any given speed:DCM DELAY STEPEquation 4F MDLL ----224 S T INWhere:FMDLL Maximum modulation frequency in Hz that the DLL can followDCM DELAY STEP Finest delay resolution for the DCM(s)S Maximum spread or frequency deviationTIN Highest effective input clock period(s)24 Constant related to the update rate of the DLL frequency and phase adjustmentsThe DFS provides a flexible range of output frequencies based on the ratio of two user-definedintegers, a multiplier (CLKFX MULTIPLY) and a divisor (CLKFX DIVIDE). Equation 5estimates the maximum modulation frequency (FMDFS) for the DFS portion:DCM DELAY STEPF MDFS ----22 M D S T INEquation 5Where:FMDFS Maximum Modulation Frequency (Hz) DFS can followDCM DELAY STEP Finest delay resolution for the DCM(s)M CLKFX MULTIPLYD CLKFX DIVIDES Maximum spread or frequency deviationTIN Highest effective input clock period (s)2 Constant related to the update rate of DFS frequency and phase adjustmentsIn video applications that use both DFS and DLL, the maximum modulation frequency isdetermined by Equation 5.The DCM settings in this section were used during reference design testing. The parametersbest represent the 7:1 LVDS designs commonly found in displays: CLKFX MULTIPLY 7 andCLKFX DIVIDE 2. The DCM multiplies the clock to 3.5 times the original frequency. Usingthe DDR registers provides the full 7x data rate multiplication.When using spread spectrum clocks, use the fixed phase-shift mode. The variable phase-shiftmode disables the internal phase shift controls that update the phase shift with the frequencychanges. As a result, variable phase shifting should not be used with spread-spectrum inputclocks.XAPP1065 (v1.0) March 22, 2010www.xilinx.com13

Other Methods of Reducing EMIApplying the DCM settings from the 7:1 LVDS applications and using Equation 4 andEquation 5, limits for a 75 MHz spread-spectrum clock can be estimated with a 5% frequencydeviation.– 1223 10F MDLL ------------------ 108 KHz–9 224 0.05 ( 13.3 10 )– 1223 10F MDFS ---------------------------------- 92.9 KHz–9 2·2 7 2 0.05 ( 13.3 10 )Similarly, other display functions such as PPDS (10:1) or MINI-LVDS (8:1) use otherserialization. The ability of the DCM to track the spread-spectrum signal when multiplying is afunction of the multiply and divide values shown in Equation 5. For other display functions, suchas PPDS (M 5, D 1) or MINI-LVDS (M 4, D 1), the modulation frequency threshold ishigher than this 7x example.Other Methodsof ReducingEMIIn addition to supporting spread-spectrum clocks, Spartan-6 devices further reduce EMI bycontrolling the I/O type by selecting a specific SelectIO interface.Spartan-6 devices use LVCMOS and LVTTL I/Os with separate slew rate and drive strengthattributes. The drive strength can be reduced by lowering DRIVE. The slew rate can be reducedby changed SLEW to SLOW or QUIETIO, which further reduces the ringing.LCD modules are replacing the noisy LVTTL interfaces with differential interfaces likereduced-swing differential signaling (RSDS), MINI-LVDS, and even point-to-point differentialsignaling (PPDS). For the lowest EMI, Spartan-6 devices directly drive these differentialinterfaces.ReferenceDesignGeneral information about the reference design is shown in Table 4. The device utilization isshown in Table 5 for both the fixed spread-spectrum and soft spread-spectrum designs.The reference design files can be downloaded o?cid 143697Table 4: Reference Design ChecklistDeveloper NameXilinxTarget devicesSpartan-6 FPGAsSource code providedYesSource code formatVerilogDesign uses code/IP from an existing reference design,application note, 3rd party, Core GeneratorNoSimulationFunctional simulation performedRequires ISE softwarev12.1 or laterTiming simulation performedRequires ISE softwarev12.1 or laterTestbench used for functional and timing simulations providedNot applicableTestbench formatNot applicableSimulator software usedMXESPICE/IBIS simulationsNoImplementationXAPP1065 (v1.0) March 22, 2010www.xilinx.com14

ConclusionTable 4: Reference Design Checklist (Cont’d)Synthesis software tools usedXST 11.4Implementation software tools usedISE v11.4 softwareStatic timing analysis performedYesHardware verifiedYesHardware platform used for verificationSP601Table 5: Device UtilizationFixed Spread-SpectrumDesignSoft Spread-SpectrumDesignDCM CLKGENs used11BUFGs used02Slice LUT Flip-Flop pairs used099ConclusionThis application note gives examples of a typical spread-spectrum clock for video applicationsusing the Spartan-6 FPGA DCM CLKGEN primitive. DCM CLKGEN can be used for fixedspread-spectrum generation without any logic or in a soft spread-spectrum solution using astate machine. While the focus is specifically on LVDS display applications, applications withsimilar DCM usage can use similar spread-spectrum clocks.ReferenceThis document references the following Xilinx documentation:1. DS162, Spartan-6 FPGA Data Sheet2. UG382, Spartan-6 FPGA Clocking Resources User Guide3. XAPP469, Spread-Spectrum Clocking Reception for DisplaysThis application note only applies to Spartan-3E and Extended Spartan-3A family devices.Additional ResourcesThe following resources provided additional information useful for working with this applicationnote and reference design:4. http://www.fcc.gov, Federal Communications Commission5. http://www.ansi.org, American National Standards Institute6. r.html, International SpecialCommittee on Radio Interference, National Telecommunications and InformationAdministration7. http://www.national.com/appinfo/fpd/, Flat Panel Displays, National Semiconductor8. http://www.cclab.com/engnotes/eng290.htm, Engineering Note 290: Comparison of FCCLimits with CISPR Limits, Communication Certification LaboratoryRevisionHistoryThe following table shows the revision history for this document.DateVersion03/22/101.0XAPP1065 (v1.0) March 22, 2010Description of RevisionsInitial Xilinx release.www.xilinx.com15

Notice of DisclaimerNotice ofDisclaimerXilinx is disclosing this Application Note to you “AS-IS” with no warranty of any kind. This Application Noteis one possible implementation of this feature, application, or standard, and is subject to change withoutfurther notice from Xilinx. You are responsible for obtaining any rights you may require in connection withyour use or implementation of this Application Note. XILINX MAKES NO REPRESENTATIONS ORWARRANTIES, WHETHER EXPRESS

Spartan-6 FPGAs can generate a spread-spectrum clock source from a standard fixed-frequency oscillator. A Spartan-6 FPGA spread-spectrum clock source is generated by . machine to control the DCM_CLKGEN primitive and is focused on video applications (M 7, D 2).The attributes used