Instruction Set Architectures Part II: X86, RISC, And CISC
Instruction SetArchitecturesPart II: x86, RISC, andCISCReadings: 2.16-2.181
Which ISA runs in most cell phones andtablets?LetterAnswerAARMBx86CMIPSDVLIWECISC2
Was the full x86 instruction set we havetoday carefully planned out?LetterAnswerAYesBDI wish I could unlearn everything I knowabout x86. I feel unclean.Are you kidding? I’ve never seen a morepoorly planned ISA!*sob*EB, C, or DC3
Why did AMD and ARM (and MIPS)introduce 64-bit versions of their ISAs?LetterAnswerATo make the CPU smaller.BSupport more memoryCTo allow for more opcodesDB and CEA and B4
X86 Registers LetterAnswerAHave fixed functionsBAre generic, like in MIPSCWere originally (in 1978) 64 bits wideDAre implemented in main memoryENone of the above.5
Which of these is Amdahl’s law?LetterAnswerAStot 1/(S/x (1-x))BEP IC * CPI * CTCStot x/S (1-x)DStot 1/(x/S (1 – x))EE MC 26
End of Quiz7
Fair reading quiz questions?LetterAnswerAVery fairBSort of fairCNot very fairDTotally unfair8
How do you like the class so far overall?LetterAnswerAVery wellBGoodCOkDNot so muchENot at all9
How do you like using the clickers?LetterAnswerAVery wellBGoodCOkDNot so muchENot at all10
How does your experience with clickers in thisclass compare with your experience with themin other classes?LetterAnswerAThis class is betterBThe other classes have been betterCAbout the sameDI haven’t used clickers before.11
Have you been going to the discussionsection on Wednesday?LetterAnswerAYes, frequentlyBYes, once or twiceCNoDWe have a discussion section onWednesday?12
How is 141L going for you?LetterAnswerAGoing well. It’s fun!BGoing ok so far CNot going so wellDNot going well at allEI’m not in 141L13
Has this class been helpful for 141L?LetterAnswerAVery muchBSomeCNot reallyDNot at allEI’m not in 141L14
Start, Keep, Stop One the piece of paper write One thing I should start doing One thing I should keep doing One thing I should stop doing15
Goals for this Class Understand how CPUs run programs How do we express the computation the CPU?How does the CPU execute it?How does the CPU support other system components (e.g., the OS)?What techniques and technologies are involved and how do theywork?Understand why CPU performance varies How does CPU design impact performance?What trade-offs are involved in designing a CPU?How can we meaningfully measure and compare computerperformance?Understand why program performance varies How do program characteristics affect performance?How can we improve a programs performance by considering the CPUrunning it?How do other system components impact program performance?16
Goals Start learning to read x86 assembly Understand the design trade-offs involved incrafting an ISA Understand RISC and CISC MotivationsOrigins Very long instruction word (VLIW)Arm and Thumb Learn something about other current ISAs17
The Stack Frame A function’s “stack frame”holds It’s local variablesCopies of callee-saved registers (ifneeds to used them)Copies of caller-saved registers (whenit makes function calls).The frame pointer ( fp) points to the baseof the frame stack frame.The frame pointer in action.Adjust the stack pointer to allocate theframeSave the fp into the frame (it’scallee-saved)Copy from the sp to the fpUse the sp as needed for functioncalls.Refer to local variables relative to fp.Clean up when you’re done. Examplemain:addiu sp, sp,-32sw fp,24( sp)move fp, spsw 0,8( fp)li v0,1sw v0,12( fp)li v0,2sw v0,16( fp)lw 3,12( fp)lw v0,16( fp)addu v0, 3, v0sw v0,8( fp)lw v0,8( fp)move sp, fplw fp,24( sp)addiu sp, sp,32j ra18
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x86 Assembly21
x86 ISA Caveats x86 is a poorly-designed ISA It breaks almost every rule of good ISA design.There is nothing “regular” or predictable about its syntax.We don’t have time to learn how to write x86 with anykind of thoroughness.It is the most widely used ISA in the world today. It is the ISA you are most likely to see in the “real world”So it’s useful to study.Intel and AMD have managed to engineer (atconsiderable cost) their CPUs so that this uglinesshas relatively little impact on their processors’performance (more on this later)22
Some Differences Between MIPSand x86 x86 instructions can operate on memory orregisters or both x86 is a “two address” ISA Both arguments are sources.One is also the destination Between 1 and 15 bytes x86 has (lots of) special-purpose registers x86 has variable-length instructions23
x86-64 Assembly Syntax There are two syntaxes for x86 assemblyWe will use the “gnu assembler (gas) syntax”, aka“AT&T syntax”. This is different than “IntelSyntax”The most confusing difference: argument order AT&T/gas instruction src dst Intel instruction dst src Also, different instruction namesThere are some other differences too (seehttp://en.wikipedia.org/wiki/X86 assembly language#Syntax)If you go looking for help online, make sure it usesthe AT&T syntax (or at least be aware, if it doesn’t)!24
Registers8-bit16-bit32-bit 64-bitDescriptionNotes%AL%AX%EAX %RAXThe accumulator register%BL%BX%EBX %RBXThe base register%CL%CX %ECX %RCXThe counter%DL%DX %EDX %RDXThe data register%SPL%SP%ESP %RSPStack pointer%SBP%BP%EBP %RBPPoints to the base of the stack frame%RnB %RnW %RnD %Rn(n 8.15) General purpose registers%SIL%SI%ESI %RSI%DIL%DI%EDI %RDI Destination index for string operations%IP%EIP %RIP%FLAGSThese can be usedmore or lessinterchangeably, likethe registers inMIPS.Source index for string operationsInstruction PointerCondition codes%RAX (64 bits)Different names (e.g. %AX vs. %EAX vs. %RAX)refer to different parts of the same register%EAX (32 bits)%AX%AL 25
Instruction SuffixesInstruction SuffixesbbyteExample8 bitssshort16 bitswword16 bitsllong32 bitsqquad64 bitsaddbaddwaddladdq 4, %al 4, %ax 4, %eax%rcx, %rax26
Arguments/Addressing ModesTypeSyntaxMeaningExampleRegister% reg R[%reg]%RAXImmediate nnnconstant 42Label labellabel foobarDisplacementn(%reg)Mem[R[%reg] n]-42(%RAX)Base-Offset(%r1, %r2)Mem[R[%r1] %R[%r2]](%RAX,%AL)Scaled Offset(%r1, %r2, 2n)Mem[R[%r1] %R[%r2] * 2n](%RAX,%AL, 4)Scaled OffsetDisplacementk(%r1, %r2, 2n)Mem[R[%r1] %R[%r2] * 2n k]-4(%RAX,%AL, 2)27
movx86 does not have loads and stores. It hasmov.x86 InstructionRTLMIPS Equivalentmovb 0x05, %alR[al] 0x05ori t0, zero, 5movl -4(%ebp), %eaxR[eax] mem[R[ebp] -4]lw t0, -4( t1)movl %eax, -4(%ebp)mem[R[ebp] -4] R[eax]sw t0, -4( t1)mem[R[esp]] LC0la at, LC0sw at, 0( t0)movl %R0, -4(%R1,%R2,4)mem[R[%R1] R[%R2] *2n k] %R0slr at, t2, 2add at, at, t1sw t0, k( at)movl %R0, %R1R[%R1] R[%R0]ori t1, t0, zeromovl LC0, (%esp)28
ArithmeticInstructionRTLsubl 0x05, %eaxR[eax] R[eax] - 0x05subl %eax, -4(%ebp)mem[R[ebp] -4] mem[R[ebp] -4] - R[eax]subl -4(%ebp), %eaxR[eax] R[eax] - mem[R[ebp] -4]29
Stack ManagementInstructionMeaningx86 EquivalentMIPS equivalentpushl %eaxPush %eax onto thestacksubl 4, %esp;movl %eax, (%esp)subi sp, sp, 4sw t0, ( sp)popl %eaxPop %eax off the stackmovl (%esp), %eaxaddl 4, %esplw t0, ( sp)addi sp, sp, 4enter nSave stack pointer,allocate stack frame withn bytes for localspush %BPmov %SP, %BPsub n, %SPleaveRestore the callers stackpointer.movl %ebp, %esppop %ebpNone of these are pseudo instructions. They arereal instructions, just very complex.30
The Stack Frame A function’s “stackframe” holds It’s local variablesCopies of callee-saved registers (ifneeds to used them)Copies of caller-saved registers(when it makes function calls).The base pointer (%ebp) points to thebase of the frame stack frame.The base pointer in actionSave the old stack pointer.Align the stack pointerSave the old %ebpCopy from the %esp to the %ebpAllocate the frame by decrementing%espRefer to local variables relative to%ebpClean up when you’re done. movladdlmovlmovladdlpopllealret4(%esp), %ecx -16, %esp-4(%ecx)%ebp%esp, %ebp 16, %esp 0, -16(%ebp) 1, -12(%ebp) 2, -8(%ebp)-8(%ebp), %eax-12(%ebp), %eax%eax, -16(%ebp)-16(%ebp), %eax 16, %esp%ebp-4(%ecx), %esp31
Branches x86 uses condition codes for branches Condition codes are special-purpose bits thatmake up the flags registerArithmetic ops set the flags registercarry, parity, zero, sign, overflowInstructionMeaningcmpl %r1 %r2Set flags register for %r2 - %r1jmp location Jump to location je location Jump to location if the equal flag is setjg, jge, jl, jle, jnz, .jump if { , , , , ! 0,}32
Function CallsInstructionMeaningMIPScall label Push the return address onto the stack.Jump to the function.Homework?Pop the return address off the stack andjump to it.lw at, 0( sp)addi sp, sp, 4jr atretExample Return address goes on the stack(rather than a register as in MIPS)Arguments are passed on the stack(with push)Return value in %eax/%raxint foo(int x, int y);.d foo(a, b);pushq %R9pushq %R8call foomovq %eax, d33
x86 Assembly Resources These slides don’t cover everything you’ll needfor the homeworks on x86 assembly There’s too many ugly details to cover in class.But you may still encounter this code in real life (or on thehomeworks).You’ll need to do some looking of your own tofind the missing bits http://en.wikipedia.org/wiki/X86 architecturehttp://en.wikibooks.org/wiki/X86 Assembly/GAS SyntaxThe text book.Make sure you know if the resources you find areAT&T or Intel syntax! If there aren’t any “%”, it’s probably Intel, and the dstcomes first, rather than last.34
Which of the following is NOT correctabout these two ISAs?Selection StatementAx86 provides more instructions than MIPSBx86 usually needs more instructions to express a programCAn x86 instruction may access memory 3 timesDAn x86 instruction may be shorter than a MIPS instructionEAn x86 instruction may be longer than a MIPS instruction40
Other ISAs41
Designing an ISA to ImprovePerformance The PE tells us that we can improveperformance by reducing CPI. Can we get CPIto be less than 1? Yes, but it means we must execute more the oneinstruction per cycle.That means parallelism.How can we modify the ISA to support theexecution of multiple instructions each cycle?Later, we’ll look at modifying the processorimplementation to do the same thing withoutchanging the ISA.42
Very Long Instruction Word (VLIW) Put two (or more) instructions in one!Each sub-instruction is just like a normal instruction.The instructions execute at the same time.The processor can treat them as a single unit.Typical VLIW widths are 2-4 instructions, but somemachine have been much higher43
VLIW Example VLIW-MIPS Two MIPS instruction/VLIW instruction wordNot a real VLIW ISA.MIPS Codeorioriaddsub s2, s3, s2, s4, zero, 6 zero, 4 s2, s3 s2, s3Results: s2 10 s4 6Since the add and subexecute sequentially,the sub sees the newvalue for s2VLIW-MIPS Code ori s2, zero,6; ori s3, zero, 4 add s2, s2, s3; sub s4, s2, s3 Results: s2 10 s4 2Since the add and sub execute at the same time theyboth see the original value of s244
VLIW ChallengesVLIW has been around for a long time, but it’s not seenmainstream success.The main challenging is finding instructions to fill theVLIW slots.This is tortuous by by hand, and difficult for the compiler.VLIW-MIPS Code ori s2, zero,6; ori s3, zero, 4 add s2, s2, s3; nop sub s4, s2, s3; nop Results: s2 10 s4 6Now, the add and sub execute sequentially, butwe’ve wasted space and resources executing nops.45
VLIW’s History VLIW has been around for a long time However, the compiler problem (previous slide) isextremely hard. It’s the simplest way to get CPI 1.The ISA specifies the parallelism, the hardware can be very simpleWhen hardware was expensive, this seemed like a good idea.There end up being lots of noops in the long instruction words.Especially for “branchy” code (word processors, compilers, games,etc.)As a result, they have either 1. met with limited commercial success as general purpose machines(many companies) or,2. Become very complicated in new and interesting ways (forinstance, by providing special registers and instructions to eliminatebranches), or3. Both 1 and 2 -- See the Itanium from intel.46
Consider a 2-wide VLIW processor whose cycle time is 0.75x thatour baseline MIPS processors. For your code, the compiler endsup including one nop in ½ of the VLIW instruction words itgenerates. What’s the overall speedup of the VLIW processor vs.the baseline MIPS? Assume the number of non-nops doesn’tchange.SelectionVLIW CPITotal 1.547
VLIW’s Success Stories VLIW’s main success is in digital signalprocessing DSP applications mostly comprise very regular loops Constant loop bounds,Simple data access patternsNon-data-dependent computationSince these kinds of loops make up almost all (i.e., x isalmost 1.0) of the applications, Amdahl’s Laws sayswriting the code by hand is worthwhile.These applications are cost and power sensitive VLIW processors are simpleSimple means small, cheap, and efficient.I would not be surprised if there’s a VLIWprocessor in your cell phone.48
The ARM ISA The ARM ISA is in most oftoday’s cool mobile gadgetsIt got started at about the sametime as MIPS There are ARM chips availablefrom many vendors ARM Holdings. Inc. owns the ISA andlicenses it to other companies.It does not actually build chips. The vendors compete or otherfeatures (e.g., integrated graphics coprocessors)Drives down cost.There’s an ARM version ofyour text book.50
MIPS vs. ARM MIPS and ARM are both modern, relativelyclean ISAs ARM has Fixed-length instruction words (mostly. More inmoment)General-purpose registers (although only 16 ofthem)A similar set of instructions. But there are some differences.51
MIPS vs. ARM: Addressing Modes MIPS has 3 “addressing modes” Register -- s1Displacement -- 4( s1)Immediate -- 4 ARM has several moreARM InstructionMeaningLDR r0,[r1,#8]R[r0] Mem[R[r1] 8]Displacement (like mips)LDR r0,[r1,#8]!R[r1] R[r1] 8R[r0] Mem[R[r1]];Pre-incrementDisplacementLDR r0,[r1],#8R[r0] Mem[R[r1]];R[r1] R[r1] 8Post-incrementDisplacement52
MIPS vs. ARM: Shifts ARM likes to perform shift operations The second src operand of most instructionscan be shifted before use MIPS is less shift-happy.ARM InstructionMeaningAdd r1,r2,r3, LSL #4R[r1] R[r2] (R[r3] 4)Add r1,r2,r3, LSL r4R[r1] R[r2] (R[r3] R[r4])53
MIPS vs. ARM: Branches The the corresponding condition code isset, the instruction will execute.Otherwise, the instruction will be a nop.An instruction suffix specifies the conditioncodeThis eliminates many branches. if (x y)p q rCondition codes: negative, zero, carry,overflowInstruction set themInstruction can be made conditionalon one of the condition codes C CodeARM uses condition codes andpredication for branchesWe’ll see later on in this class thatbranches can slow down execution.xypqrxypqrisisisisisisisisisis s0 s1 s2 s3 s4r0r1r2r3r4MIPS Assemblybne s0, s1, fooadd s2, s3, s4foo:ARM AssemblyCMP r0,r1ADDEQ r2,r3,r454
ISA Alternatives 2-address code add r1, r2 means R[r1] R[r1] R[r2] few operands, so more bits for each.- lots of extra copy instructions1-address -- Accumulator architectures An “accumulator” is a source and destination for alloperationsadd r1 means acc acc R[r1]setacc r1 mean acc R[r1]getacc r1 mean R[r1] acc“0-address” code -- Stack-based architectures55
Stack-based ISA No register file. Instead, a stack holds valuesSome instruction manipulate the stack push -- add something to the stackpop -- remove the top item.swap -- swaps the top two itemsMost instructions operate on the contents of thestack Zero-operand instructions‘add’ is equivalent to t1 pop; t2 pop; push t1 t2; Elegant in theory Clumsy in hardware. How big is the stack? Java and Python “byte code” are stack-basedISAs Infinite stack, but it runs in a VM56
Stack Example: A X * Y - B * C Stack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPCPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopBase ptr (BP)0x1000BP MemoryX 4Y 8B 12C 16A57
Stack Example: A X * Y - B * C PCStack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopBase ptr (BP)0x1000CBP MemoryX 4Y 8B 12C 16A58
Stack Example: A X * Y - B * C PCStack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopBase ptr (BP)0x1000BC SPMemoryX 4Y 8B 12C 16A59
Stack Example: A X * Y - B * C PCStack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopBase ptr (BP)0x1000B*CBP MemoryX 4Y 8B 12C 16A60
Stack Example: A X * Y - B * C PCStack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopBase ptr (BP)0x1000YB*C BPMemoryX 4Y 8B 12C 16A61
Stack Example: A X * Y - B * C PCStack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopBase ptr (BP)0x1000YXB*C BPMemoryX 4Y 8B 12C 16A62
Stack Example: A X * Y - B * C PCStack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopBase ptr (BP)0x1000X*YB*C BPMemoryX 4Y 8B 12C 16A63
Stack Example: A X * Y - B * C PCStack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopX*Y-B*CBase ptr (BP)0x1000BP MemoryX 4Y 8B 12C 16A64
compute A X * Y - B * C PCStack-based ISAProcessor state: PC, “operand stack”, “Base ptr”Push -- Put something from memory onto the stackPop -- take something off the top of the stack , -, *, -- Replace top two values with the resultStore -- Store the top of the stackPush 12(BP)Push 8(BP)MultPush 0(BP)Push 4(BP)MultSubStore 16(BP)PopX*Y-B*CBase ptr (BP)0x1000BP MemoryX 4Y 8B 12C 16A65
RISC vs CISC66
In the Beginning. 1964 -- The first ISA appears on the IBM System 360In the “good” old days Initially, the focus was on usability by humans.Lots of “user-friendly” instructions (remember the x86 addressing modes).Memory was expensive, so code-density mattered.Many processors were microcoded -- each instruction actually triggered theexecution of a builtin function in the CPU. Simple hardware to executecomplex instructions (but CPIs are very, very high).so. Many, many different instructions, lots of bells and whistlesVariable-length instruction encoding to save space. their success had some downsides. ISAs evolved organically.They got messier, and more complex.67
Things Changed In the modern era Compilers write code, not humans.Memory is cheap. Code density is unimportant.Low CPI should be possible, but only for simpleinstructionsWe learned a lot about how to design ISAs, how to let themevolve gracefully, etc.So, architects started with with a clean slate.68
Reduced Instruction SetComputing (RISC) Simple, regular ISAs, mean simple CPUs, and simpleCPUs can go fast. Fast clocks.Low CPI.Simple ISAs will also mean more instruction (increasing IC), but thebenefits should outweigh this.Compiler-friendly, not user-friendly. Simple, regular ISAs, will be easy for compilers to useA few, simple, flexible, fast operations that compiler can combineeasily.Separate memory access and data manipulationInstructions access memory or manipulate register values. Notboth.“Load-store architectures” (like MIPS) 69
Instruction FormatsArithmetic: Register[rd] Register[rs] Register[rt]Register indirect jumps: PC PC Register[rs]Arithmetic: Register[rd] Register[rs] ImmBranches: If Register[rs] Register[rt], goto PC ImmediateMemory: Memory[Register[rs] Immediate] Register[rt]Register[rt] Memory[Register[rs] Immediate]Direct jumps: PC AddressSyscalls, break, etc.70
RISC Characteristics of MIPSAll instructions have 1 arithmetic op 1 memory access 2 register reads 1 register write 1 branchIt needs a small, fixed amount ofhardware.Instructions operate onmemory or registers notboth “Load/Store Architecture”Decoding is easy Uniform opcode locationUniform register locationAlways 4 bytes - the location ofthe next PC is to know. Uniform executionalgorithm FetchDecodeExecuteMemoryWrite BackCompiling is easy No complex instructions toreason aboutNo special registersThe HW is simple A skilled undergrad can build onein 10 weeks.33 instructions can run complexprograms.
CISC: x86 x86 is the prime example of CISC (therewere many others long ago) Many, many instruction formats. Variable length.Many complex rules about which register can beused when, and which addressing modes are validwhere.Very complex instructionsCombined memory/arithmetic.Special-purpose registers.Many, many instructions. Implementing x86 correctly is almostintractable74
Mostly RISC: ARM ARM is somewhere in between Four instruction formats. Fixed length.General purpose registers (except the condition codes)Moderately complex instructions, but they are still“regular” -- all instructions look more or less the same.ARM targeted embedded systems Code density is importantPerformance (and clock speed) is less criticalBoth of these argue for more complex instructions.But they can still be regular, easy to decode, and crafted tominimize hardware complexityImplementing an ARM processor is also tractablefor 141L, but it would be harder than MIPS75
RISCing the CISC Everyone believes that RISC ISAs are better for buildingfast processors.So, how do Intel and AMD build fast x86 processors? Despite using a CISC ISA, these processors are actually RISCThe precedingwas a dramatization. MIPSprocessorsinsideinstructionswere usedfor clarityintoandbecauseIInternally,they convertx86 instructionsMIPS-likemicro-ops(uops), and feedthemto a RISC-styleprocessorhadsomelaying around.uopsNo x86instruction were harmed in thex86 Codeori t0, t0, 5production of this slide.movb 0x05, %allw t0, -4( t1)movl -4(%ebp), %eaxsw t0, -4( t1)movl %eax, -4(%ebp)movl %R0, -4(%R1,%R2,4)slr at, t2, 2add at, at, t1sw t0, k( at)movl %R0, %R1ori t0, t0, zero76
VLIWing the CISC We can also get rid of x86 in software.Transmeta did this. They built a processor that was completely hidden behind a“soft” implementation of the x86 instruction set.Their system would translate x86 instruction into an internalVLIW instruction set and execute that instead.Originally, their aim was high performance.That turned out to be hard, so they focused low powerinstead.Transmeta eventually lost to Intel Once Intel decided it cared about power (in part becauseTransmeta made the case for low-power x86 processors),it started producing very efficient CPUs.77
The End
A ARM B x86 C MIPS D VLIW E CISC 2. Was the full x86 instruction set we have today carefully planned out? Letter Answer A Yes B I wish I could unlearn everything I know about x86. I feel unclean. C Are you kidding? I’ve never seen a more poorly planned ISA! D *sob* E B, C, or D 3.
Microservice-based architectures. Using containerisation in hybrid cloud architectures: Docker, Kubernetes, OpenShift: Designing microservice architectures. Managing microservice architectures. Continuous integration and continuous delivery (CI/CD) in containerised architectures. Cloud-native microservice architectures: serverless.
A Closer Look at Instruction Set Architectures 5.1 Introduction 293 5.2 Instruction Formats 293 5.2.1 Design Decisions for Instruction Sets 294 5.2.2 Little versus Big Endian 295 5.2.3 Internal Storage in the CPU: Stacks versus Registers 298 5.2.4 Number of Operands and Instruction Length
PLC-5 Instruction Set Alphabetical Listing PLC-5 Instruction Set Alphabetical Listing For this Instruction: See Page: For this Instruction: See Page: For this Instruction: See Page: For this Instruction: See Page: ABL 17-51 CMP 3-3 JSR 13-12 RES 2-25 ACB 17-71 COP 9-20 LBL 13-5 RET 13-12 AC
Part No : MS-HTB-4 Part No : MS-HTB-6M Part No : MS-HTB-6T Part No : MS-HTB-8 Part No : MS-TBE-2-7-E-FKIT Part No : MS-TC-308 Part No : PGI-63B-PG5000-LAO2 Part No : RTM4-F4-1 Part No : SS 316 Part No : SS 316L Part No : SS- 43 ZF2 Part No : SS-10M0-1-8 Part No : SS-10M0-6 Part No : SS-12?0-2-8 Part No : SS-12?0-7-8 Part No : SS-1210-3 Part No .
EE 109 Unit 8 –MIPS Instruction Set 8.2 INSTRUCTION SET OVERVIEW Architecting a vocabulary for the HW 8.3 Instruction Set Architecture (ISA) Defines the _ of the processor and memory system Instruction set is the _ the HW can understand and the SW is composed with 2 approaches
EE 109 Unit 13 –MIPS Instruction Set 2 INSTRUCTION SET OVERVIEW Architecting a vocabulary for the HW 3 Instruction Set Architecture (ISA) Defines the _ of the processor and memory system Instruction set is the _ the HW can understand and the SW is composed with 2 approaches
Instruction Set Preliminary 5-1 AVR Instruction Set This section describes all instructions for the 8-bit AVR in detail. For a specific device please refer to the specific Instruction Set Summary in the hardware description. Addressing modes are described in detail in the hardware description for each device. 8-Bit Instruction Set
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