AVR Data Book: 5. Instruction Set
Instruction SetAVR Instruction SetThis section describes all instructions for the 8-bit AVR in detail. For aspecific device please refer to the specific Instruction Set Summary in thehardware description.Addressing modes are described in detail in the hardware description foreach device.8-BitInstruction SetPreliminary5-1
Instruction Set Nomenclature:Status Register (SREG):SREG: Status registerC:Carry flag in status registerZ:Zero flag in status registerN:Negative flag in status registerV:Twos complement overflow indicatorS:N V, For signed testsH:Half Carry flag in the status registerT:Transfer bit used by BLD and BST instructionsI:Global interrupt enable/disable flagRegisters and operands:Rd:Destination (and source) register in the registerfileRr:Source register in the register fileR:Result after instruction is executedK:Constant literal or byte data (8 bit)k:Constant address data for program counterb:Bit in the register file or I/O register (3 bit)s:Bit in the status register (3 bit)X,Y,Z: Indirect address register (X R27:R26,Y R29:R28 and Z R31:R30)P:I/O port addressq:Displacement for direct addressing (6 bit)I/O RegistersRAMPX, RAMPY, RAMPZ: Registers concatenatedwith the X, Y and Z registers enabling indirectaddressing of the whole SRAM area on MCUs withmore than 64K bytes SRAM.Stack:STACK:Stack for return address and pushed registersSP:Stack Pointer to STACKOpcode:X:Don’t careFlags: :0:1:-:Flag affected by instructionFlag cleared by instructionFlag set by instructionFlag not affected by instructionConditional Branch onicCommentRd RrZ (N V) 0BRLT*Rd RrZ (N V) 1BRGE*SignedRd Rr(N V) 0BRGERd Rr(N V) 1BRLTSignedRd RrZ 1BREQRd RrZ 0BRNESignedRd RrZ (N V) 1BRGE*Rd RrZ (N V) 0BRLT*SignedRd Rr(N V) 1BRLTRd Rr(N V) 0BRGESignedRd RrC Z 0BRLO*Rd RrC Z 1BRSH*UnsignedRd RrC 0BRSH/BRCCRd RrC 1BRLO/BRCSUnsignedRd RrZ 1BREQRd RrZ 0BRNEUnsignedRd RrC Z 1BRSH*Rd RrC Z 0BRLO*UnsignedRd RrC 1BRLO/BRCSRd RrC 0BRSH/BRCCUnsignedCarryC 1BRCSNo carryC 0BRCCSimpleNegativeN 1BRMIPositiveN 0BRPLSimpleOverflowV 1BRVSNo overflowV 0BRVCSimpleZeroZ 1BREQNot zeroZ 0BRNESimple* Interchange Rd and Rr in the operation before the test. i.e. CP Rd,Rr CP Rr,Rd5-2Instruction Set Preliminary
Instruction SetComplete Instruction Set ClockNoteARITHMETIC AND LOGIC INSTRUCTIONSADDRd, RrAdd without CarryRd Rd RrZ,C,N,V,H1ADCRd, RrAdd with CarryRd Rd Rr CZ,C,N,V,H1ADIWRd, KAdd Immediate to WordRd 1:Rd Rd 1:Rd KZ,C,N,V2SUBRd, RrSubtract without CarryRd Rd - RrZ,C,N,V,H1SUBIRd, KSubtract ImmediateRd Rd - KZ,C,N,V,H1SBCRd, RrSubtract with CarryRd Rd - Rr - CZ,C,N,V,H1SBCIRd, KSubtract Immediate with CarryRd Rd - K - CZ,C,N,V,H1SBIWRd, KSubtract Immediate from WordRd 1:Rd Rd 1:Rd - KZ,C,N,V2ANDRd, RrLogical ANDRd Rd RrZ,N,V1ANDIRd, KLogical AND with ImmediateRd Rd KZ,N,V1ORRd, RrLogical ORRd Rd v RrZ,N,V1ORIRd, KLogical OR with ImmediateRd Rd v KZ,N,V1EORRd, RrExclusive ORRd Rd RrZ,N,V1COMRdOne’s ComplementRd FF - RdZ,C,N,V1NEGRdTwo’s ComplementRd 00 - RdZ,C,N,V,H1SBRRd,KSet Bit(s) in RegisterRd Rd v KZ,N,V1CBRRd,KClear Bit(s) in RegisterRd Rd ( FFh - K)Z,N,VINCRdIncrementRd Rd 1Z,N,V1DECRdDecrementRd Rd - 1Z,N,V1TSTRdTest for Zero or MinusRd Rd RdZ,N,V1CLRRdClear RegisterRd Rd RdZ,N,V1SERRdSet RegisterRd FFNone1MULRd,RrMultiply UnsignedR1, R0 Rd RrC2 )Not available in base-line microcontrollers1 (continued)Preliminary5-3
Complete Instruction Set Summary ags#ClockNoteBRANCH INSTRUCTIONSkRelative JumpPC PC k 1None2Indirect Jump to (Z)PC ZNone2JMPkJumpPC kNone3RCALLkRelative Call SubroutinePC PC k 1None3Indirect Call to (Z)PC ZNone3RJMPIJMPICALLCall SubroutinePC kNone4RETSubroutine ReturnPC STACKNone4RETIInterrupt ReturnPC STACKI4Rd,RrCompare, Skip if Equalif (Rd Rr) PC PC 2 or 3NoneCPRd,RrCompareZ,C,N,V,H,1CPCRd,RrCompare with CarryRd - Rr - CZ,C,N,V,H1CPIRd,KCompare with ImmediateRd - KZ,C,N,V,H1SBRCRr, bSkip if Bit in Register Clearedif (Rr(b) 0) PC PC 2 or 3NoneCALLCPSEkRd - Rr1/21/2SBRSRr, bSkip if Bit in Register Setif (Rr(b) 1) PC PC 2 or 3None1/2SBICP, bSkip if Bit in I/O Register Clearedif(I/O(P,b) 0) PC PC 2 or 3None2/3SBISP, bSkip if Bit in I/O Register SetIf(I/O(P,b) 1) PC PC 2 or 3None2/3BRBSs, kBranch if Status Flag Setif (SREG(s) 1) then PC PC k 1None1/2BRBCs, kBranch if Status Flag Clearedif (SREG(s) 0) then PC PC k 1None1/2BREQkBranch if Equalif (Z 1) then PC PC k 1None1/2BRNEkBranch if Not Equalif (Z 0) then PC PC k 1None1/2BRCSkBranch if Carry Setif (C 1) then PC PC k 1None1/2BRCCkBranch if Carry Clearedif (C 0) then PC PC k 1None1/2BRSHkBranch if Same or Higherif (C 0) then PC PC k 1None1/2BRLOkBranch if Lowerif (C 1) then PC PC k 1None1/2BRMIkBranch if Minusif (N 1) then PC PC k 1None1/2BRPLkBranch if Plusif (N 0) then PC PC k 1None1/2BRGEkBranch if Greater or Equal, Signedif (N V 0) then PC PC k 1None1/2BRLTkBranch if Less Than, Signedif (N V 1) then PC PC k 1None1/2BRHSkBranch if Half Carry Flag Setif (H 1) then PC PC k 1None1/2BRHCkBranch if Half Carry Flag Clearedif (H 0) then PC PC k 1None1/2BRTSkBranch if T Flag Setif (T 1) then PC PC k 1None1/2BRTCkBranch if T Flag Clearedif (T 0) then PC PC k 1None1/2BRVSkBranch if Overflow Flag is Setif (V 1) then PC PC k 1None1/2BRVCkBranch if Overflow Flag is Clearedif (V 0) then PC PC k 1None1/2None1/2None1/2BRIEkBranch if Interrupt Enabledif ( I 1) then PC PC k 1BRIDkBranch if Interrupt Disabledif ( I 0) then PC PC k 1(continued)5-4Instruction Set Preliminary
Instruction SetComplete Instruction Set Summary ags#ClockNoteDATA TRANSFER INSTRUCTIONSMOVRd, RrCopy RegisterRd RrNone1LDIRd, KLoad ImmediateRd KNone1LDSRd, kLoad Direct from SRAMRd (k)None3LDRd, XLoad IndirectRd (X)None2LDRd, X Load Indirect and Post-IncrementRd (X), X X 1None2LDRd, -XLoad Indirect and Pre-DecrementX X - 1, Rd (X)None2LDRd, YLoad IndirectRd (Y)None2LDRd, Y Load Indirect and Post-IncrementRd (Y), Y Y 1None2LDRd, -YLoad Indirect and Pre-DecrementY Y - 1, Rd (Y)None2LDDRd,Y qLoad Indirect with DisplacementRd (Y q)None2LDRd, ZLoad IndirectRd (Z)None2LDRd, Z Load Indirect and Post-IncrementRd (Z), Z Z 1None2LDRd, -ZLoad Indirect and Pre-DecrementZ Z - 1, Rd (Z)None2LDDRd, Z qLoad Indirect with DisplacementRd (Z q)None2STSk, RrStore Direct to SRAMRd (k)None3STX, RrStore Indirect(X) RrNone2STX , RrStore Indirect and Post-Increment(X) Rr, X X 1None2ST-X, RrStore Indirect and Pre-DecrementX X - 1, (X) RrNone2STY, RrStore Indirect(Y) RrNone2STY , RrStore Indirect and Post-Increment(Y) Rr, Y Y 1None2ST-Y, RrStore Indirect and Pre-DecrementY Y - 1, (Y) RrNone2STDY q,RrStore Indirect with Displacement(Y q) RrNone2STZ, RrStore Indirect(Z) RrNone2STZ , RrStore Indirect and Post-Increment(Z) Rr, Z Z 1None2ST-Z, RrStore Indirect and Pre-DecrementZ Z - 1, (Z) RrNone2STDZ q,RrStore Indirect with Displacement(Z q) RrNone2Load Program MemoryR0 (Z)None3LPMINRd, PIn PortRd PNone1OUTP, RrOut PortP RrNone1PUSHRrPush Register on StackSTACK RrNone2POPRdPop Register from StackRd STACKNone2(continued)Preliminary5-5
Complete Instruction Set Summary ags#ClockNoteBIT AND BIT-TEST INSTRUCTIONSLSLRdLogical Shift LeftRd(n 1) Rd(n),Rd(0) 0,C Rd(7)Z,C,N,V,H1LSRRdLogical Shift RightRd(n) Rd(n 1),Rd(7) 0,C Rd(0)Z,C,N,V1ROLRdRotate Left Through CarryRd(0) C,Rd(n 1) Rd(n),C Rd(7)Z,C,N,V,H1RORRdRotate Right Through CarryRd(7) C,Rd(n) Rd(n 1),C Rd(0)Z,C,N,V1ASRRdArithmetic Shift RightRd(n) Rd(n 1), n 0.6Z,C,N,V1SWAPRdSwap NibblesRd(3.0) Rd(7.4)None1BSETsFlag SetSREG(s) 1SREG(s)1BCLRsFlag ClearSREG(s) 0SREG(s)1SBIP, bSet Bit in I/O RegisterI/O(P, b) 1None2CBIP, bClear Bit in I/O RegisterI/O(P, b) 0None2BSTRr, bBit Store from Register to TT Rr(b)T1BLDRd, bBit load from T to RegisterRd(b) TNone1SECSet CarryC 1C1CLCClear CarryC 0C1SENSet Negative FlagN 1N1CLNClear Negative FlagN 0N1SEZSet Zero FlagZ 1Z1CLZClear Zero FlagZ 0Z1SEIGlobal Interrupt EnableI 1I1CLIGlobal Interrupt DisableI 0I1SESSet Signed Test FlagS 1S1CLSClear Signed Test FlagS 0S1SEVSet Two’s Complement OverflowV 1V1CLVClear Two’s Complement OverflowV 0V1SETSet T in SREGT 1T1CLTClear T in SREGT 0T1SEHSet Half Carry Flag in SREGH 1H1CLHClear Half Carry Flag in SREGH 0H1NOPNo OperationSLEEPSleep(see specific descr. for Sleep)None1WDRWatchdog Reset(see specific descr. for WDR)None15-6Instruction Set PreliminaryNone1
Instruction SetADC - Add with CarryDescription:Adds two registers and the contents of the C flag and places the result in the destination register Rd.(i)Operation:Rd Rd Rr C(i)Syntax:ADC Rd,RrOperands:0 d 31, 0 r 3116 bit Opcode:000111rdddddProgram Counter:PC PC 1rrrrStatus Register (SREG) Boolean Formulae:I-T-H S V N Z C H:Rd3 Rr3 Rr3 R3 R3 Rd3Set if there was a carry from bit 3; cleared otherwiseS:N V, For signed tests.V:Rd7 Rr7 R7 Rd7 Rr7 R7Set if two’s complement overflow resulted from the operation; cleared otherwise.N:R7Set if MSB of the result is set; cleared otherwise.Z:R7 R6 R5 R4 R3 R2 R1 R0Set if the result is 00; cleared otherwise.C:Rd7 Rr7 Rr7 R7 R7 Rd7Set if there was carry from the MSB of the result; cleared otherwise.R (Result) equals Rd after the operation.Example:addadc; Add R1:R0 to R3:R2r2,r0 ; Add low byter3,r1 ; Add with carry high byteWords: 1 (2 bytes)Cycles: 1Preliminary5-7
ADD - Add without CarryDescription:Adds two registers without the C flag and places the result in the destination register Rd.(i)Operation:Rd Rd Rr(i)Syntax:ADD Rd,RrOperands:0 d 31, 0 r 3116 bit Opcode:000011rdddddProgram Counter:PC PC 1rrrrStatus Register (SREG) and Boolean Formulae:I-T-H S V N Z C H:Rd3 Rr3 Rr3 R3 R3 Rd3Set if there was a carry from bit 3; cleared otherwiseS:N V, For signed tests.V:Rd7 Rr7 R7 Rd7 Rr7 R7Set if two’s complement overflow resulted from the operation; cleared otherwise.N:R7Set if MSB of the result is set; cleared otherwise.Z:R7 R6 R5 R4 R3 R2 R1 R0Set if the result is 00; cleared otherwise.C:Rd7 Rr7 Rr7 R7 R7 Rd7Set if there was carry from the MSB of the result; cleared otherwise.R (Result) equals Rd after the operation.Example:addaddr1,r2r28,r28; Add r2 to r1 (r1 r1 r2); Add r28 to itself (r28 r28 r28)Words: 1 (2 bytes)Cycles: 15-8Instruction Set Preliminary
Instruction SetADIW - Add Immediate to WordDescription:Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates on theupper four register pairs, and is well suited for operations on the pointer registers.(i)Operation:Rdh:Rdl Rdh:Rdl K(i)Syntax:ADIW Rdl,KOperands:dl {24,26,28,30}, 0 K 6316 bit Opcode:10010110KKddProgram Counter:PC PC 1KKKKStatus Register (SREG) and Boolean Formulae:I-T-H-S V N Z C S:N V, For signed tests.V:Rdh7 R15Set if two’s complement overflow resulted from the operation; cleared otherwise.N:R15Set if MSB of the result is set; cleared otherwise.Z:R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0Set if the result is 0000; cleared otherwise.C:R15 Rdh7Set if there was carry from the MSB of the result; cleared otherwise.R (Result) equals Rdh:Rdl after the operation (Rdh7-Rdh0 R15-R8, Rdl7-Rdl0 R7-R0).Example:adiwadiwr24,1r30,63; Add 1 to r25:r24; Add 63 to the Z pointer(r31:r30)Words: 1 (2 bytes)Cycles: 2Preliminary5-9
AND - Logical ANDDescription:Performs the logical AND between the contents of register Rd and register Rr and places the result in the destinationregister Rd.(i)Operation:Rd Rd Rr(i)Syntax:AND Rd,RrOperands:0 d 31, 0 r 3116 bit Opcode:001000rdddddProgram Counter:PC PC 1rrrrStatus Register (SREG) and Boolean Formulae:I-T-H-S V0N S:N V, For signed tests.V:0ClearedN:R7Set if MSB of the result is set; cleared otherwise.Z:R7 R6 R5 R4 R3 R2 R1 R0Set if the result is 00; cleared otherwise.Z C-R (Result) equals Rd after the operation.Example:andldiandr2,r3r16,1r2,r16; Bitwise and r2 and r3, result in r2; Set bitmask 0000 0001 in r16; Isolate bit 0 in r2Words: 1 (2 bytes)Cycles: 15-10Instruction Set Preliminary
Instruction SetANDI - Logical AND with ImmediateDescription:Performs the logical AND between the contents of register Rd and a constant and places the result in the destinationregister Rd.(i)Operation:Rd Rd K(i)Syntax:ANDI Rd,KOperands:16 d 31, 0 K 25516 bit Opcode:0111KKKKddddProgram Counter:PC PC 1KKKKStatus Register (SREG) and Boolean Formulae:I-T-H-S V0N S:N V, For signed tests.V:0ClearedN:R7Set if MSB of the result is set; cleared otherwise.Z:R7 R6 R5 R4 R3 R2 R1 R0Set if the result is 00; cleared otherwise.Z C-R (Result) equals Rd after the operation.Example:andiandiandir17, 0Fr18, 10r19, AA; Clear upper nibble of r17; Isolate bit 4 in r18; Clear odd bits of r19Words: 1 (2 bytes)Cycles: 1Preliminary5-11
ASR - Arithmetic Shift RightDescription:Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C flag of the SREG. Thisoperation effectively divides a twos complement value by two without changing its sign. The carry flag can be used toround the result.Operation:b7 - - - - - - - - - b0(i)(i)CSyntax:ASR RdOperands:0 d 3116 bit Opcode:1001010dddddProgram Counter:PC PC 10101Status Register (SREG) and Boolean Formulae:I-T-H-S V N Z C S:N V, For signed tests.V:N C (For N and C after the shift)Set if (N is set and C is clear) or (N is clear and C is set); Cleared otherwise (for values of N and C after theshift).N:R7Set if MSB of the result is set; cleared otherwise.Z:R7 R6 R5 R4 R3 R2 R1 R0Set if the result is 00; cleared otherwise.C:Rd0Set if, before the shift, the LSB of Rd was set; cleared otherwise.R (Result) equals Rd after the operation.Example:ldiasrldiasrr16, 10r16r17, FCr17;;;;Load decimal 16 into r16r16 r16 / 2Load -4 in r17r17 r17/2Words: 1 (2 bytes)Cycles: 15-12Instruction Set Preliminary
Instruction SetBCLR - Bit Clear in SREGDescription:Clears a single flag in SREG.(i)Operation:SREG(s) 0(i)Syntax:BCLR sOperands:0 s 716 bit Opcode:100101001sssProgram Counter:PC PC 11000Status Register (SREG) and Boolean Formulae:I T H S I:0 if s 7; Unchanged otherwise.T:0 if s 6; Unchanged otherwise.H:0 if s 5; Unchanged otherwise.S:0 if s 4; Unchanged otherwise.V:0 if s 3; Unchanged otherwise.N:0 if s 2; Unchanged otherwise.Z:0 if s 1; Unchanged otherwise.C:0 if s 0; Unchanged otherwise.V N Z C Example:bclrbclr07; Clear carry flag; Disable interruptsWords: 1 (2 bytes)Cycles: 1Preliminary5-13
BLD - Bit Load from the T Flag in SREG to a Bit in Register.Description:Copies the T flag in the SREG (status register) to bit b in register Rd.(i)Operation:Rd(b) T(i)Syntax:BLD Rd,bOperands:0 d 31, 0 b 716 bit Opcode:1111100dddddProgram Counter:PC PC 1XbbbStatus Register (SREG) and Boolean Formulae:I-T-H-S-V-N-Z-C-Example:bstbldr1,2r0,4; Copy bit; Store bit 2 of r1 in T flag; Load T flag into bit 4 of r0Words: 1 (2 bytes)Cycles: 15-14Instruction Set Preliminary
Instruction SetBRBC - Branch if Bit in SREG is ClearedDescription:Conditional relative branch. Tests a single bit in SREG and branches relatively to PC if the bit is cleared. This instructionbranches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and isrepresented in two’s complement form.(i)Operation:If SREG(s) 0 then PC PC k 1, else PC PC 1(i)Syntax:BRBC s,kOperands:0 s 7, -64 k 6316 bit Opcode:111101kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falseksssStatus Register (SREG) and Boolean r20,51,noteq; Compare r20 to the value 5; Branch if zero flag cleared; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is truePreliminary5-15
BRBS - Branch if Bit in SREG is SetDescription:Conditional relative branch. Tests a single bit in SREG and branches relatively to PC if the bit is set. This instructionbranches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and isrepresented in two’s complement form.(i)Operation:If SREG(s) 1 then PC PC k 1, else PC PC 1(i)Syntax:BRBS s,kOperands:0 s 7, -64 k 6316 bit Opcode:111100kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falseksssStatus Register (SREG) and Boolean pr0,36,bitset; Load T bit with bit 3 of r0; Branch T bit was set; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is true5-16Instruction Set Preliminary
Instruction SetBRCC - Branch if Carry ClearedDescription:Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is cleared. This instructionbranches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and isrepresented in two’s complement form. (Equivalent to instruction BRBC 0,k).(i)Operation:If C 0 then PC PC k 1, else PC PC 1(i)Syntax:BRCC kOperands:-64 k 6316 bit Opcode:111101kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek000Status Register (SREG) and Boolean opr22,r23nocarry; Add r23 to r22; Branch if carry cleared; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is truePreliminary5-17
BRCS - Branch if Carry SetDescription:Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is set. This instruction branchesrelatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and is representedin two’s complement form. (Equivalent to instruction BRBS 0,k).(i)Operation:If C 1 then PC PC k 1, else PC PC 1(i)Syntax:BRCS kOperands:-64 k 6316 bit Opcode:111100kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek000Status Register (SREG) and Boolean r26, 56carry; Compare r26 with 56; Branch if carry set; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is true5-18Instruction Set Preliminary
Instruction SetBREQ - Branch if EqualDescription:Conditional relative branch. Tests the Zero flag (Z) and branches relatively to PC if Z is set. If the instruction is executedimmediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the unsigned orsigned binary number represented in Rd was equal to the unsigned or signed binary number represented in Rr. Thisinstruction branches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset fromPC and is represented in two’s complement form. (Equivalent to instruction BRBS 1,k).(i)Operation:If Rd Rr (Z 1) then PC PC k 1, else PC PC 1(i)Syntax:BREQ kOperands:-64 k 6316 bit Opcode:111100kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek001Status Register (SREG) and Boolean 1,r0equal; Compare registers r1 and r0; Branch if registers equal; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is truePreliminary5-19
BRGE - Branch if Greater or Equal (Signed)Description:Conditional relative branch. Tests the Signed flag (S) and branches relatively to PC if S is cleared. If the instruction isexecuted immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the signedbinary number represented in Rd was greater than or equal to the signed binary number represented in Rr. Thisinstruction branches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset fromPC and is represented in two’s complement form. (Equivalent to instruction BRBC 4,k).(i)Operation:If Rd Rr (N V 0) then PC PC k 1, else PC PC 1(i)Syntax:BRGE kOperands:-64 k 6316 bit Opcode:111101kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek100Status Register (SREG) and Boolean pr11,r12greateq; Compare registers r11 and r12; Branch if r11 r12 (signed); Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is true5-20Instruction Set Preliminary
Instruction SetBRHC - Branch if Half Carry Flag is ClearedDescription:Conditional relative branch. Tests the Half Carry flag (H) and branches relatively to PC if H is cleared. This instructionbranches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and isrepresented in two’s complement form. (Equivalent to instruction BRBC 5,k).(i)Operation:If H 0 then PC PC k 1, else PC PC 1(i)Syntax:BRHC kOperands:-64 k 6316 bit Opcode:111101kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek101Status Register (SREG) and Boolean Formulae:I-T-H-S-V-N-Z-C-Example:hclear:brhc hclear.nop; Branch if half carry flag cleared; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is truePreliminary5-21
BRHS - Branch if Half Carry Flag is SetDescription:Conditional relative branch. Tests the Half Carry flag (H) and branches relatively to PC if H is set. This instructionbranches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and isrepresented in two’s complement form. (Equivalent to instruction BRBS 5,k).(i)Operation:If H 1 then PC PC k 1, else PC PC 1(i)Syntax:BRHS kOperands:-64 k 6316 bit Opcode:111100kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek101Status Register (SREG) and Boolean ; Branch if half carry flag set; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is true5-22Instruction Set Preliminary
Instruction SetBRID - Branch if Global Interrupt is DisabledDescription:Conditional relative branch. Tests the Global Interrupt flag (I) and branches relatively to PC if I is cleared. Thisinstruction branches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset fromPC and is represented in two’s complement form. (Equivalent to instruction BRBC 7,k).(i)Operation:If I 0 then PC PC k 1, else PC PC 1(i)Syntax:BRID kOperands:-64 k 6316 bit Opcode:111101kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek111Status Register (SREG) and Boolean Formulae:I-T-H-S-V-N-Z-C-Example:intdis:brid intdis.nop; Branch if interrupt disabled; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is truePreliminary5-23
BRIE - Branch if Global Interrupt is EnabledDescription:Conditional relative branch. Tests the Global Interrupt flag (I) and branches relatively to PC if I is set. This instructionbranches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and isrepresented in two’s complement form. (Equivalent to instruction BRBS 7,k).(i)Operation:If I 1 then PC PC k 1, else PC PC 1(i)Syntax:BRIE kOperands:-64 k 6316 bit Opcode:111100kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek111Status Register (SREG) and Boolean en; Branch if interrupt enabled; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is true5-24Instruction Set Preliminary
Instruction SetBRLO - Branch if Lower (Unsigned)Description:Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is set. If the instruction isexecuted immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if theunsigned binary number represented in Rd was smaller than the unsigned binary number represented in Rr. Thisinstruction branches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset fromPC and is represented in two’s complement form. (Equivalent to instruction BRBS 0,k).(i)Operation:If Rd Rr (C 1) then PC PC k 1, else PC PC 1(i)Syntax:BRLO kOperands:-64 k 6316 bit Opcode:111100kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek000Status Register (SREG) and Boolean lonopr19,r19r19; Clear r19; Increase r19r19, 10loop; Compare r19 with 10; Branch if r19 10 (unsigned); Exit from loop (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is truePreliminary5-25
BRLT - Branch if Less Than (Signed)Description:Conditional relative branch. Tests the Signed flag (S) and branches relatively to PC if S is set. If the instruction isexecuted immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the signedbinary number represented in Rd was less than the signed binary number represented in Rr. This instruction branchesrelatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and is representedin two’s complement form. (Equivalent to instruction BRBS 4,k).(i)Operation:If Rd Rr (N V 1) then PC PC k 1, else PC PC 1(i)Syntax:BRLT kOperands:-64 k 6316 bit Opcode:111100kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek100Status Register (SREG) and Boolean 6,r1less; Compare r16 to r1; Branch if r16 r1 (signed); Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is true5-26Instruction Set Preliminary
Instruction SetBRMI - Branch if MinusDescription:Conditional relative branch. Tests the Negative flag (N) and branches relatively to PC if N is set. This instructionbranches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and isrepresented in two’s complement form. (Equivalent to instruction BRBS 2,k).(i)Operation:If N 1 then PC PC k 1, else PC PC 1(i)Syntax:BRMI kOperands:-64 k 6316 bit Opcode:111100kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek010Status Register (SREG) and Boolean .nopr18,4negative; Subtract 4 from r18; Branch if result negative; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is truePreliminary5-27
BRNE - Branch if Not EqualDescription:Conditional relative branch. Tests the Zero flag (Z) and branches relatively to PC if Z is cleared. If the instruction isexecuted immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if theunsigned or signed binary number represented in Rd was not equal to the unsigned or signed binary number representedin Rr. This instruction branches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is theoffset from PC and is represented in two’s complement form. (Equivalent to instruction BRBC 1,k).(i)Operation:If Rd Rr (Z 0) then PC PC k 1, else PC PC 1(i)Syntax:BRNE kOperands:-64 k 6316 bit Opcode:111101kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek001Status Register (SREG) and Boolean nenopr27,r27r27; Clear r27; Increase r27r27,5loop; Compare r27 to 5; Branch if r27 5; Loop exit (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is true5-28Instruction Set Preliminary
Instruction SetBRPL - Branch if PlusDescription:Conditional relative branch. Tests the Negative flag (N) and branches relatively to PC if N is cleared. This instructionbranches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is the offset from PC and isrepresented in two’s complement form. (Equivalent to instruction BRBC 2,k).(i)Operation:If N 0 then PC PC k 1, else PC PC 1(i)Syntax:BRPL kOperands:-64 k 6316 bit Opcode:111101kkkkkkProgram Counter:PC PC k 1PC PC 1, if condition is falsek010Status Register (SREG) and Boolean .nopr26, 50positive; Subtract 50 from r26; Branch if r26 positive; Branch destination (do nothing)Words: 1 (2 bytes)Cycles: 1 if condition is false2 if condition is truePreliminary5-29
BRSH - Branch if Same or Higher (Unsigned)Description:Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is cleared. If the instruction isexecuted immediately after execution of any of the instructions CP, CPI, SUB or SUBI the branch will occur if and onlyif the unsigned binary number represented in Rd was greater than or equal to the unsigned binary number represented inRr. This instruction branches relatively to PC in either direction (PC-64 destination PC 63). The parameter k is theoffset from PC and is represented
Instruction Set Preliminary 5-1 AVR Instruction Set This section describes all instructions for the 8-bit AVR in detail. For a specific device please refer to the specific Instruction Set Summary in the hardware description. Addressing modes are described in detail in the hardware description for each device. 8-Bit Instruction Set
AVR Basics The AVR microcontrollers are divided into three groups: 1. tiny AVR 2. AVR (Classic AVR) 3. mega AVR 4. xmega AVR The difference between these devices lies in the available features. The tinyAVR μC are usually devices with lower pin-count or a reduced feature set compared to the mega & xmega AVR's. All AVR devices have identical
The AVR 3700/AVR 370 7.2-channel and AVR 2700/AVR 270 7.1-channel digital audio/ video receivers continue this tradition with some of the most advanced audio and video processing capabilities yet, and a wealth of listening and viewing options. To obtain the maximum enjoyment from your new receiver, please read this manual and
the Avr 3700/Avr 370 7.2-channel and Avr 2700/Avr 270 7.1-channel digital audio/ video receivers continue this tradition with some of the most advanced audio and video processing capabilities yet, and a wealth of listening and viewing options. to obtain the maximum enjoyment from your new receiver, please read this manual and
avr 3700 и avr 2700 предназначены для использования с переменным током напряжением 120 В. avr 370 и avr 270 предназначены для использования с переменным током напряжением 220 – 240 В. Подключение к напряжению,
die receiver avr 3700 und avr 2700 sind für den Betrieb mit 120 v Wechselstrom (ac) ausgelegt. die receiver avr 370 und avr 270 sind für den Betrieb mit 220-240 v Wechselstrom (ac) ausgelegt. der anschluss an ein Stromnetz, das nicht dem Stromnetz entspricht, für das ihr receiver gebaut wurde, kann zu einem Sicherheits- und
download the AVR 3650, AVR 365, AVR 2650, AVR 265 Owner’s Manual. Place the Receiver Place the receiver on a firm and level surface. Be certain that the surface and any mounting hardware can support the receiver’s weight. Provide proper space above and below the receiver for ventilation. If you install the receiver
Устройства avr 3650 и avr 2650 были сконструированы для использования с источником сетевого напряжения 120 В переменного тока. Устройства avr 365 и avr 265 были сконструированы для исполь-
The Bridge II-ready Harman Kardon receivers, and the Harman Kardon DMC 1000 digital media center. As of the printing of this manual, these models include: Audio playback only: AVR 140, AVR 240, AVR 340, AVR 145, AVR 245, AVR 445, AVR 645, AVR 745, HK 3490
