PIC18F - Dr Jeff Software - Dr Jeff Home

COMP 122COMP122ASSEMBLY Programming/ISAPIC18FDr Jeff mljeffrey.drobman@csun.edu Jeff Drobman2016-2019

COMP122ISAPIC Jeff Drobman2016-2019

COMP122PIC Families Jeff Drobman2016-2019

COMP122PIC18F amily/8bit/ Jeff Drobman2016-2019

COMP122PIC18F Products Jeff Drobman2016-2019

PipeliningCOMP122INSTRUCTION FETCHSTOREPIC18FProgram Memory ReadINSTRUCTION DECODEEXECUTION Jeff Drobman2016-2019Opcode Data operand fetchALU, MoveWrite Buffer - MemoryPICINSTRUCTION DECODEDRXWDECODE READEXEC STOREInstruction cycle 4x clock frequency

ALU OperandsCOMP122INSTRUCTION REGISTER Jeff Drobman2016-2019PIC18FAddressLiteralLDATARAM(Reg File)FW REGISTERALUDATARAMW REGISTERADD WF: W F à WADD LW: L W à WSFRs-or-àF

COMP122PIC18F Dual MemoryPIC18FPIC 18F MICROCONTROLLERSTACKDATAAREA**CODEROM*SP, STATUS, W REGISTERSCOPYDATA AREAFILEREGSFRDATAROM**READ ONLY**use DB, DWDATARAM Jeff Drobman2016-2019

COMP122BSR (0-3)RAM Banks Jeff Drobman2016-2019PIC18F

COMP122SFRs Jeff Drobman2016-2019PIC18F

ALU & MOVECOMP122ADD Jeff Drobman2016-2019PIC18FSets all flagsADDLW data ;Add W to Literal data à W (only)ADDWF(C) addr , W/F ;Add W to F (Data RAM) à W or FMOVESets NO flags (1 exception*)MOVLW data ;Load Literal data à WMOVF* addr , W/F ;Load F at addr à W or F (same location; sets N, Z)MOVWF addr ;Store W à F at addr MOVFF addr1 , addr2 ;Move F1 à F2 in DataRAM (different location)MULTIPLYMULLWMULWFMOVFFMOVFFSets NO flags;Multiply W by Literal data à PROD [H,L];Multiply W by F at addr à PROD [H,L]PRODL , addr ;Store PRODL* à F at addr PRODH, addr ;Store PRODH* à F at addr *SFR

COMP122Addressing ModesPIC18FvDirect (in instruction) MOVF/WF addr [8]JUMP long-addr [21], BRA offset [ -7]vImmediate (Literal Data) MOV/ADDLW k [-128 to 127]vIndirect (Register indirect, uses FSR)§ LFSR n, addr [12-bit] (n 0, 1, 2)§ MOVF/WF INDFn§ CLRF/MOVF POSTINCn/POSTDECn/PREINCnvIndexed (Base Register FSR Index Register W )§ CLRF/MOVF PLUSWn§ INCF addr ,F ;increment F -or§ ADDLW 0x01 ;increment W Jeff Drobman2016-2019

Multiply & DivideCOMP122 Jeff Drobman2016-2019PIC18FMULTIPLYv Unsigned onlyv First convert negative numbers (2sC) – NEG opv Compute result sign: 0 if both signs same, 1 else (not )v Complement result if sign is negative – NEG opv Other MPUs use signed multiply (2sC) via “Booth’s Algorithm”DIVIDEv No hardware, no instructionv Create subroutine (may find ones in asm library)v Compute§ Long division§ Non-restoring division§ Iterative subtraction (very slow)v Use tricks§ Divide by 2 or any 2n: right SHIFT by n§ Divide by 10: convert to BCD, then right SHIFT by 4 (reconvert to binary)§ Divide by 5: divide by 10, then multiply by 2 (by shifting after conv. Bin)

PIC18F Memory MapCOMP122 Jeff Drobman2016-2019Setup codePIC 18F MICROCONTROLLERTABLEPTR(TBLPTR)RESETAREADATA AREACODEAREACODEROM*COPYDATA AREAFILEREGSFR*READ ONLY**DB, DWØ Using MPLab IDEDATAPTRInclude file (.inc);set code & data areas (EQU)START EQU 100H ;set code to start at 100HRDATA ORG EQU 50H ;reserved 176 bytes for dataCOUNTER EQU 0 ;reserve counter at 0DATAPTR EQU 1 ;base of File Reg at 1DATA SIZE EQU D’25’;create Data Table (DB) in CODE ROMZERO DB 0ONE DB 1TEN DB D’10’ALL1 DB FFH ;COPY Data Table from ROM to File Reg (next slide)

PIC18F Memory MapCOMP122 Jeff Drobman2016-2019“HELLO WORLD”PIC 18F MICROCONTROLLERTABLEPTR(TBLPTR)RESETAREADATA AREACOPYDATA AREACODEAREACODEROM*Ø Using MPLab IDEFILEREGSFRPORT BDATAPTRInclude file (.inc);set code & data areas (EQU)START EQU 100H ;set code to start at 100HRDATA ORG EQU 50H ;reserved 176 bytes for dataCOUNTER EQU 0 ;reserve counter at 0DATAPTR EQU 1 ;base of File Reg at 1DATA SIZE EQU D’12’;create Data Table (DB) in CODE ROM for messageHE DW A’HE’LL DW A’LL’OSP DW A’O ’WO DW A’WO’RL DW A’RL’D! DW A’D!’;COPY Data Table from ROM to PORT B (next slide)

COMP122Headers;set jump to start (mandatory)ORG 0GOTO start; reserve code ROM areas for INTsORG 0x08 ;high priority Int;output Int Ack or GOTO ISRRETFIEORG 0x18 ;low priority Int;output Int Ack or GOTO ISRRETFIE; declare useful constants – ‘ORG’ optZERO EQU 0ONE EQU 1TEN EQU D’10’ ;not just 10ALL1 EQU 0xFFSTART EQU 0x100 ;address 256ORG STARTstart NOP; start your code here Jeff Drobman2016-2019PIC18FØ Using MPLab IDERESERVE CODE AREADECLARE CONSTANTSSTART CODEZEROONETENALL1DBDBDBDB01D’10’0xFF

COMP122Use Headers Jeff Drobman2016-2019PIC18FØ Using MPLab IDE#include p18Fnnnn.inc ; “nnnn” part number#include constants.inc CREATE#include mylibrary.inc ;my code starts here your code SLEEP ;or use an infinite loopENDSimulator issues

COMP122Copy Data Table;Init vars & pointerMOVLW DATA SIZEMOVWF COUNTER ;init counter;LFSR 1,DATAPTR – not neededPIC18FØ Using MPLab IDE;init Table Pointer (21-bit address)CLRF TBLPTRU ;upper 5 bitsCLRF TBLPTRH ;High byteMOVLW RDATA ORGMOVWF TBLPTRL ; Low byte;Copy ROM Table into Port B loopLOOP TBLRD * ;read data from table into TABLAT & inc TBLPTRMOVFF TABLAT,PORTBCALR DELAY ;delay loop subroutineDECF COUNTERBNZ LOOPDO THIS IN THE LAB Jeff Drobman2016-2019

COMP122Copy Data Table8080/80856800 Jeff Drobman2016-2019

COMP122Connections Min Jeff Drobman2016-2019PIC18F

COMP122Configuration Jeff Drobman2016-2019PIC18F

COMP122Config Code Jeff Drobman2016-2019PIC18FASSEMBLYC

InterruptsCOMP122CLASSESv MASKABLEq NMI (non)q INT (maskable)PINSu INT 0 à Pin 33u INT 1 à Pin 34u INT 2 à Pin 35v VECTOREDq NVI (non – PIC)q VIv PRIORITY (PIC)q Highq Low (High INTs “preempt” Low)v INTERNALq Hardware events§ Timers§ ADC§ I/O (S, P)q Software exceptions Jeff Drobman2016-2019PIC18FENABLESv GIE – global (all 3)v INT 0-2v PRIE – peripheralsPRIORITIESv HIGHv LOWà SAVED ON STACKv PCvWv STATUSv BSRPROCESSOR STATE

COMP122Interrupts/Clocks PinsPIC18F Jeff Drobman2016-2019

COMP122Interrupts C ExamplePIC18F#include p18f4321.h void ISR (void); //declares ISR as sub after main#pragma code Int 0x08void Intasm( ){asm //use assembly codeGOTO ISRendasm}#pragma code //org mainVoid main( ){// do stuff hereWhile(1) { }}#pragma interrupt ISRVoid ISR (void) //interrupt svc routine{ //do int stuff} Jeff Drobman2016-2019

COMP122Config Interrupts in C Jeff Drobman2016-2019EXTERNAL INTS PIC18FVoid ISR( ); //declare the “ISR” subroutine#pragma code int vectH 0x08 //assign int “vector” for High Pri Int SET ORGSVoid IntH( ) {asm //use assembly code here (no “GOTO” in C)Or use a “Call”:GOTO ISRISR( )endasm#pragma code int vectL 0x18 //assign int “vector” for Low Pri Int#pragma code //main starts here (after the Ints)Void main ( ){PINSADCON1 0x0F; //config Port B as input for interruptsINTCONbits.INT0IE 1 //enable INT0u INT 0 à RB0INTCON3bits.INT1IE 1 //enable INT1 SETUPu INT 1 à RB1INTCONbits.INT0F 0 //clear flagu INT 2 à RB2INTCON3bits.INT1F 0 //clear flagINTCON3bits.INT1IP 0 //set INT1 to Low priorityRCONbits.IPEN 1 //enable all priority interruptsINTCONbits.GIEH 1 //enable Global High priority interruptsINTCONbits.GIEL 1 //enable Global Low priority interruptsWhile(1); //wait for INT0 or INT1}

TimersCOMP122Timersv Timer 0v Timer 1v Timer 2v Timer 3v WatchdogPRESCALERv Clock pulse counter(a power of 2)§§§§§§§§248163264128256 Jeff Drobman2016-2019PIC18FMODESvTimersØØØØCount UP or DOWNPreset start valueINT on OVERFLOWUse INTERNAL clockvCountersØ Use EXTERNAL clock (pin TnCKI)

COMP122Config Timers in C#pragma code //main starts here (after the Ints)Void main ( ){SETUPT0CON 0x06; //config T0TMR0H 0XFF //init T0 High byteTMR0L 0XF0 //init T0 Low byte -16 (will count UP to 0)INTCONbits.TMR0IF 0 //clear Timer0 flagT0CONbits.TMR0ON 1 //start timer RUN TIMERWhile(INTCONbits.TMR0IF 0); //wait for INT0 or INT1T0CONbits.TMR0ON 0 //stop timerWhile(1); //halt}Using Timer0 to create a 1ms delay, assume:q 8MHz crystal ( 2MHz Instruction rate)q Prescale value 128 (2000/128 16) Jeff Drobman2016-2019PIC18FTimersv Timer 0v Timer 1v Timer 2v Timer 3v Watchdog

COMP122Parallel Ports Jeff Drobman2016-2019PIC18F

COMP122WriteàRead Jeff Drobman2016-2019PIC18F

Serial PortsCOMP122 Jeff Drobman2016-2019PIC18FvUSART – async or syncvEIA (RS) 232 asyncq Framed: START, STOP bitsq Handshake: RTS, CTSvSPI – syncqqqqCOVEREDTHIS WEEKClocked data (SCK)SYNC charactersMaster/slave (clock data)2 registers§§Tx/Rx shifterBuffervI2C – syncq Peer to peer (IC to IC)vSPI – sync (4 pins)§§§SDISDOSDCLKvI2C – sync (4 pins)§§§SDISDOSDCLK

COMP122Serial Ports – Pins Jeff Drobman2016-2019PIC18F

INSTRUCTION FETCH INSTRUCTION DECODE EXECUTION STORE Opcode Data operand fetch ALU, Move Write Buffer - Memory Program Memory Read INSTRUCTION DECODE PIC D R X W DECODE READ EXEC STORE Instruction cycle 4x clock frequency PIC18F