ECE 485/585 Microprocessor System Design

ECE 485/585Microprocessor System DesignLecture 7:Memory ModulesMemory ControllersZeshan ChishtiElectrical and Computer Engineering Dept.Maseeh College of Engineering and Computer ScienceSource: Lecture based on materials provided by Mark F.

Memory Modules184 pin DDR SDRAM DIMM All chips in a “rank” receive same address and controlsignals Each chip responsible for subset of data bits in its rank Module acts as high capacity DRAM with wide data path Example: 8 chips, each 8 bits wide 64 bits Easy to add/replace memory in a system No need to solder or remove individual chips Memory granularity issue What’s the smallest increment in memory size?ECE 485/585From Hsien-Hsin Sean Lee, Georgia Institute of Technology

DRAM RanksECE 485/585

Organization of DRAM ModulesECE 485/585

Memory Modules SIMM (Single Inline Memory Module) 30-pin: some 286, most 386, some 486systems– Page Mode, Fast Page mode devices 72-pin: some 386, most 486, nearly allPentium (before DIMM)– Fast Page Mode, EDO devicesDIMM (Dual Inline Memory Module) Dominant todaySODIMM (Small Outline DIMM) Used in notebooks, Apple iMacRIMM (Rambus RDRAM Module)SIMM168 pin SDRAM DIMM184 pin DDR SDRAM DIMM200 pin DDR2, DDR3 SDRAM DIMMSODIMM240 pin DDR2, DDR3 SDRAM DIMMRIMMECE 485/585RIMM

SPD (Serial Presence Detect) 8-pin serial EEPROM on memory module Key parameters for SDRAM controller Number of row/column addressesNumber of ranksModule widthRefresh rate/typeError checking (none, parity, ECC)LatencyTiming parametersECE 485/585

DRAM and DIMM NomenclatureDevicenameClockM transfersper secMB/secPer DIMMDIMMnameDDR200100 MHz2001,600 MB/sPC-1600DDR266133 MHz2662,133 MB/sPC-2100DDR333166 MHz3332,666 MB/sPC-2700DDR400200 MHz4003,200 MB/sPC-3200DDR2-400200 MHz4003,200 MB/sPC2-3200DDR2-533266 MHz5334,266 MB/sPC2-4200DDR2-667333 MHz6665,333 MB/sPC2-5300DDR2-800400 MHz8006,400 MB/sPC2-6400DDR2-1066533 MHz10668,533 MB/sPC2-8500DDR3-800400 MHz8006,400 MB/sPC3-6400DDR3-1066533 MHz10668,500 MB/sPC3-8500DDR3-1333666 MHz133310,666 MB/sPC3-10600DDR3-1600800 MHz160012,800 MB/sPC3-12800DDR3-1866933 MHZ186614928 MB/sPC3-14900M transfers/second 2 transfers (DDR) x Clock RateDRAM name incorporates M transfers per secondMB/sec 8 bytes x M transfers per secondDIMM name incorporates MB/sec (rounded)ECE 485/585

DRAM/SDRAM Latency Specifications DRAM Used 4 numbers (e.g. 4-1-1-1) Indicates number of CPU cycles for 1st and successive accessesSDRAM CAS Latency (CAS or CL) Delay in clock cycles between request and the time the first data is available PC133 module might be described as CAS-2, CAS 2, CL2, CL-2, or CL 2SDR-DRAM DDR-DRAM CAS Latency of 1, 2, or 3CAS Latency of 2 or 2.5When three numbers appear (e.g. 3-2-2) CAS Latency (tCAC) RAS-to-CAS delay (tRCD) RAS pre-charge time (tRP)DDR3 seeing use of four numbers CAS Latency ( tCAS tCL, CL) RAS-to-CAS delay (tRCD) RAS pre-charge time (tRP) RAS access time (tRAS)ECE 485/5853-3-3-10 timing

Key SDRAM Timing Parameters Determines Latency: tRCD: Minimum time between an ACTIVE command andREAD command CL (CAS Latency): Time between READ command and firstdata valid Determines Bandwidth: tRC: Time between successive row access to different rows(tRC tRAS tRP) tRAS : Time between ACTIVE command and end of restoration ofdata in DRAM array tRP: Time to pre-charge DRAM array in preparation for anotherrow accessECE 485/585

EX: Comparing Performance of DIMMsParameterClock PeriodTCKCAS LatencyCLPC3-12800DIMM1/800Mhz 1.25ns9RAS-to-CAS DelayTRCD99RAS pre-charge timeTRP99RAS access timeTRAS2727Cost/pair 176196 SDRAMSpecPC3-14900 DIMM1/933Mhz 1.07ns9Best Bandwidth/ : tRC tRAS tRP 27 9 36 (for both DIMMs) 14900/12800 1.16, 196/176 1.11 so 16% bandwidth gain, 11%increase in cost I’d buy the PC3-14900 DIMMsTime from ACTIVATE to end of cycle: Time to first byte (Latency) for PC3-12800 TRCD CL 9 9 18 Time to get 8 bytes of data (burst size 8, DDR) 4 Total time (18 4) * 1.25ns 27.5nsECE 485/585

DDR4 JEDEC released standard September 2012Reached 50% of market by 2015-2016Hynix announced 128 GB module using 8 Gb DDR4 in April 2014AMD (Hierofalcon), Intel (Haswell-E) supporting DDR4 in 2014No longer multi-drop – point-to-point with single DIMM per channel284-pin DIMM interfaceECE 485/585

Memory ControllersECE 485/585

Memory Controllers Handle the actual interface to memory Determine memoryconfiguration/capability Memory Timing/Signal interface Address Mapping Error CorrectionSchedulingRefreshWAS in North Bridge of chipset Physical Address to Memory TopologyIntel prior to NehalemMCH (Memory Controller Hub)Isolates mp from memorytechnology/device changesIS Integrated with microprocessor AMD, Intel NehalemLow latency for high performanceOpens possibility for processor-directedhintsECE 485/585

Address MappingDual channelsChannel IDECE 485/585Memory moduleRankRowBankColumn

Address Mapping(cont’d)Dual channelsChannel IDMemory moduleRankRowBankColumnChannelPhysical path between CPU andmemoryRankGroup of DRAM chips operating inlockstepSame address, control, CSResponsible for subset of same“word”BankSet of independent memory arraysin DRAM chipRow/ColumnAddress of bit cell in a bankMay be several “planes” to achieve n bits“wide”ECE 485/585

From Hsien-Hsin Sean Lee, Georgia Institute of Technology. ECE 485/585 DRAM Ranks. ECE 485/585 Organization of DRAM Modules. ECE 485/585 Memory Modules SIMM (Single Inline Memory Module) 30-pin: some 286, most 386, some 486 systems – Page Mode, Fast Page mode devices