Universal Serial Bus Specification - HW
Universal Serial BusSpecificationCompaqDigital Equipment CorporationIBM PC CompanyIntelMicrosoftNECNorthern TelecomRevision 1.0January 15, 1996
Universal Serial Bus Specification Revision 1.0Scope of this RevisionThe 1.0 revision of the specification is intended for product design. Every attempt has been made to ensure aconsistent and implementable specification. Implementations should ensure compliance with this revision.Revision HistoryRevisionIssue DateComments0.7November 11, 1994Supersedes 0.6e.0.8December 30, 1994Revisions to Chapters 3-8, 10, and 11. Addedappendixes.0.9April 13, 1995Revisions to all the chapters.0.99August 25, 1995Revisions to all the chapters.1.0 FDRNovember 13, 1995Revisions to Chapters 1, 2, 5-11.1.0January 15, 1996Edits to Chapters 5, 6, 7, 8, 9, 10, and 11 forconsistency.Proposal for Universal Serial Bus SpecificationCopyright 1996, Compaq Computer Corporation, Digital Equipment Corporation,IBM PC Company, Intel Corporation, Microsoft Corporation, NEC, Northern Telecom.All rights reserved.INTELLECTUAL PROPERTY DISCLAIMERTHIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANYWARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANYWARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE.A LICENSE IS HEREBY GRANTED TO REPRODUCE AND DISTRIBUTE THIS SPECIFICATION FORINTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY OTHER INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY.AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FORINFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION INTHIS SPECIFICATION. AUTHORS OF THIS SPECIFICATION ALSO DO NOT WARRANT OR REPRESENTTHAT SUCH IMPLEMENTATION(S) WILL NOT INFRINGE SUCH RIGHTS.GeoPort and Apple Desktop Bus are trademarks of Apple Computer, Inc.Windows and Windows NT are trademarks and Microsoft and Win32 are registered trademarks of MicrosoftCorporation.IBM, PS/2, and Micro Channel are registered trademarks of International Business Machines Corporation.AT&T is a registered trademark of American Telephone and Telegraph Company.Compaq is a registered trademark of Compaq Computer Corporation.UNIX is a registered trademark of UNIX System Laboratories.2I C is a trademark of Phillips Semiconductors.DEC is a trademark of Digital Equipment Corporation.All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.Please send comments via electronic mail to USB@fes.fm.intel.comFor industry information, refer to the USB Implementers Forum web page at http://www.teleport.com/ USB2
Universal Serial Bus Specification Revision 1.0ContentsCHAPTER 1 INTRODUCTION1.1 Motivation . 111.2 Objective of the Specification. 111.3 Scope of the Document. 121.4 Document Organization. 12CHAPTER 2 TERMS AND ABBREVIATIONSCHAPTER 3 BACKGROUND3.1 Goals for the Universal Serial Bus . . 233.2 Taxonomy of Application Space. 233.3 Feature List. 243.4 Some Existing Technologies. 26CHAPTER 4 ARCHITECTURAL OVERVIEW4.1 USB System Description . 274.1.1 Bus Topology. 284.2 Physical Interface. 294.2.1 Electrical. 294.2.2 Mechanical . 304.3 Power. 304.3.1 Power Distribution . 304.3.2 Power Management. 304.4 Bus Protocol . 304.5 Robustness. 314.5.1 Error Detection . 314.5.2 Error Handling . 313
Universal Serial Bus Specification Revision 1.04.6 System Configuration.314.6.1 Attachment of USB Device .314.6.2 Removal of USB Device .324.6.3 Bus Enumeration.324.6.4 Inter-Layer Relationship.324.7 Data Flow Types.324.7.1 Control Transfers .334.7.2 Bulk Transfers.334.7.3 Interrupt Transfers.334.7.4 Isochronous Transfers.334.7.5 Allocating USB Bandwidth .344.8 USB Devices.344.8.1 Device Characterizations.344.8.2 Device Descriptions .354.9 USB Host: Hardware and Software .374.10 Architectural Extensions.37CHAPTER 5 USB DATA FLOW MODEL5.1 Implementer Viewpoints.395.2 Bus Topology.415.2.1 USB Host .415.2.2 USB Devices.425.2.3 Physical Bus Topology.425.2.4 Logical Bus Topology .435.2.5 Client Software to Function Relationship .445.3 USB Communication Flow.445.3.1 Device Endpoints .465.3.2 Pipes .475.4 Transfer Types .495.5 Control Transfers.505.5.1 Data Format .505.5.2 Direction .515.5.3 Packet Size Constraints .515.5.4 Bus Access Constraints .525.5.5 Data Sequences .535.6 Isochronous Transfers.545.6.1 Data Format .545.6.2 Direction .545.6.3 Packet Size Constraints .545.6.4 Bus Access Constraints .555.6.5 Data Sequences .564
Universal Serial Bus Specification Revision 1.05.7 Interrupt Transfers. 565.7.1 Data Format . 565.7.2 Direction. 565.7.3 Packet Size Constraints . 565.7.4 Bus Access Constraints . 575.7.5 Data Sequences . 585.8 Bulk Transfers . 585.8.1 Data Format . 595.8.2 Direction. 595.8.3 Packet Size Constraints . 595.8.4 Bus Access Constraints . 595.8.5 Data Sequences . 605.9 Bus Access for Transfers . 615.9.1 Transfer Management . 615.9.2 Transaction Tracking . 645.9.3 Calculating Bus Transaction Times. 655.9.4 Calculating Buffer Sizes in Functions/Software. 675.9.5 Bus Bandwidth Reclamation . 675.10 Special Considerations for Isochronous Transfers . 675.10.1 Example Non-USB Isochronous Application. 685.10.2 USB Clock Model . 715.10.3 Clock Synchronization . 735.10.4 Isochronous Devices. 735.10.5 Data Prebuffering. 815.10.6 SOF Tracking. 825.10.7 Error Handling . 825.10.8 Buffering for Rate Matching . 83CHAPTER 6 MECHANICAL6.1 Architectural Overview . 856.2 Dimensioning Requirements. 856.3 Cable. 866.3.1 Cable Specification . 866.3.2 Connector (Series A). 906.3.3 Connector (Series B) . 966.3.4 Serial Bus Icon. 1016.3.5 Plug/Receptacle Mechanical and Electrical Requirements. 1026.4 Cable Voltage Drop Requirements. 1076.5 Propagation Delay. 1086.6 Grounding . 1086.7 Regulatory Information . 1095
Universal Serial Bus Specification Revision 1.0CHAPTER 7 ELECTRICAL7.1 Signaling .1117.1.1 USB Driver Characteristics .1117.1.2 Receiver Characteristics .1137.1.3 Signal Termination.1147.1.4 Signaling Levels.1157.1.5 Data Encoding/Decoding.1217.1.6 Bit Stuffing . 1227.1.7 Sync Pattern .1237.1.8 Initial Frame Interval and Frame Adjustability .1247.1.9 Data Signaling Rate.1247.1.10 Data Signal Rise and Fall Time . 1247.1.11 Data Source Signaling .1257.1.12 Hub Signaling Timings.1267.1.13 Receiver Data Jitter .1277.1.14 Cable Delay.1297.1.15 Bus Turnaround Time/Interpacket Delay.1297.1.16 Maximum End to End Signal Delay .1307.2 Power Distribution.1317.2.1 Classes of Devices.1317.2.2 Voltage Drop Budget.1357.2.3 Power Control During Suspend/Resume .1367.2.4 Dynamic Attach and Detach.1367.3 Physical Layer.1377.3.1 Environmental.1377.3.2 Bus Timing/Electrical Characteristics .1387.3.3 Timing Waveforms .142CHAPTER 8 PROTOCOL LAYER8.1 Bit Ordering .1458.2 SYNC Field.1458.3 Packet Field Formats .1458.3.1 Packet Identifier Field .1458.3.2 Address Fields.1468.3.3 Frame Number Field .1478.3.4 Data Field .1478.3.5 Cyclic Redundancy Checks .1478.4 Packet Formats .1488.4.1 Token Packets .1488.4.2 Start of Frame Packets.1498.4.3 Data Packets.1498.4.4 Handshake Packets.1498.4.5 Handshake Responses.1506
Universal Serial Bus Specification Revision 1.08.5 Transaction Formats. 1528.5.1 Bulk Transactions . 1528.5.2 Control Transfers . 1538.5.3 Interrupt Transactions . 1558.5.4 Isochronous Transactions . 1568.6 Data Toggle Synchronization and Retry . 1578.6.1 Initialization via SETUP Token . 1578.6.2 Successful Data Transactions . 1578.6.3 Data Corrupted or Not Accepted . 1588.6.4 Corrupted ACK Handshake. 1588.6.5 Low Speed Transactions . 1598.7 Error Detection and Recovery . 1618.7.1 Packet Error Categories. 1618.7.2 Bus Turnaround Timing . 1618.7.3 False EOPs. 1628.7.4 Babble and Loss of Activity Recovery . 163CHAPTER 9 USB DEVICE FRAMEWORK9.1 USB Device States . 1659.1.1 Visible Device States . 1659.1.2 Bus Enumeration. 1699.2 Generic USB Device Operations . 1709.2.1 Dynamic Attachment and Removal. 1709.2.2 Address Assignment. 1709.2.3 Configuration. 1709.2.4 Data Transfer . 1719.2.5 Power Management. 1719.3 USB Device Requests . 1729.3.1 bmRequestType . 1729.3.2 bRequest . 1739.3.3 wValue. 1739.3.4 wIndex . 1739.3.5 wLength. 1739.4 Standard Device Requests . 1739.4.1 Clear Feature. 1769.4.2 Get Configuration . 1769.4.3 Get Descriptor. 1769.4.4 Get Interface . 1779.4.5 Get Status. 1779.4.6 Set Address . 1799.4.7 Set Configuration . 1799.4.8 Set Descriptor . 1799.4.9 Set Feature . 1809.4.10 Set Interface. 1809.4.11 Synch Frame . 1807
Universal Serial Bus Specification Revision 1.09.5 Descriptors .1819.6 Standard USB Descriptor Definitions .1829.6.1 Device.
Universal Serial Bus Specification Revision 1.0 2 Scope of this Revision The 1.0 revision of the specification is intended for product design. Every attempt has been made to ensure a consistent and implementable specification. Implementations should ensure compliance with thi
Universal Serial Bus Revision 3.2 Specification Universal Serial Bus Revision 3.2 Specification. xxxx and xxxx xxxx and xxxx. Uni-versal Serial Bus Specification Universal Serial Bus Revision 3.2 Specification I2C-Bus Specification I2C-Bus Specification Sys-tem Management Bus Specification
[2] Universal Serial Bus 3.1 Specification, revision 1.0, July 26, 2013 [3] Universal Serial Bus Specification, Revision 2.0, April 27, 2000. [4] USB-IF USB 2.0 Electrical Test Specification, Version 1.03, January 2005. 1.2 USB 2.0 Compliance USB 2,0 testing is required for USB 3.1 devices and is covered by a separate compliance testing program.
Product Specification LogiCORE IP AXI Universal Serial Bus 2.0 Device (v1.00a) Functional Description The USB 2.0 protocol multiplexes many devices over a single, half-duplex, serial bus. The bus runs at 480 Mbps (High Speed) or at 12 Mbps (Full Speed) and is designed to be plug-and-pl
Product Specification LogiCORE IP XPS Universal Serial Bus 2.0 Device (v7.00.a) Functional Description The USB 2.0 protocol multiplexes many devices over a single, half-duplex, serial bus. The bus runs at 480 Mb/s (High Speed) or at 12 Mb/s (Full Speed) and is designed to be plug-and-pl
1 TXD O (1) Serial port (Transmitted Data) 2 DTR_N O (1) Serial port (Data Terminal Ready) 3 RTS_N O (1) Serial port (Request To Send) 4 VDD_325 P RS232 VDD. The power pins for the serial port signals. When the serial port is 3.3V, this should be 3.3V. When the serial port is 2.5V, this should be 2.5V. 5 RXD I (2) Serial port (Received Data)
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Universal Serial Bus Class Definitions for Communication Devices Version 1.1 January 19, 1999. . Scope of this Revision This version 1.1 of this class specification is intended for product design. Every attempt has been made to ensure a consistent and implementable specification. Implem
Rough paths Guide for this section Hölder p-rough paths, which control the rough differential equations dxt F(xt)X(dt),d ϕt F X(dt), and play the role of the controlhin the model classical ordinary differential equation dxt Vi(xt)dh i t F(xt)dht are defined in section 3.1.2. As R -valued paths, they are not regular enough for the formula µts(x) x Xi ts Vi(x) to define an .
