Analog Dialogue Volume 45, Number 3, 2011

Power ManagementDesign for PLLsBy Austin Harney and Grzegorz WawrzolaAbstractThe phase-locked loop (PLL) is a fundamental building blockof modern communication systems. PLLs are typically used toprovide the local-oscillator (LO) function in a radio receiver ortransmitter; they are also used for clock-signal distribution andnoise reduction—and, increasingly, as the clock source for highsampling-rate analog-to-digital or digital-to-analog conversion.As the noise performance of PLLs is improving with eachgeneration, the impact of power supply noise is becomingincreasingly evident, and can even limit noise performance insome cases.T his ar ticle considers t he basic PL L scheme shown inFigure 1 and examines the power-management requirements foreach building block.VP3V TO 30V0.5mA TO 5mALOW RIPPLEPHASEDETECTORCHARGEPUMPLOOPFILTERN DIVIDERVVCO3V TO 5V25mA TO 300mAULTRALOW NOISEVCOVOLTAGE-CONTROLLEDOSCILLATORAVDD/DVDD1.8V TO 5V10mA TO 50mAMODERATE NOISEFigure 1. A basic phase-locked loop showing the variouspower-management requirements.The sensitivity of the VCO to power-supply variation is defined asthe VCO pushing (Kpushing), usually a fraction of the wanted K VCO.For example, Kpushing is usually 5% to 20% of K VCO. Thus, forhigh-gain VCOs, the pushing effect becomes larger, and the noisecontribution from the VCO supply source becomes more critical.VCO pushing is measured by applying a dc tuning voltage to theVTUNE pin, varying the power supply voltage, and measuringthe frequency change. The pushing figure is the ratio of frequencychange to voltage change, as shown in Table 1, using theADF4350 PLL.Table 1. ADF4350 VCO Pushing MeasurementsVtune(V)f 1 (MHz) atV VCO 3 Vf 2 (MHz) atV VCO 3.3 VKpushing d(MHz)Another method, mentioned in Reference 2, is to dc-couple alow-frequency square wave into the supply, while observing thefrequency-shift-keyed (FSK) modulation peaks on either side of theVCO spectrum (Figure 2). The frequency deviation between thepeaks divided by the amplitude of the square wave yields the VCOpushing number. This can be a more accurate measure than thestatic dc test, as it removes any thermal effects associated with achange in dc input voltage. Figure 2 shows a spectrum analyzerplot of the ADF4350 VCO output at 3.3 GHz with a 10 kHz,0.6 V p-p square wave applied to the nominal 3.3-V supply. Theresulting deviation is 3326.51 MHz – 3324.89 MHz 1.62 MHz,for a pushing number of 1.62 MHz/0.6 V or 2.7 MHz/V. Thiscompares to the static measure of 2.3 MHz/V given in Table 1.In a PLL, the feedback control loop drives a voltage-controlledoscillator (VCO) to make the oscillator frequency (or phase)accurately track a multiple of an applied reference frequency. Manygood references, for example, Best’s Phase-Locked Loops,1 explainthe mathematical analysis of the PLL; and simulation tools, suchas Analog Devices’ ADIsimPLL , can be helpful in understandingthe loop transfer functions and calculations. Let us now look atthe PLL building blocks in turn.The VCO and VCO PushingThe voltage-controlled oscillator converts the error voltage from thephase detector into an output frequency. Its “gain,” defined asKVCO, is usually specified in MHz/V. A voltage-controlled variablecapacitance diode (varactor) is often used to adjust frequency inVCOs. The gain of the VCO is usually large enough to provideadequate frequency coverage, but not so large as to degrade phasenoise—since any varactor noise will be amplified by K VCO andcontribute to output phase noise.The advent of multiband integrated VCOs, such as that used in theADF4350 frequency synthesizer with integrated VCO, obviates thetrade-off between KVCO and frequency coverage, allowing the PLLdesigner to use an IC containing several moderate-gain VCOs, withintelligent band switching routines to select the appropriate band,depending on the programmed output frequency. This partitioningof the frequency band provides wide overall range and lower noise.In addition to the desired translation from input voltage changeto output frequency change (K VCO), power-supply variation canproduce an unwanted component of output frequency change.Analog Dialogue Volume 45 Number 3Figure 2. A spectrum-analyzer plot of ADF4350 VCOresponse to supply modulation by a 10-kHz, 0.6-V p-psquare wave.In a PLL system, higher VCO pushing means greater multiplicationof VCO power-supply noise. A low-noise power supply is requiredto minimize the impact on VCO phase noise.Reference 3 and Reference 4 provide good examples of howdifferent low-dropout regulators (LDOs) can affect PLL phasenoise. For example, a comparison was made between the ADP3334and ADP150 LDOs in powering an ADF4350. The integratedrms noise of the ADP3334 regulator is 27 µV (over four decades,3

from 10 Hz to 100 kHz). This compares to 9 µV for the ADP150,the LDO used on the ADF4350 evaluation board. The differencein measured PLL phase-noise spectral density can be seen inFigure 3. The measurement was taken with a 4.4-GHz VCOfrequency, where the VCO pushing was maximum (Table 1), sothis is a worst-case result. The ADP150 regulator noise was lowenough so that its contribution did not measurably add to the VCOnoise, as was confirmed by repeating the measurement with two(presumably “noiseless”) AA batteries.ΦINPHASEDETECTORLOW-PASSFILTERVCOΦOUT NCOUNTERFigure 4. Small-signal additive VCO supply noise model.–60SUPPLY 2 ADP3334AA BATTERY (2 1.5V)SUPPLY 2 ADP150–70PHASE NOISE (dBc/Hz)ΦLDOIn a free-running VCO, the total noise is the root-sum-square (rss)of LLDO and the VCO noise. Thus, expressed in dB:–80For example, consider a VCO with a pushing number of 10 MHz/Vand a measured phase noise of –116 dBc/Hz at 100 kHz offset:what is the required noise spectral density of the power supplyso as to not degrade the VCO noise performance at 100 kHz?The supply noise and VCO noise add as the root-sum-square, sothe supply noise should be at least 6 dB less than the VCO noiseto minimize its contribution. Thus, L LDO should be less than–122 dBc/Hz. Using Equation 1,–90–100–110–1201k10k100k1MOFFSET FROM 4.4GHz CARRIER (Hz)Figure 3. ADF4350 phase noise comparison at4.4 GHz when powered with pairs of ADP3334 andADP150 LDOs—and AA batteries.solving for vLDO ( f ),Figure 3 emphasizes the importance of a low-noise power sourcefor the ADF4350, but how do you specify the noise requirementof the power supply or LDO?In a manner similar to VCO noise, the phase noise contributionof the LDO can be modeled as an additive component, ΦLDO (t),as shown in Figure 4. Reusing the VCO excess phase expressionyields:The LDO noise spectral density at a given offset can usually beread from the LDO data sheet’s typical performance curves.When the VCO is connected in a negative-feedback PLL, the LDOnoise, LLDO, is high-pass filtered by the PLL loop filter, in a similarmanner to VCO noise. Thus, the above formula only applies tofrequency offsets greater than the PLL loop bandwidth. Withinthe PLL’s loop bandwidth, the PLL can successfully track andfilter the LDO noise, reducing its contribution.LDO Filteringor, in the frequency domainwhere vLDO ( f ) is the voltage noise spectral density of the LDO.The single-sideband power spectral density SΦ( f ) in a 1-Hzbandwidth is given byExpressing this in dB, the formula for calculating the phase noisecontribution due to the power supply noise is:(1)where L(LDO) is the noise contribution from the regulator to theVCO phase noise (in dBc/Hz), at an offset f; Kpushing is the VCOpushing figure in Hz/V; and vLDO ( f ) is the noise spectral densityat a given frequency offset in V/ Hz.4vLDO ( f ) 11.2 nV/ Hz at 100-kHz offsetTo improve LDO noise, there are typically two choices: use anLDO with less noise or post-filter the LDO’s output. The filteringoption can be a good choice when the noise requirements withouta filter are beyond the capability of affordable LDOs. A simpleLC π-filter is often sufficient to reduce out-of-band LDO noiseby 20 dB (Figure 5).Figure 5. LC π-filter to attenuate LDO noise.Care is needed in the choice of components. A typical inductor willbe in the microhenry range—with a ferrite core—so it is necessaryto consider its saturation current (ISAT), specified in inductor datasheets as the dc current level at which the inductance drops by 10%.The current drawn by the VCO should be less than ISAT. Effectiveseries resistance (ESR) is also a concern, as this will cause an IRdrop across the filter. For a microwave VCO drawing 300-mA dc,an inductor with ESR less than 0.33 Ω would be needed to yieldan IR drop of less than 100 mV. A low, but nonzero, ESR is alsodesirable to damp the filter response and improve LDO stability.It can be practical to choose a capacitor with very low parasiticAnalog Dialogue Volume 45 Number 3

Charge Pump and FilterThe charge pump converts the phase detector error voltage intocurrent pulses, which are integrated and smoothed by the PLL loopfilter. The charge pump can typically operate at up to 0.5 V belowits supply voltage (V P). For example, if the maximum charge pumpsupply is 5.5 V, the charge pump could only operate at an outputvoltage up to 5 V. If the VCO requires higher tuning voltages,an active filter is typically required. Useful information and areference design of an actual PLL can be found in Circuit NoteCN-0174,5 and ways of dealing with high-voltage are discussed in“Designing High-Performance Phase-Locked Loops with HighVoltage VCOs,”6 which appeared in Analog Dialogue Volume 43,Number 4 (2009). The alternative to an active filter is to use aPLL with a charge pump designed for higher voltage, such as theADF4150HV. The ADF4150HV can operate with charge-pumpvoltages as high as 30 V, thus avoiding the need for active filtersin many cases.The low current drawn by the charge pump makes it look attractiveto use a boost converter to generate the high charge-pump voltagefrom a lower supply voltage, but the switching-frequency rippleassociated with this type of dc-to-dc converter could produceunwanted spurious tones at the output of the VCO. High PLLspurs can potentially cause failure of a transmitter emission masktest or degrade sensitivity and out-of-band blocking in a receiversystem. To help guide the specification of converter ripple, acomprehensive power supply rejection plot vs. frequency wastaken for various PLL loop bandwidths, using the measurementsetup of Figure 6.SIGNALGENERATORDC INPUT 10𝛍HDC AC 0200400600800 1000 1200 1400 1600 1800 2000INJECTED AC SIGNAL FREQUENCY (kHz)Figure 7. ADF4150HV charge pump power-supplyrejection plot.POWER SUPPLYPS2520GACINPUT 2𝛍FWith a switching speed of 1.3 MHz, the ADP1613 is a good exampleof a suitable boost converter. With the PLL loop bandwidth set to10 kHz, a PSR of about 90 dB i

Differential Interfaces Improve Performance in RF Transceiver Designs Traditional IF and RF transceivers use 50-Ω single-ended interfaces, with interconnected circuits all seeing matching input and output impedances. In modern transceiver designs, differential interfaces provide better performance, but their implementation