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AXI DMA v7.1LogiCORE IP Product GuideVivado Design SuitePG021 April 27, 2022Xilinx is creating an environment where employees, customers,and partners feel welcome and included. To that end, we’reremoving non-inclusive language from our products and relatedcollateral. We’ve launched an internal initiative to removelanguage that could exclude people or reinforce historical biases,including terms embedded in our software and IPs. You may stillfind examples of non-inclusive language in our older products aswe work to make these changes and align with evolving industrystandards. Follow this link for more information.
Table of ContentsIP FactsChapter 1: OverviewFeature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Chapter 2: Product SpecificationPerformance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Scatter Gather Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Multichannel DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Chapter 3: Designing with the CoreTypical System Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68697070Chapter 4: Design Flow StepsCustomizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75838484Chapter 5: Example DesignImplementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Test Bench for the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89LogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback2
Appendix A: UpgradingMigrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Appendix B: DebuggingFinding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Vivado Design Suite Debug Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Appendix C: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback94949595983
IP FactsIntroductionThe Xilinx LogiCORE IP AXI Direct MemoryAccess (AXI DMA) core is a soft Xilinx IP core foruse with the Xilinx Vivado Design Suite. TheAXI DMA provides high-bandwidth directmemory access between memory andAXI4-Stream target peripherals. Its optionalscatter/gather capabilities also offload datamovement tasks from the Central ProcessingUnit (CPU).LogiCORE IP Facts TableCore SpecificsSupportedDeviceFamily (1)Versal ACAP, UltraScale UltraScale Zynq -7000 SoC,Xilinx 7 series FPGAsSupportedUser InterfacesAXI4, AXI4-Lite, AXI4-StreamResourcesPerformance and Resource Utilization web pageProvided with CoreFeatures AXI4 compliant Optional Scatter/Gather Direct MemoryAccess (DMA) support AXI4 data width support of 32, 64, 128, 256,512 and 1,024 bits AXI4-Stream data width support of 8, 16,32, 64, 128, 256, 512 and 1,024 bitsDesign FilesVHDLExampleDesignVHDLTest BenchVHDLConstraintsFileDelivered with IP GenerationSupportedS/W Drivers (2)Standalone and LinuxTested Design Flows (3)Design Entry Optional Keyhole supportSimulation Optional Data Re-Alignment support forstreaming data widths up to 512 bitsSynthesis Optional AXI Control and Status Streams Optional Micro DMA Support Support for up to 64-bit addressingVivado Design SuiteFor supported simulators, see theXilinx Design Tools: Release Notes Guide.Vivado SynthesisSupportXilinx Support web page1. For a complete list of supported devices, see the Vivado IPcatalog.2. Standalone driver information can be found in the SoftwareDevelopment Kit (SDK) installation directory. Seexilinx drivers.htm in install directory /SDK/ release /data/embeddedsw/doc/xilinx drivers.htm.3. For the supported versions of the tools, see theXilinx Design Suite: Release Notes Guide.LogiCORE IP AXI DMA v7.1PG021 April 27, 2022Send Feedbackwww.xilinx.com4
Chapter 1OverviewThe AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memoryaccess between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its optionalscatter gather capabilities also offload data movement tasks from the Central ProcessingUnit (CPU) in processor-based systems. Initialization, status, and management registers areaccessed through an AXI4-Lite slave interface. Figure 1-1 illustrates the functionalcomposition of the core.X-Ref Target - Figure 1-1AXI4 Memory Map ReadDataMoverMM2S Cntl/Sts LogicAXI4-LiteRegistersScatter/GatherS2MM Cntl/Sts LogicAXI4 Memory Map WriteDataMoverAXI4 Stream Master (MM2S)AXI4 Control Stream (MM2S)AXI4 Memory Map Write/ReadAXI4 Stream (S2MM)AXI4-Stream Slave (S2MM)x13225Figure 1-1:LogiCORE IP AXI DMA v7.1PG021 April 27, 2022AXI DMA Block Diagramwww.xilinx.comSend Feedback5
Chapter 1: OverviewPrimary high-speed DMA data movement between system memory and stream target isthrough the AXI4 Read Master to AXI4 memory-mapped to stream (MM2S) Master, and AXIstream to memory-mapped (S2MM) Slave to AXI4 Write Master. AXI DMA also enables upto 16 multiple channels of data movement on both MM2S and S2MM paths inscatter/gather mode.The MM2S channel and S2MM channel operate independently. The AXI DMA provides 4 KBaddress boundary protection (when configured in non Micro DMA), automatic burstmapping, as well as providing the ability to queue multiple transfer requests using nearlythe full bandwidth capabilities of the AXI4-Stream buses. Furthermore, the AXI DMAprovides byte-level data realignment allowing memory reads and writes starting at any byteoffset location.The MM2S channel supports an AXI Control stream for sending user application data to thetarget IP. For the S2MM channel, an AXI Status stream is provided for receiving userapplication data from the target IP.The optional Scatter/Gather Engine fetches and updates buffer descriptors from systemmemory through the AXI4 Scatter Gather Read/Write Master interface.Feature Summary AXI4 compliant Optional Independent Scatter/Gather Direct Memory Access (DMA) support Provides offloading of DMA management work from the CPU Provides fetch and update of transfer descriptors independent from primary databus Allows descriptor placement to be in any memory-mapped location separate fromdata buffers. For example, descriptors can be placed in block RAM. Provides optional cyclic operationOptional Direct Register Mode (no scatter/gather support)A lower performance but less FPGA-resource-intensive mode can be enabled byexcluding the Scatter Gather engine. In this mode transfers are commanded by setting aSource Address (for MM2S) or Destination Address (For S2MM) and then specifying abyte count in a length register. Primary AXI4 data width support of 32, 64, 128, 256, 512 and, 1,024 bits Primary AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and, 1,024 bits Optional Data Re-alignment Engine for a stream data width up to 512 bitsLogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback6
Chapter 1: OverviewAllows data realignment to the byte (8 bits) level on the primary memory map andstream datapaths Optional AXI Control and Status Streams to interface to AXI Ethernet IPProvides optional Control Stream for the MM2S Channel and Status Stream for theS2MM channel to offload low-bandwidth control and status from the high-bandwidthdatapath. Optional Micro modeAXI DMA can be configured to deliver a low footprint, low performance IP that canhandle the transfer of small packets. Read the following chapters for more information.ApplicationsThe AXI DMA provides high-speed data movement between system memory and anAXI4-Stream-based target IP such as AXI Ethernet.Licensing and OrderingThis Xilinx LogiCORE IP module is provided at no additional cost with the XilinxVivado Design Suite under the terms of the Xilinx End User License.Information about this and other Xilinx LogiCORE IP modules is available at the XilinxIntellectual Property page. For information on pricing and availability of other XilinxLogiCORE IP modules and tools, contact your local Xilinx sales representative.LogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback7
Chapter 2Product SpecificationPerformanceThis section contains the following subsections. Performance and Resource Utilization Latency and ThroughputLatency and ThroughputTable 2-1 and Table 2-2 describe the latency and throughput for the AXI DMA. The tablesprovide performance information for a typical configuration. The throughput test consistedof transferring 10,000 bytes on the MM2S and S2MM side.Throughput is measured from completion of descriptor fetching (DMACR.Idle 1) to framecount interrupt assertion.Table 2-1:AXI DMA Latency NumbersDescriptionClocksMM2S ChannelTail Descriptor write to m axi sg arvalid10m axi sg arvalid to m axi mm2s arvalid28m axi mm2s arvalid to m axis mm2s tvalid6S2MM ChannelTail Descriptor write to m axi sg arvalid10s axis s2mm tvalid to m axi s2mm awvalid39Table 2-2:AXI DMA Throughput Numbers (1)ChannelClock Frequency (MHz)MM2S (2)100LogiCORE IP AXI DMA v7.1PG021 April 27, 2022Bytes Transferred10,000www.xilinx.comTotal Throughput (MB/s)399.04Percent ofTheoretical99.76Send Feedback8
Chapter 2: Product SpecificationTable 2-2:AXI DMA Throughput Numbers (1) (Cont’d)ChannelClock Frequency (MHz)S2MM (3)100Bytes TransferredTotal Throughput (MB/s)10,000298.59Percent ofTheoretical74.64Notes:1. The preceding figures are measured with the default IP configuration.2. The MM2S throughput is measured between the first arvalid on Memory Map side to the tlast on streamingside.3. The S2MM throughput is measured between the first tvalid on streaming side to last wlast on the MemoryMap side.LogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback9
Chapter 2: Product SpecificationResource UtilizationFor full details about performance and resource utilization, visit thePerformance and Resource Utilization web page.Port DescriptionsThe AXI DMA I/O signals are described in Table 2-3.Table 2-3:I/O Signal DescriptionSignal NameInterfaceSignalTypes axi lite aclkClockIAXI4-Lite Clock.m axi sg aclkClockIAXI DMA Scatter Gather Clockm axi mm2s aclkClockIAXI DMA MM2S Primary Clockm axi s2mm aclkClockIAXI DMA S2MM Primary Clockaxi resetnResetIAXI DMA Reset. Active-Low reset. Whenasserted Low, resets entire AXI DMA core. Mustbe synchronous to s axi lite aclk.InterruptO0Interrupt Out for Memory Map to StreamChannel.InterruptO0Interrupt Out for Stream to Memory MapChannel.NAO0Debug signals for internal use.mm2s introuts2mm introutaxi dma tstvecInitStatusDescriptionAXI4-Lite Interface Signalss axi lite *S AXI LITEInput/OutputSee Appendix A of the AXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.MM2S Memory Map Read Interface Signalsm axi mm2s *M AXI MM2SInput/OutputSee Appendix A of the AAXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.MM2S Master Stream Interface Signalsmm2s prmry reset out nM AXIS MM2SOm axis mm2s *M AXIS MM2SInput/Output1Primary MM2S Reset Out. Active-Low reset.See Appendix A of the AXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.MM2S Master Control Stream Interface Signalsmm2s cntrl reset out nM AXIS CNTRLOm axis mm2s cntrl *M AXIS CNTRLInput/Output1Control Reset Out. Active-Low reset.See Appendix A of the AXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.S2MM Memory Map Write Interface SignalsLogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback10
Chapter 2: Product SpecificationTable 2-3:I/O Signal Description (Cont’d)Signal NameInterfaceSignalTypem axi s2mm *M AXI S2MMInput/OutputInitStatusDescriptionSee Appendix A of the AXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.S2MM Slave Stream Interface Signalss2mm prmry reset out nS AXIS S2MMO1Primary S2MM Reset Out. Active-Low reset.s axis s2mm *S AXIS S2MMIInput/OutputSee Appendix A of the AXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.S2MM Slave Status Stream Interface Signalss2mm sts reset out nS AXIS STSOs axis s2mm sts *S AXIS STSInput/OutputAXI Status Stream (STS) Reset Output.Active-Low reset.1See Appendix A of the AXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.Scatter Gather Memory Map Read Interface Signalsm axi sg *Input/OutputM AXI SGSee Appendix A of the AXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.Scatter Gather Memory Map Write Interface Signalsm axi sg*Input/OutputM AXI SGSee Appendix A of the AXI Reference Guide(UG1037) [Ref 2] for the AXI4 signal.Register SpaceThe AXI DMA core register space for Scatter/Gather Mode is shown in Table 2-4. The AXIDMA core register space for Direct Register mode is shown in Table 2-5. The AXI DMAregisters are memory-mapped into non-cacheable memory space. This memory space mustbe aligned on an AXI word (32-bit) boundary.Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (* wdata) signal,and is not impacted by the AXI Write Data Strobe (* wstrb) signal. For a Write, both the AXI WriteAddress Valid (* awvalid) and AXI Write Data Valid (* wvalid) signals should be assertedtogether.EndianessAll registers are in Little Endian format, as shown in Figure 2-1.X-Ref Target - Figure 2-1MSBLSBAddr Offset 0x0331BYTE3Addr Offset 0x022423BYTE2Addr Offset 0x0116 15BYTE 1Addr Offset 0x0087BYTE00X14584Figure 2-1:LogiCORE IP AXI DMA v7.1PG021 April 27, 202232-bit Little Endian Examplewww.xilinx.comSend Feedback11
Chapter 2: Product SpecificationAXI DMA Register Address MapTable 2-4:Scatter / Gather Mode Register Address MapAddress Space Offset(1)NameDescription00hMM2S DMACRMM2S DMA Control register04hMM2S DMASRMM2S DMA Status registerMM2S CURDESCMM2S Current Descriptor Pointer. Lower 32bits of the address.MM2S CURDESC MSBMM2S Current Descriptor Pointer. Upper 32bits of address.MM2S TAILDESCMM2S Tail Descriptor Pointer. Lower 32bits.MM2S TAILDESC MSBMM2S Tail Descriptor Pointer. Upper 32 bitsof address.SG CTLScatter/Gather User and Cache30hS2MM DMACRS2MM DMA Control register34hS2MM DMASRS2MM DMA Status registerS2MM CURDESCS2MM Current Descriptor Pointer. Lower 32address bitsS2MM CURDESC MSBS2MM Current Descriptor Pointer. Upper 32address bits.S2MM TAILDESCS2MM Tail Descriptor Pointer. Lower 32address bits.S2MM TAILDESC MSBS2MM Tail Descriptor Pointer. Upper 32address bits.08h0Ch10h14h2Ch(2)38h3Ch40h44hNotes:1. Address Space Offset is relative to C BASEADDR assignment.2. Register 2Ch is available only when DMA is configured in multichannel mode.Table 2-5:Direct Register Mode Register Address MapAddress Space Offset(1)NameDescription00hMM2S DMACRMM2S DMA Control register04hMM2S DMASRMM2S DMA Status register08h – 14hReservedN/A18hMM2S SAMM2S Source Address. Lower 32 bits ofaddress.1ChMM2S SA MSBMM2S Source Address. Upper 32 bits ofaddress.28hMM2S LENGTHMM2S Transfer Length (Bytes)30hS2MM DMACRS2MM DMA Control registerLogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback12
Chapter 2: Product SpecificationTable 2-5:Direct Register Mode Register Address Map (Cont’d)Address Space Offset(1)NameDescription34hS2MM DMASRS2MM DMA Status register38h – 44hReservedN/A48hS2MM DAS2MM Destination Address. Lower 32 bitaddress.4ChS2MM DA MSBS2MM Destination Address. Upper 32 bitaddress.58hS2MM LENGTHS2MM Buffer Length (Bytes)Notes:1. Address Space Offset is relative to C BASEADDR assignment.Memory Map to Stream Register DetailRegister Access Type Description RO Read Only. Writing has no effect R/W Read and Write Accessible R/WC Read / Write to ClearMM2S DMACR (MM2S DMA Control Register – Offset 00h)This register provides control for the Memory Map to Stream DMA Channel.X-Ref Target - Figure 2-2Dly IrqENRSVD312416 15 14 13 12 11 10 923Keyhole RSVD876RSVDIRQDelayIRQThresholdFigure 2-2:LogiCORE IP AXI DMA v7.1PG021 April 27, 2022ERR IrqENIOC IrqEN5 432ResetCyclic BD Enable10RSX14563MM2S DMACR Registerwww.xilinx.comSend Feedback13
Chapter 2: Product SpecificationTable 2-6:BitsMM2S DMACR Register DetailsField NameDefaultValueAccessDescriptionTypeRun / Stop control for controlling running and stopping of theDMA channel.0RS0R/W 0 Stop – DMA stops when current (if any) DMA operations arecomplete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. AXI4-Stream outs arepotentially terminated early. Descriptors in the update queueare allowed to finish updating to remote memory before enginehalt.For Direct Register mode pending commands/transfers areflushed or completed. AXI4-Stream outs are potentiallyterminated.The halted bit in the DMA Status register asserts to 1 when theDMA engine is halted. This bit is cleared by AXI DMA hardwarewhen an error occurs. The CPU can also choose to clear this bitto stop DMA operations. 1 Run – Start DMA operations. The halted bit in the DMAStatus register deasserts to 0 when the DMA engine beginsoperations.12ReservedReset10ROR/WWriting to this bit has no effect and is always read as 1.Soft reset for resetting the AXI DMA core. Setting this bit to a 1causes the AXI DMA to be reset. Reset is accomplished gracefully.Pending commands/transfers are flushed or completed.AXI4-Stream outs are potentially terminated early. Setting eitherMM2S DMACR.Reset 1 or S2MM DMACR.Reset 1 resets theentire AXI DMA engine. After completion of a soft reset, allregisters and bits are in the Reset State. 0 Normal operation. 1 Reset in progress.3Keyhole0R/WKeyhole Read. Setting this bit to 1 causes AXI DMA to initiateMM2S reads (AXI4read) in non-incrementing address mode (FixedAddress Burst transfer on AXI4). This bit can be updated when AXIDMA is in idle. When using keyhole operation the Max BurstLength should not exceed 16. This bit should not be set when DREis enabled.This bit is non functional when the multichannel feature is enabledor in Direct Register mode.4Cyclic BDEnable0R/WWhen set to 1, the DMA operates in Cyclic Buffer Descriptor (BD)mode without any user intervention. In this mode, the ScatterGather module ignores the 'Completed' bit of the BD. With this bitset, you can use the same BDs in cyclic manner without worryingabout any stale descriptor errors.This bit should be set/unset only when the DMA is idle or whennot running. Updating this bit while the DMA is running can resultin unexpected behavior.This bit is non functional when DMA operates in multichannelmode.LogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback14
Chapter 2: Product SpecificationTable 2-6:MM2S DMACR Register Details (Cont’d)BitsField NameDefaultValueAccessDescriptionType11 to 5Reserved0RO12IOC IrqEn0R/WWriting to these bits has no effect, and they are always read aszeros.Interrupt on Complete (IOC) Interrupt Enable. When set to 1,allows DMASR.IOC Irq to generate an interrupt out for descriptorswith the IOC bit set. 0 IOC Interrupt disabled 1 IOC Interrupt enabledInterrupt on Delay Timer Interrupt Enable. When set to 1, allowsDMASR.Dly Irq to generate an interrupt out.13Dly IrqEn0R/W 0 Delay Interrupt disabled 1 Delay Interrupt enabledNote: This bit is ignored when AXI DMA is configured for Direct RegisterMode.Interrupt on Error Interrupt Enable.14Err IrqEn0R/W 0 Error Interrupt disabled 1 Error Interrupt enabled1523 to 16ReservedIRQThreshold001hROWriting to this bit has no effect and it is always read as zeros.R/WInterrupt Threshold. This value is used for setting the interruptthreshold. When IOC interrupt events occur, an internal countercounts down from the Interrupt Threshold setting. When thecount reaches zero, an interrupt out is generated by the DMAengine.Note: The minimum setting for the threshold is 0x01. A write of 0x00 tothis register has no effect.Note: This field is ignored when AXI DMA is configured for DirectRegister Mode.Interrupt Delay Time Out. This value is used for setting theinterrupt timeout value. The interrupt timeout mechanism causesthe DMA engine to generate an interrupt after the delay timeperiod has expired. Timer begins counting at the end of a packetand resets with receipt of a new packet or a timeout event occurs.31 to 24IRQDelay00hR/W1 Timeout Interval 125 ( clock period of SG clock )Setting a value of 3 here results in a delay timeout of 125 x 3 x(clock period of SG clock).Note: Setting this value to zero disables the delay timer interrupt.Note: This field is ignored when AXI DMA is configured for DirectRegister Mode.LogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback15
Chapter 2: Product SpecificationMM2S DMASR (MM2S DMA Status Register – Offset 04h)This register provides the status for the Memory Map to Stream DMA Channel.X-Ref Target - Figure 2-3Dly IrqRSVD3124IRQDlySts23SGSlvErrRSVD16 15 14 13 12 11 10 210SGDecErr RSVDErr IrqSGIncldSGIntErr DMASlvErrIdleIOC IrqX14574Figure 2-3:Table 2-7:BitsMM2S DMASR RegisterMM2S DMASR Register DetailsField NameDefaultValueAccessDescriptionTypeDMA Channel Halted. Indicates the run/stop state of the DMAchannel. 0 DMA channel running.0Halted1RO 1 DMA channel halted. For Scatter / Gather Mode this bitgets set when DMACR.RS 0 and DMA and Scatter Gather(SG) operations have halted. For Direct Register mode(C INCLUDE SG 0) this bit gets set when DMACR.RS 0and DMA operations have halted. There can be a lag of timebetween when DMACR.RS 0 and when DMASR.Halted 1.Note: When halted (RS 0 and Halted 1), writing to TAILDESC PTRpointer registers has no effect on DMA operations when in ScatterGather Mode. For Direct Register Mode, writing to the LENGTHregister has no effect on DMA operations.DMA Channel Idle. Indicates the state of AXI DMA operations.For Scatter / Gather Mode when IDLE indicates the SG Enginehas reached the tail pointer for the associated channel and allqueued descriptors have been processed. Writing to the tailpointer register automatically restarts DMA operations. TheIDLE bit is associated with the BDs. The DMA may be in IDLEstate, there may be active data on the AXI interface.For Direct Register Mode when IDLE indicates the currenttransfer has completed.1Idle0RO 0 Not Idle. For Scatter / Gather Mode, SG has not reachedtail descriptor pointer and/or DMA operations in progress.For Direct Register Mode, transfer is not complete. 1 Idle. For Scatter / Gather Mode, SG has reached taildescriptor pointer and DMA operation paused. for DirectRegister Mode, DMA transfer has completed and controlleris paused.Note: This bit is 0 when channel is halted (DMASR.Halted 1). This bitis also 0 prior to initial transfer when AXI DMA configured for DirectRegister Mode.2ReservedLogiCORE IP AXI DMA v7.1PG021 April 27, 20220ROWriting to this bit has no effect and it is always read as zero.www.xilinx.comSend Feedback16
Chapter 2: Product SpecificationTable 2-7:MM2S DMASR Register Details (Cont’d)BitsField UDESGRO4DMAIntErr0RO1 Scatter Gather Enabled0 Scatter Gather not enabledDMA Internal Error. Internal error occurs if the buffer lengthspecified in the fetched descriptor is set to 0. This errorcondition causes the AXI DMA to halt gracefully. TheDMACR.RS bit is set to 0, and when the engine has completelyshut down, the DMASR.Halted bit is set to 1. 0 No DMA Internal Errors 1 DMA Internal Error detected. DMA Engine halts.Note: This bit is not used and is fixed at 0 when AXI DMA isconfigured for Direct Register Mode.5DMASlvErr0RODMA Slave Error. This error occurs if the slave read from theMemory Map interface issues a Slave Error. This error conditioncauses the AXI DMA to halt gracefully. The DMACR.RS bit is setto 0, and when the engine has completely shut down, theDMASR.Halted bit is set to 1. 0 No DMA Slave Errors. 1 DMA Slave Error detected. DMA Engine halts.6DMADecErr0RODMA Decode Error. This error occurs if the address requestpoints to an invalid address. This error condition causes theAXI DMA to halt gracefully. The DMACR.RS bit is set to 0, andwhen the engine has completely shut down, the DMASR.Haltedbit is set to 1. 0 No DMA Decode Errors. 1 DMA Decode Error detected. DMA Engine halts.78ReservedSGIntErr00ROROWriting to this bit has no effect, and it is always read as zeros.Scatter Gather Internal Error. This error occurs if a descriptorwith the “Complete bit” already set is fetched. Refer to theScatter Gather Descriptor section for more information.Thisindicates to the SG Engine that the descriptor is a staledescriptor. This error condition causes the AXI DMA to haltgracefully. The DMACR.RS bit is set to 0, and when the enginehas completely shut down, the DMASR.Halted bit is set to 1. 0 No SG Internal Errors. 1 SG Internal Error detected. DMA Engine halts.Note: This bit is not used and is fixed at 0 when AXI DMA isconfigured for Direct Register Mode.LogiCORE IP AXI DMA v7.1PG021 April 27, 2022www.xilinx.comSend Feedback17
Chapter 2: Product SpecificationTable 2-7:Bits9MM2S DMASR Register Details (Cont’d)Field atter Gather Slave Error. This error occurs if the slave readfrom on the Memory Map interface issues a Slave error. Thiserror condition causes the AXI DMA to halt gracefully. TheDMACR.RS bit is set to 0, and when the engine has completelyshut down, the DMASR.Halted bit is set to 1. 0 No SG Slave Errors. 1 SG Slave Error detected. DMA Engine halts.Note: This bit is not used and is fixed at 0 when AXI DMA isconfigured for Direct Register Mode.10SGDecErr0ROScatter Gather Decode Error. This error occurs if CURDESC PTRand/or NXTDESC PTR points to an invalid address. This errorcondition causes the AXI DMA to halt gracefully. TheDMACR.RS bit is set to 0, and when the engine has completelyshut down, the DMASR.Halted bit is set to 1. 0 No SG Decode Errors. 1 SG Decode Error detected. DMA Engine halts.Note: This bit is not used and is fixed at 0 when AXI DMA isconfigured for Direct Register Mode.1112ReservedIOC Irq00ROR/WCWriting to this bit has no effect, and it is always read as zeros.Interrupt on Complete. When set to 1 for Scatter/Gather Mode,indicates an interrupt event was generated on completion of adescriptor. This occurs for descriptors with the End of Frame(EOF) bit set. When set to 1 for Direct Register Mode, indicatesan interrupt event was generated on completion of a transfer.If the corresponding bit is enabled in the MM2S DMACR(IOC IrqEn 1) and if the interrupt threshold has been met,causes an interrupt out to be generated from the AXI DMA. 0 No IOC Interrupt. 1 IOC Interrupt detected.Writing a 1 to this bit clears it.Interrupt on Delay. When set to 1, indicates an interrupt eventwas generated on delay timer timeout. If the corresponding bitis enabled in the MM2S DMACR (Dly IrqEn
The AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its optional scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor-based systems. Initialization, status, and management registers are
PG 3 DMA-011 DMA-043 DMA-096 DMA-053 DMA-056 DMA-064 DMA-063 DMA-066 DMA-066B DMA-067 DMA-068 DMA-079 DMA-084 DMA-087 DMA-088
AXI Reference Guide www.xilinx.com 5 UG761 (v13.1) March 7, 2011 Chapter 1 Introducing AXI for Xilinx System Development Introduction Xilinx has adopted the Advanced eXtensible Interface (AXI) protocol for Intellectual Property (IP) cores beginning with the Sparta
Different DMA for each surface type. Slide courtesy of Santa Barbara County and Dan Cloak. 1225 SF Existing Impervious Area. DMA-1. 3200 DMA-2. 3200 DMA-3: 3700 DMA-4. 12400 DMA-5: 500 DMA-6. 8500 DMA-7: 4200 Total 35700 1225 SF Existing Impervious Area. Slide courtesy of Santa Barbara County and Dan Cloak. Sizing - Treatment Only. DMA Name .
This DMA General Certification Overview course is the first of five mandatory courses required for DMA certification: 1. DMA General Certification Overview 2. DMA Military Sexual Trauma (MST) and the Disability Examination Process 3. DMA Medical Opinions 4. DMA Aggravation Opinions 5. DMA Gulf War General Medical Examination
AXI Bridge for PCI Express v2.5 www.xilinx.com 8 PG055 November 19, 2014 Chapter 2 Product Specification Figure 2-1 shows the architecture of the AXI Bridge for PCI Express core. The Register block contains registers used in the AXI Bridge for PCI Express core for dynamically mapping the AXI4 memory mapped (MM) address range provided using the
“Video IP: AXI Feature Adoption” section of the AXI Reference Guide (UG761). AXI4 Data Width The AXI VDMA core supports the primary AXI4 data bus width of 32, 64, 128, 256, 512, and 1024 bits. AXI4‐Stream Data Width The AXI VDMA core supports the primary AXI4-S tre
DMA interrupt handler are implemented in emlib, but callbacks can be registered by application emlib DMA config includes DMA interrupt handler Callback functions registered during DMA config 17. Hands-on task 1 - Basic Mode 1. Open an\fae_training\iar\dma.eww and got to adc_basic project 2. Run code and check that DMA- CHREQSTATUS[0] is set to 1
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