CSCI 350 Ch. 2 - Kernel And User Mode

2y ago
18 Views
2 Downloads
804.43 KB
20 Pages
Last View : 3d ago
Last Download : 3m ago
Upload by : Ronan Orellana
Transcription

1CSCI 350Ch. 2- Kernel and User ModeMark Redekopp

2USER VS. KERNEL MODE

3Exceptions Any event that causes a break in normal execution Error Conditions Invalid address, Arithmetic/FP overflow/error Hardware Interrupts / Events Handling a keyboard press, mouse moving, USB data transfer, etc. We already know about these so we won't focus on these again System Calls / Traps User applications calling OS code General idea: When these occur, automatically callsome subroutine (a.k.a. "handler") to handle theissue, then resume normal processing

4Interrupt Exceptions Two methods for processor and I/O devices to notify each otherevents– WŽůůŝŶŐ ͞ďƵƐLJ͟ ůŽŽƉ ;ƌĞƐƉŽŶƐŝďŝůŝ Processor has responsibility of checking each I/O device Many I/O events happen infrequentlyms)( with respect to the processors abilityto execute instructions (ns) causing the loop to execute many times– Interrupts (responsibility on I/O device) I/O device notifies processor only when it needs attentionPolling: We can wait for a key press by continuouslyreading a status flag bit in the interface register (e.g.KEYCSR Keyboard Control/Status Register). Keepwaiting 'while' KPFlag bit is 0)With Interrupts: We can ask the Keyboardcontroller to "interrupt" the processor when itsdone so the processor doesn't have to sitthere pollingwhile((KEYCSR & (1 KPFlag)) 0);I/O Device (Keybd)Proc.KEYCSRI/O Device (Keybd)Proc.KEYCSRKPFlagKPFlagPolling LoopInterrupt

5User vs. Kernel Mode Kernel modeis a special mode of the processor for executing trusted (OS)code– Certain features/privileges are only allowed to code running in kernel mode– OS and other system software should run in kernel mode User modeis where user applications are designed to run to limit whatthey can do on their own– Provides protection by forcing them to use the OS for many services User vs. kernel mode determined somebybit(s)in some processor controlregister– x86 Architecture uses lower-bits2 in the CS segment register (referred to asthe Current Privilege Level bits [CPL])– 0 Most privileged (kernel mode)and 3 Least privileged (user mode) Levels 1 and 2 may also be used but are not by Linux On an exception, the processor will automatically switch tokernel mode

6Kernel Mode Privileges0xffffffff Privileged instructionsKernelSpace–hƐĞƌ ĂƉƉƐ͘ ƐŚŽƵůĚŶ͛ƚ ďĞ Ăůdisable/enable interrupts, changememory mappings, etc.0xc0000000 Privileged Memory or I/O access–Processor supports special areas ofmemory or I/O space that can only beaccessed from kernel mode Separate stacks and register setsUserSpace0x00000000Address–D/W ƉƌŽĐĞƐƐŽƌƐ ĐĂŶ ƵƐĞ ͞ƐSpaceƌĞŐŝƐƚĞƌ ƐĞƚƐ ;ĂůƚĞƌŶĂƚĞ 'kernel mode).

7Syscalls Provide a controlled method for user mode applications to callkernel mode (OS) code LJƐĐĂůů͛Ɛand traps are very similar to subroutine calls but theyswitch into "kernel" mode when called Provided a structured entry point to the OS– Really just a subroutine call that also switches into kernel mode– Often used to allow user apps. to request I/O or other services fromthe OS MIPS Syntax:syscall– Necessary arguments are defined by the OS and expected to be placein certain registers x86 Syntax: INT 0x80 (value between-2550 or 0x00-0xff)– Argument placed in EAX or on stack

8Exception Processing Now that you know what causes exceptions, whatdoes the hardware do when an exception occurs? Save necessary state to be able to restart the proces–Save PC of current/offending instruction Ăůů ĂŶ ĂƉƉƌŽƉƌŝĂƚĞ ͞ŚĂŶthe error / interrupt / syscall–Handler identifies cause of exception and handles it–May need to save more state Restore state and return to offending application (orkill it if recovery is impossible)

9Exception Processing Where will you be in your program code when an interrupt occurs? Ŷ ĞdžĐĞƉƚŝŽŶ ĐĂŶ ďĞ͙– Asynchronous (due to an interrupt or error)– Synchronous (due to a system call/trap) Must save PC of offending instruction, program state, and any information neededto return afterwards Restore upon returnSystem ExceptionUser ------------------------------------------Return fromexception

10Solution for Calling a Handler ŝŶĐĞ ǁĞ ĚŽŶ͛ƚ ŬŶŽǁ ǁŚĞŶ ĂŶ be a preset location where an exception handler should bedefined or some way of telling the processor in advance whereour exception handlers will be located Method 1: Single hardwired address for master handler– Early MIPS architecture defines that the exception handler should belocated at 0x8000 0180. Code there should then examine CAUSE regand then call appropriate handler routine Method 2: Vectored locations (usually for interrupts)– Each interrupt handler at a different address based on interrupt numbe(a.k.a. vector) (INT1 @ 0x80000200, INT2 @ 0x80000300) Method 3: Vector tables– Table in memory holding start address of exception handlers (i.e.overflow exception handler pointer at 0x0004, FP exception handlerpointer at 0x0008, etc.)

11Handler Calling 0180KernelSpaceINT n Hand.0x80000?INT 2 Hand.INT 1 ethod 10xffffffffKernelSpaceINT 2 Hand.x3Handler 1INT 1 Hand.x1x2addr x3addr x2addr x1Vector0x80000000 TableUserSpace0x00000000Method 20xffffffff0x00000000Method 3

12Problem of Changed State When an exception occurs and we call ahandler what could go wrong?f1:done:.textdeceaxjnzdone---------retWhat if an exception occurs at this pointin time? We’d want to call an exceptionhandler but executing that handler wouldoverwrite the EFLAGs register.

13Problem of Changed State x86 architecture will save stack pointer, programcounter (EIP), and EFLAGS register on the stackautomatically when an exception xceptiondec ecxoreax,ecx.iretHandlers need to save/restore values to stack to avoid overwriting neededregister values

14Problem of Changed State Other registers must also be pushed onto the onHAND:pushad.oreax,ecxWe don't know if the.interrupted app. waspopad using eax, edx, etc Weshould save them on theiretstack firstHandlers need to save/restore values to stack to avoid overwriting neededregister values

15Transition from User to Kernel Mode– Lower 2 bits in CS register store the CPL (currentprivilege level) where 0 Most privileged (kernelmode) and 3 Least privileged (user mode)0xffffffffMemoryHandler CodeGDTKernel mem. The process executing a user xeip0x000080a4edxcsKernel Stack0x800000000x7ffffc80eflagsCPUUser e0x0Process 1 ASUser mem.U

16Transition from User to Kernel Mode– HW enters kernel mode and disables interrupts– Temporary copies are made of the stack pointer,program counter (IP), and flags register0xffffffffMemoryHandler CodeGDTKernel mem. An interrupt s0xbffff8000x000080a40x7ffff400Kernel Stack0x000080a40x80000000KflagsCPU– Using the task segmenttr),( the hardware looks upthe kernel stack location and points theespto thatlocation0x7ffffc80User e0x0Process 1 ASUser mem.eax

17Transition from User to Kernel Mode– HW pushes user process'esp, eip, eflagsregister0xffffffffonto the stack– Loads eip with handler start address by looking it upin the interrupt vector ip0xe00010a4edxcsGDTesp 0x7ffff400eip 0x000080a4eflagsError code0x80000000KUser e0x0Process 1 ASUser mem.CPUHandler CodeKernel Stack0x7ffffc80eflagsMemoryKernel mem. HW updates the stack and basic registers

18Transition from User to Kernel Mode Handler saves remaining state– Pushes other registerseax( , ebx, etc.) onto the stack– Can now execute kernel mode0xffffffffMemoryHandler xeip0xe00010a4edxcs0x80000000Kernel StackUser e0x0Process 1 ASUser mem.CPUesp 0x7ffff400eip 0x000080a4eflagsError codeSaved RegistersK0x7ffffc80eflagsKernel mem.HAND:pushad.popadiret

19Transition from User to Kernel Mode When handler is done– Restores saved registerseax( , ebx, etc.)– Executesiret'' which pops off eflags, eip, espbackinto the registers– Mode is restored appropriately0xffffffffHandler xeip0x000080a4edxcs0x80000000Kernel StackUser e0x0Process 1 ASUser mem.CPUesp 0x7ffff400eip 0x000080a4eflagsError codeSaved RegistersU0x7ffffc80eflagsMemoryKernel mem.HAND:pushad.popadiret

20Summary Understand the purpose of the (at least) 2 modes of operation– User mode– Kernel mode Occurrence of an exception automatically causes kernel modeto be entered Understand how state is saved when an exception is triggered– There are usually 2 stacks (user mode and kernel stack) Understand how the vector table works and its purpose– Understand that a handler must be associated in the vector tablebefore exceptions start occurring

User vs. Kernel Mode Kernel mode is a special mode of the processor for executing trusted (OS) code – Certain features/privileges are only allowed to code running in kernel mode – OS and other system software should run in kernel mode User mode is where user applications a

Related Documents:

Anatomy of a linux kernel development Questions : – How to work kernel code? – How to write C code on the kernel? – How to building and install the kernel on old version linux? – How to release the linux kernel? – How to fixes bugs (patch) on kernel trees? Goal : –

CSCI 561 – Theory of Computation Dr. Neil T. Dantam CSCI-561, Colorado School of Mines Fall 2021 Dantam (Mines CSCI-561) Intro Fall 2021 1/32

What if Linux Kernel Panics Kexec: system call to load and boot into another kernel from the currently running kernel (4.9.74). crashkernel 128M [normal kernel cmdline] irqpoll, nosmp, reset_devices [crash kernel cmdline] --load-panic option Kdump: Linux mechanism to dump machine memory content on kernel panic.

Kernel Boot Command-Line Parameter Reference The majority of this chapter is based on the in-kernel documentation for the ichwerewrittenbythe kernel developers and released under the GPL. There are three ways to pass options to the kernel and thus control its behavior: When building the kernel.

n Linux is a modular, UNIX -like monolithic kernel. n Kernel is the heart of the OS that executes with special hardware permission (kernel mode). n "Core kernel" provides framework, data structures, support for drivers, modules, subsystems. n Architecture dependent source sub -trees live in /arch. CS591 (Spring 2001) Booting and Kernel .

General Purpose Strain Gages—Tee Rosette GAGE PATTERN DATA actual size GAGE DESIGNATION See Note 1, 3 RESISTANCE (OHMS) See Note 2 OPTIONS AVAILABLE See Note 3 EA-XX-050TG-350 WA-XX-050TG-350 EP-08-050TG-350 SA-XX-050TG-350 350 0.2% 350 0.4% 350 0.2% 350 0.4% L, LE DESCRIPTION Miniature high-

WEB4 - Posting Elevation Certificates. Up to 20 points. 350 - Flood Protection Information. Manual. Page 350-10. Visual 320. 11. Visual 350-11. 350 - Flood Protection Information. Documentation . Visual 320. 12. Visual 350-12. 350 - Flood Protection Information. Manual. Page 350-11. Credit calculation:

-Animal Nutrition Report Categories: CSSF Activity Report Approved By: James Johnson, Agricultural Affairs Officer Prepared By: Swe Mon Aung, Agricultural Specialist Report Highlights: In July 2019, FAS sent five Myanmar private feed millers and importers to the United States on a Cochran Fellowship Program to learn more about feed and feed ingredients available in the United States poultry .