EECE488: Analog CMOS Integrated Circuit Design Set 7
EECE488: Analog CMOS Integrated Circuit DesignSet 7Opamp DesignReferences: “Analog Integrated Circuit Design” by D. Johns and K. Martinand “Design of Analog CMOS Integrated Circuits” by B. RazaviAll figures in this set of slides are taken from the above booksShahriar MirabbasiDepartment of Electrical and Computer EngineeringUniversity of British Columbiashahriar@ece.ubc.caSMEECE488 Set 7 - Opamp Design1
General Considerations SMGainSmall-signal bandwidthLarge-signal performanceOutput swingInput common-mode rangeLinearityNoise/offsetSupply rejectionEECE488 Set 7 - Opamp Design2
One-Stage Op AmpsSMEECE488 Set 7 - Opamp Design3
One-Stage Op Amp in Unity GainConfigurationSMEECE488 Set 7 - Opamp Design4
Cascode Op AmpsSMEECE488 Set 7 - Opamp Design5
Unity Gain One Stage CascodeSMEECE488 Set 7 - Opamp Design6
Folded Cascode Op AmpsSMEECE488 Set 7 - Opamp Design7
Folded Cascode StagesSMEECE488 Set 7 - Opamp Design8
Folded Cascode (cont.)SMEECE488 Set 7 - Opamp Design9
Folded Cascode (cont.) Av gm1 {[(gm 3 gmb3 )ro3 (ro1 ro5 )] [(gm 7 gmb 7 )ro7 ro9 ]}SMEECE488 Set 7 - Opamp Design10
Telescopic versus Folded CascodeSMEECE488 Set 7 - Opamp Design11
Example Folded-Cascode Op AmpSMEECE488 Set 7 - Opamp Design12
Single-Ended Output Cascode Op AmpsSMEECE488 Set 7 - Opamp Design13
Triple CascodeAv app. (gmro)3/2Limited Output SwingComplex biasingSMEECE488 Set 7 - Opamp Design14
Output Impedance EnhancementRout A1 g m 2 ro 2 ro1SMEECE488 Set 7 - Opamp Design15
Gain Boosting in Cascode StageSMEECE488 Set 7 - Opamp Design16
Differential Gain BoostingSMEECE488 Set 7 - Opamp Design17
Differential Gain BoostingSMEECE488 Set 7 - Opamp Design18
Differential Gain BoostingSMEECE488 Set 7 - Opamp Design19
Two-Stage Op AmpsSMEECE488 Set 7 - Opamp Design20
Single-Ended Output Two-Stage Op AmpSMEECE488 Set 7 - Opamp Design21
Two-Stage CMOS Opamp Popular opamp design approachA good example to review many important design conceptsOutput buffer is typically used to drive resistive loadsFor capacitive loads (typical case in CMOS) buffer is notrequired.CV inA1Differentialinput stageSMc– A2Secondgain stageEECE488 Set 7 - Opamp Design1VoutOutputbuffer22
Two-Stage CMOS Opamp ExampleSMEECE488 Set 7 - Opamp Design23
Gain of the Opamp First StageDifferential to single-ended Second StageCommon-source stage SMOutput buffer is not required when driving capacitive loadsEECE488 Set 7 - Opamp Design24
Gain of the OpampThird Stage Source follower Typical gain: between 0.7 to1 Note: go 1/ro and GL 1/RL gmb is body-effect conductance (is zero if source can be tied tosubstrate)SMEECE488 Set 7 - Opamp Design25
Frequency ResponseQ5Vbias300vin Q1300vin–Q2300v1CCv2A3 1150vouti g m1 vin150Q3SMA3–A2Ceq CC ( 1 A 2 )Q4EECE488 Set 7 - Opamp Design26
Frequency ResponseSimplifying assumptions: CC dominates Ignore Q16 for the time being (it is used for lead compensation)Miller effect results in At midband frequenciesSMEECE488 Set 7 - Opamp Design27
Frequency Response Overall gain (assuming A3 1)which results in a unity-gain frequency of Note: ωta is directly proportional to gm1 and inverselyproportional to CC.SMEECE488 Set 7 - Opamp Design28
Frequency Response First-order model20 log ( A1 A 2 )– 20 dB/decadeGain(dB)ω ta gm 1 C CFreq0ωp 1ω ta(log)ωp 10ω taPhaseFreq(log)(degrees)– 90– 180SMEECE488 Set 7 - Opamp Design29
Slew Rate Maximum rate of output change when input signal is large.Q5Vbias300vin Q1300vin–Q2300v1CCv2A3 1–A2150A3vouti g m1 vin150Q3Q4 All the bias current of Q5 goes either into Q1 or Q2.SMEECE488 Set 7 - Opamp Design30
Slew RateSMEECE488 Set 7 - Opamp Design31
Slew Rate Normally, the designer has not much control over ωta Slew-rate can be increased by increasing Veff1 This is one of the reasons for using p-channel input stage:higher slew-rateSMEECE488 Set 7 - Opamp Design32
Systematic Offset Voltage To ensure inherent (systematic) offset voltage does not exist,nominal current through Q7 should equal to that of Q6 when thedifferential input is zero.Q5VDD300VbiasQ6300I b ia sQ1Vin –Q2300Vin 300Vo ut300150150Q3SMQ4VSSEECE488 Set 7 - Opamp DesignQ733
Systematic Offset Voltage Avoid systematic offset by choosing: Found by notingandthen settingSMEECE488 Set 7 - Opamp Design34
N-Channel versus P-Channel Input Stage Complimentary opamp can be designed with an n-channel inputdifferential pair and p-channel second-stage Overall gain would be roughly the same in both designsP-channel Advantages Higher slew-rate: for fixed bias current, Veff is larger (assumingsimilar widths used for maximum gain) Higher frequency of operation: higher transconductance ofsecond stage which results in higher unity-gain frequency Lower 1/f noise: holes less likely to be trapped; p-channeltransistors have lower 1/f noise N-channel source follower is preferable (less voltage drop andhigher gm)N-channel Advantage Lower thermal noise — thermal noise is lowered by hightransconductance of first stageSMEECE488 Set 7 - Opamp Design35
Feedback and Opamp CompensationYH ( s)( s) X1 βH ( s ) Feedback systems may oscillate The following two are the oscillation conditions: βH ( jω ) 1 βH ( jω ) 180SMEECE488 Set 7 - Opamp Design36
Stable and Unstable SystemsSMEECE488 Set 7 - Opamp Design37
Time-domain response of a feedback systemSMEECE488 Set 7 - Opamp Design38
One-pole systemH ( s) A01 sω0A01 β A0Y( s) sX1 ω 0 (1 βA0 )S p ω 0 (1 β A0 )Bode plot of the Loop gainSMEECE488 Set 7 - Opamp Design39
Multi-pole system0.1ω p 2 10ω p1Bode plot of the Loop gainSMEECE488 Set 7 - Opamp Design40
Phase Margin-20 dB/decadeLoop Gain(dB)20 log (LG (j ω))0ωtωp 1Freq(log)GM(gain margin)ωp 1PhaseωtFreq(log)0Loop Gain(degrees)–90PM(phase margin)–180SMEECE488 Set 7 - Opamp Design41
Phase Marginβ H ( ω1 ) 1 e j175Y11.5(s) XβClosed loop frequency responseSMEECE488 Set 7 - Opamp Design42
Phase Margin (Cont.)PM 180 βH ( ωGX )Phase Margin 45 SMEECE488 Set 7 - Opamp Design43
Phase Margin (Cont.)Phase Margin 45 SMEECE488 Set 7 - Opamp Design44
Phase Margin (Cont.) SMAt PM 60o results in a small overshoot in the step response.If we increase PM, the system will be more stable but the timeresponse slows down.EECE488 Set 7 - Opamp Design45
Frequency Compensation Push phase crossing point out Push gain crossing point inSMEECE488 Set 7 - Opamp Design46
Telescopic Opamp (single-ended) -exampleSMEECE488 Set 7 - Opamp Design47
Compensation (Cont.) Assume we need a phase margin of 45o (usuallyinadequate) and other non-dominant poles are at highfrequency.SMEECE488 Set 7 - Opamp Design48
Compensation of a two-stage opampMiller Effectf pE SMCeq CE (1 Av 2 )CC12πRout [CE (1 Av 2 )CC ]EECE488 Set 7 - Opamp Design49
Compensating Two-Stage OpampsQ5Vbias1300VDDQ1300Q2300Vin-Q6Vin 300Vout2Vbias2Q16Cc300150150Q3SMQ4EECE488 Set 7 - Opamp DesignQ750
Compensating Two-Stage Opampsvgvm1 inR11C1RCCCgvm7 1R2C2 Q16 has VDS16 0 therefore it is hard in the triode region. Small signal analysis: without RC, a right-half plane zero occursand worsens the phase-margin.SMEECE488 Set 7 - Opamp Design51
Compensating Two-Stage Opamps Using RC (through Q16) places zero at Zero moved to left-half plane to aid compensation Good practical choice is satisfied by lettingSMEECE488 Set 7 - Opamp Design52
Design ProcedureDesign example: Find CC with RC 0 for a 55o phase margin– Arbitrarily choose C’C 1pF and set RC 0– Using SPICE, find frequency ωt where a –125 phase shiftexists, define gain as A’– Choose new CC so ωt becomes unity-gain frequency of theloop gain, resulting in a 55o phase margin.Achieved by setting CC CCA’– Might need to iterate on CC a couple of times using SPICESMEECE488 Set 7 - Opamp Design53
Design ProcedureNext: Choose RC according to– Increasing ωt by about 20 percent, leaves zero near final ωt– Check that gain continues to decrease at frequencies above thenew ωtNext: If phase margin is not adequate, increase CC while leavingRC constant.SMEECE488 Set 7 - Opamp Design54
Design ProcedureNext: Replace RC by a transistorSPICE can be used for iteration to fine-tune the devicedimensions and optimize the phase margin.SMEECE488 Set 7 - Opamp Design55
Process and Temperature Independence Can show non-dominant pole is roughly given by Recall zero given by If RC tracks inverse of gm7 then zero will track ωp2:SMEECE488 Set 7 - Opamp Design56
Process and Temperature Independence Need to ensure Veff16/Veff7 istemperature variationsQ11VbiasQ12independent of process andQ62530025Va25Q16CCQ13300VbVbQ7 First set Veff13 Veff7 which makes Va VbSMEECE488 Set 7 - Opamp Design57
Process and Temperature IndependenceSMEECE488 Set 7 - Opamp Design58
Stable Transconductance BiasingSMEECE488 Set 7 - Opamp Design59
Stable Transconductance Biasing Transconductance of Q13 (to the first order) is determined bygeometric ratios only. Independent of power-supply voltages, process parameters,temperature, etc. For special case (W/L)15 4(W/L)13gm13 1/RB Note that high-temperature will decrease mobility and henceincrease effective gate-source voltages. Roughly 25% increase for 100 degree increase Requires a start-up circuit (might have all 0 currents)SMEECE488 Set 7 - Opamp Design60
EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design SM 1 EECE488 Set 7 - Opamp Design References: “Analog Integrated Circuit Design” by D. Johns and K. Martin and “Design of Analog CMOS Integrated Circuits” by B. Razavi All figures in this set of
EECE488: Analog CMOS Integrated Circuit Design Set 2: Background Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British Columbia shahriar@ece.ubc.ca Technical contributions of Pedram Lajevardi in revising the slides is greatly acknowledged. SM 2 EECE 4
SOI CMOS technology has been used to integrate analog circuits. In this section, SOI CMOS op amp is discussed. Then, the performance comparison of op amps using bulk and SOI CMOS technologies is presented. 3.1 Analysis on SOI CMOS Op amp Figure 5 shows an SOI CMOS single stage op amp with a symmetrical topology. This circuit has a good .
analog CMOS circuit design." We'll also introduce circuit simulation using SPICE (simulation program with integrated circuit emphasis). The introduction will be used to review basic circuit analysis and to provide a quick reference for SPICE syntax. 1.1 The CMOS IC Design Process The CMOS circuit design process consists of defining circuit .
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8. n-CH Pass Transistors vs. CMOS X-Gates 9. n-CH Pass Transistors vs. CMOS X-Gates 10. Full Swing n-CH X-Gate Logic 11. Leakage Currents 12. Static CMOS Digital Latches 13. Static CMOS Digital Latches 14. Static CMOS Digital Latches 15. Static CMOS Digital Latches . Joseph A. Elias, PhD 2
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