Interrupts And Stack Intro - UTEP

Interrupts and Stack IntroEE3376

Intro to Stackl l l l Last In – First Out LIFO structure with hardware assistl Dedicated SP pointing to TOSl One push instruction and one emulated pop instructionl All other addressing modes work as wellMust be initialized in ASM but handled under the covers for Cl The first address loaded in SP is never used.Usedl for local (temporary) variablesl for saving snapshot of registers to use temporarilyl for saving the PC and SR during interruptsGenerally just a great way to save things for short periodl Can easily de-allocate memory for other use

Intro to Stack - Push

Intro to Stack - Example

Intro to Stack - Pop

Example of Stack usage

Example of local variables

InterruptsSystem-On-Chip lsA/D converterSerialParallelTimePWMConsolidatedMemory

Interrupt Overviewl l l l Interrupts (a.k.a. exceptions) are requests to the CPUTypical example is hardware requesting serviceAvoids wasteful polling – CPU is unproductive during polling.Some sources of interrupts are intentionall l l l from internal sources (i.e. Timer or ADC sample completion)from external sources (i.e. NMI pin)from reset assertion (highest priority)Some sources of interrupts are not necessarily intentionall from instructions (i.e. illegal instruction - trap)from a variety of illegal hardware conditions (bad clock or Vdd)l Watch Dog Timeoutl l When they will occur is unknown to the CPU – asynchronousDifferent priority levels for interruptsl Most interrupts are mask-able and need to be armed.l

Interrupt Service Routine (Handler)l Interrupt cause the ISR to be executed when –––the interrupt is armed (interrupt specific arm bit is set – P1IE)interrupts in general are enabled (GIE is set in SR)and the interrupt signal is asserted (either internally or externally)l For each type of interrupt, there is an entry in the interrupt vectorl An Interrupt Service Routine (ISR) is like a special subroutine.–––––current instruction in main program is completedtypically need to clear the interrupt source with an acknowledgeexecute an rti instruction (not an rts for subroutine)all registers are restored after executionmain program resumes as if nothing happened

Interrupt Activities

RETI instruction

Interrupt Vector Table

Interrupt Examplesl Servicing data transfers for data communication peripherals–––l To perform periodic tasks using Timer interrupts––l Blinking LED (once a second)LCD display update (60 Hz)To handle unexpected software or hardware problems–––l UART buffer full and transmit completeUART receive buffer full and transmit completeIICmissing clocklow Vddbad instructionReset is a fundamental interrupt requesting to start over–Unmaskable, highest priority and no reti

Interrupt flow

Interrupt Prioritiesl For real time embedded systems, some interrupts have to behandled in a specific amount of time (real time constraint)l Analog has hard timing requirementsl Anti-lock brakes in a car need sense of urgencyl Playing Tetris – not so important – humans are slowl These interrupts get priority and can interrupt current interrupts.l Maskable interrupts also have individual bits that should set firstl GIE enables all maskable interruptsl l This bit should be set last at the end of the configurationIndividual bits control the (non)-maskable interruptsl non is in parenthesis because technically they can be maskedl Just not affected globally with the GIE bit.

MSP430 Priorities

Interrupt Flowisr2:entry:isr1:one time lessloop)retireti

Stack Pushing Prior to Interruptl Processors can take two approaches for “saving context”l Save everything – safer – all registers stacked - Motorolal Save minimum – let user save anything that could changel Faster - MSP430 uses the second approach so beware.

Stack Pushing Prior to Interruptl l l l l PC is pushed on stackSR is pushed on stackSR is cleared (GIE and low power modes remembered)Jump to Interrupt Handler location described in Interrupt VectorGIE is turned off for during handler

Interrupt Acknowledgingl Must clear the flag of any interrupt during the handlerl Otherwise, you will repeat the interruptl Other processors usually require clearing the flagl MSP430l No requirement for acknowledging for single source IRQsl For multi-source IRQs – Timer for instance – you will mustclear manually

Interrupt Synchronizationl Different software threads are executing––main program is considered foreground threadinterrupts are background threadsl Global variables are used to communicate between theml Global variables have dedicated space in SRAMl Different global data structures can be used–––l mail boxFIFOlinked listLocal variables are not allowed for passing data.–can’t use the stack because the threads are asynchronous

Nested Interrupt FlowNMIIRQmain programISRISRISRNMIThree software threads with only one active at a time.Interrupts are a hardware mechanism to switch between threads.To get second maskable interrupt in interrupt, the first handlermust enable GIE. NMI will always interrupt a maskable interrupt.

First-In First Out (FIFO) data structurel l FIFOs are useful structures for consumer-producer applicationsconsumer-producer apps–––l l Some finite amount of memory is dedicated to FIFOTwo pointers are used–––l l l data flow in one directionorder of data is importantallows producer to get X bytes ahead of consumer without problem.get pointer – controlled by the consumer (main program)put pointer – controlled by the producer (interrupt handler)get pointer chases put pointerPointers wrap around to the beginning if they extend boundaryIf get pointer put pointer after a get, FIFO emptyIf get pointer put pointer after a put, FIFO overflow

First-In First Out (FIFO) data tempty

Interrupt Service Routine (Handler) ! Interrupt cause the ISR to be executed when – the interrupt is armed (interrupt specific arm bit is set – P1IE) – interrupts in general are enabled (GIE is set in SR) – and the interrupt signal is asserted (either internally or externally) For each typ