PHY 351/651 - LABORATORY 9 Digital Electronics The Basics

PHY351/651DIGITAL ELECTRONICS – THE BASICS - LAB 9connection between the systems). There are several different ways to input the 4-bitnumber of your choice. I would first like you to do so by using 4 Boolean LED controlson the front panel of the VI. After you’ve gotten this to work successfully, you shouldtry simply typing an integer into a digital control.2.Next use LabVIEW to output in succession all integers from 1 to 255 and have themdisplayed on your LED indicators.3. Afterwards use LabVIEW to configure a single digital line to output a square TTL wavewith frequency and phase of your choice.4. Finally, use LabVIEW to read four digital lines and display the logic levels on LEDindicators. Demonstrate that this works by setting the input digital signals using the logicswitches on the PB503.**For your lab report:Include a screenshot of the front panel and diagram of each of the VI’s in this activity.Activity 3 – The 2-Bit Full Adder and SubtractorIn this activity, you will take what you learned about logic gates in Activity 1 and combine thatwith what you learned about digital I/O with LabVIEW in Activity 2 in order to implement animportant mathematical operation – either addition or subtraction of two numbers. Specifically,you have the option of implementing either a full 2-bit adder or a 2-bit subtractor (Figs. 2a and2b).Before implementing either of these circuits, it’s helpful to understand how logic gates can beused to perform computation. Figure 4 illustrates what is known as a half adder; the figure alsoincludes the associated truth table for the computation - I should note that the only difference inoperation between the full adder and the half adder is that the full adder is capable of accepting acarry from a previous stage in the circuit. You should spend some time working through the truthtable for the half adder on your own and also spend time understanding how the table representsthe addition of two bits. It may be helpful to note that binary addition works the same way asdecimal addition except that each digit can only take on two values. Thus, for example, 0 0 00; and 0 1 01; but 1 1 10 (a 1 gets carried to the next significant digit).To proceed with Activity 3: (1) Choose either the full adder or the subtractor. (2) Work throughthe truth table for the circuit (for an input carry of both 0 and 1). (3) Then build the circuit on thePB503. (4) Use LabVIEW to apply the input bits A and B and to measure the output bits Sumand Carry. (5) Verify the truth table for the circuit. Note that some of the ICs that you use mightrequire an external pull up resistor on their outputs, so be sure to read the datasheets carefully.Finally, this circuit (either the adder or the subtractor) is probably the most complicated circuitthat you have constructed and operated thus far in the class. So don’t get discouraged if it takes awhile to debug everything and have your circuit operating correctly. When you’re finished,you’ll probably be happy to know that if you ever need to build an adder or subtractor in thefuture, you won’t need to go to the lengths you did today – you can simply buy an IC that doesthe task for you (and with a much larger number of bits!).PHY 351/651 LAB 9Page 6

PHY351/651DIGITAL ELECTRONICS – THE BASICS - LAB 9Figure 4: Taken from Diefenderfer Figure 13.2. The truth table and schematic of a half adder. Be sureto fully understand this circuit before proceeding with construction of the full adder.**For your lab report: Include the truth table for the circuit that you decide to construct (either the full adder orthe subtractor), and discuss the operation of the circuit. Discuss whether your circuit operated in the manner that you expected.Activity 4 – Flip-FlopsFlip-flops (FF) are essential building blocks in digital circuits. They can be built from basicgates, and have many applications, including use as basic memory elements, as components incounters, and as elements for transferring bits of data in shift registers. In this activity, you willinitially build and operate several important digital flip-flops using an array of NAND gates.You will then operate and characterize the widely-used and versatile JK flip-flop. These initialsub-activities will serve to provide you with an understanding of how flip-flops function, whattheir truth tables are, etc. Then in the final two sub-activities, you will utilize JK flip-flops tobuild a count-to-16 binary counter and a 4-bit shift register.The clocked RSFF (reset-set flip-flop)Figure 5 illustrates the first flip-flop that you will build and characterize. This circuit is knownas the clocked reset-set flip-flop (RSFF) - it is also known as a gated set-reset latch. Tounderstand how the circuit functions, first notice that it is composed solely of NAND gates. Thefirst set of two NAND gates accepts three input signals: S (SET), R (Reset), and C (Clock), withthe Clock signal applied to both NANDs. The outputs of these first two NANDs are routed toPHY 351/651 LAB 9Page 7

PHY351/651DIGITAL ELECTRONICS – THE BASICS - LAB 9Figure 5: From Diefenderfer, Figure 12.2. A circuit schematic of a reset-set flip-flop (RSFF) constructedfrom NAND gates. In Activity 4, you should construct this circuit and verify the associated truth table.two more NAND gates, which are both configured to accept each other’s output as secondinputs. You should stop here and convince yourself that this sort of feedback results in the twooutputs being the logical inverses of one another (denoted 𝑄 and 𝑄).Now, the first important thing to note is that if the clock signal is zero (𝐶 0), then 𝑄 and 𝑄remain constant no matter what is applied to S and R. In such a state the FF is said to be disabledor inactive. Moreover, you can think of the FF in this state as acting like a latch preserving anearlier value of 𝑄 (and 𝑄).The second important thing to note is that one can control the value of 𝑄 (and 𝑄) by setting theclock to logical one (𝐶 1). In such a state, the FF is said to be enabled or active; and theoutput values (𝑄 and 𝑄) can be controlled by either changing the value of input S to logical oneor by changing the value of input R to logical one. For instance, if S 1 and R 0, you shouldconvince yourself that 𝑄 1 (and 𝑄 0). This is referred to as setting the RSFF to 1.Alternatively, if S 0 and R 1, then 𝑄 0 (and 𝑄 1). This is referred to as resetting theRSFF to 0. Of course, once the RSFF has been set or reset, it can then be disabled by settingC 0, whereby the output value is latched until the RSFF is enabled again.For this lab exercise: Construct an RSFF using one of the available NAND gate ICs that we have in the class(options include the 74HC03N and the 74LS00N; these both have four 2-input NANDgates per chip).PHY 351/651 LAB 9Page 8

PHY351/651 DIGITAL ELECTRONICS – THE BASICS - LAB 9Use either LabVIEW or the digital indicators and switches on the 503 board to verify thetruth table for the RSFF (Fig. 5). Be sure in particular to demonstrate the latchingbehavior.The DFF (data flip-flop)As you have probably already realized, with slight modification of the clocked RSFF, as shownin Fig. 6, one can make a simple one-bit memory element. This is known as the data flip-flop(DFF). In the DFF configuration, there are only two inputs: the data input (D) and the clock input(C). Just like with the RSFF, the clock signal (C) dictates whether the DFF is active (𝐶 1) ordisabled (𝐶 0). When the DFF is active, the output Q takes on the value of the input D(obviously either 0 or 1). And when the DFF is disabled, the output is latched, preserving theprepared value of Q until the DFF is activated again. Thus one can use this simple circuit has aone bit storage unit. Importantly, because the circuit is disabled and activated by the externalclock signal, one can synchronize this circuit with other circuits and thus build up an array ofmemory elements.For this lab exercise: Modify the RSFF from the previous exercise to construct a DFF. Use either LabVIEW or the digital indicators and switches on the 503 board to verify thetruth table for the DFF (Fig. 5). Make sure to investigate how the clock enables anddisables the DFF.The TFF (toggle flip-flop)The circuit in Fig. 7 illustrates one version of a device known as a toggle flip-flop (or TFF). Theoutput values of 𝑄 and 𝑄 change state every time there is a negative clock transition (i.e. C goesfrom 1 to 0). This circuit is essential for counters (as you will see in the next exercise withJKFFs). As well, it can be used for frequency division. (For example, if one feeds a TTL squarewave with frequency f into the Clock input, the output values 𝑄 and 𝑄 will toggle withfrequency f/2; stringing multiple TFFs in series, once can divide the initial clock frequency byany arbitrary factor of two.To understand how the TFF in Fig. 7 works, it’s important to realize that essentially you havetwo RSFFs in series, with the additional feature that the outputs of the second RSFF are fed backto the inputs of the first RSFF; this is done in such a manner that 𝑄 is fed to input S and 𝑄 is fedto input R. With this configuration, S and R always take on opposite values and toggle between0 and 1 on each clock cycle. Looking at the RSFF truth table in Fig. 5, this behavior results in 𝑄and 𝑄 toggling on every downward transition of the clock.You might be wondering why the output values toggle on the downward transition of the clockfor this circuit. The key to understanding this is to realize that the two RSFFs are in a so-called“master-slave” configuration, where the first RSFF (the master) transitions on a positive clockedge and the second RSFF (the slave) transitions on a negative clock edge. The relative timing ofthe master and slave RSFFs is arranged by inverting the clock signal before it is fed to the slaveRSFF (as shown in the diagram).PHY 351/651 LAB 9Page 9

PHY351/651DIGITAL ELECTRONICS – THE BASICS - LAB 9Figure 6: From Diefenderfer Fig. 12.4. A circuit schematic of a data flip-flop (DFF) and its associatedtruth table. Such circuits can be used a basic memory elements for devices like shift registers. You areto build this circuit in Activity 4.Output toggleFrequency f/2MasterRSFFSlaveRSFFClockFrequency fFigure 7: Adapted from Diefenderfer Fig. 12.5. A circuit schematic of a toggle flip-flop (TFF) constructedfrom two RSFFs in master-slave configuration. Such FFs are essential for counters. As well they are usedfor frequency division – here the output toggle frequency is ½ the clock frequency. As such this circuit isknown as a divide-by-two counter.PHY 351/651 LAB 9Page 10

PHY351/651DIGITAL ELECTRONICS – THE BASICS - LAB 9(a)(b)DFigure 8: Adapted from Diefenderfer’s Fig. 12.7. (a) The circuit symbol and truth table for the JK flip-flopthth(JKFF). The parameters 𝒕𝒏 and 𝒕𝒏H𝟏 refer to the n and (n 1) clock cycle respectively. (b) The JKFF can bemodified to function as a DFF by simply inverting the input and routing it to the K terminal. You are to usethese JK flip-flops in Activity 4 to build a binary counter and a shift register.For this lab exercise: Start with either the RSFF from the first exercise or the DFF from the previous exerciseand construct a TFF. Use LabVIEW to verify the behavior of the TFF. In particular show that the output valuestoggle at ½ the frequency of the clock. To do this, input a TTL wave at a frequency ofyour choice to the clock and record the output using your digital oscilloscope VI.**For your lab report: Provide a screen shot of a measurement of the frequency division using a TFF. Also provide a discussion on the difference in operation of the DFF and the TFF circuitsand for what applications they might be useful.The JK flip-flopPerhaps the most widely-used and versatile flip-flop is the JK flip-flop (JKFF). While I will notrequire that you understand its operation in terms of the basic logic gates that compose it, youshould take a look at a schematic of the particular JKFF that you will be using in this lab (thePHY 351/651 LAB 9Page 11

PHY351/651DIGITAL ELECTRONICS – THE BASICS - LAB 974HC76N), which can be found in the data sheet for the device, in order to get an idea of itscomposition. Essentially the JK flip-flop augments the behavior of the SR flip-flop (J Set,K Reset) by interpreting the J K 1 condition as a "flip" or toggle command. Specifically, thecombination J 1, K 0 is a command to set the flip-flop; the combination J 0, K 1 is acommand to reset the flip-flop; and the combination J K 1 is a command to toggle the flipflop, i.e., change its output to the logical complement of its current value. Setting J K 0maintains the current state.Shown in Fig. 8a are the truth table and circuit symbol for JKFFs. These you should learn andknow well. In fact, the versatility of the JKFF can be appreciated by looking at these. Forinstance, if one fixes the J and K inputs so that 𝐽 𝐾 1, then the JKFF acts like a TFF withoutputs 𝑄 and 𝑄 toggling between 0 and 1 on each downward clock edge. (Note: some JKFFsare engineered to toggle on the positive clock edge. The one you will use today transitions on thenegative edge, but you should always check the specs just to be sure.) In a few minutes you willuse several of these JKFFs in TFF mode to create a binary counter.Alternatively, if one makes the modification shown in Fig. 8b, the JKFF will act like a DFF, witha single input D, which can be transferred to the output Q on a negative clock edge and storedtemporarily.Before you start working with this device, there are a couple of other things that should be pointedout. First, the SET terminal is used to set the output value Q to one (𝑄 1). You should look inthe specs to confirm, but this should occur when SET 0 for the 74HC76N. It should be notedthat the SET input overrides the J, K and clock inputs. So make sure you change SET back to oneafter setting the output. Finally, the RESET terminal is used to set the output value of Q to zero(𝑄 0). For the 74HC76N, this occurs when RESET 0. Just like with the SET function, theRESET function will override the J, K, and clock inputs, so be sure to set it to one after resetting.For this lab exercise: Verify the truth table for the JKFF. Be sure to also explore the SET and RESET functions.It may be simplest to do this using a digital oscilloscope and input TTL to the clock (ratherthan trying to see it on the LEDS on the 503; but it’s up to you). Use several JKFFs in TFF mode to create a count-to-16 binary counter.I’m not going to give you the exact circuit schematic. But to aid your design, I’ve provideda picture of a count-to-4 binary counter in Fig. 9a. You can see in this design that the Jand K inputs on each of the JKFFs are set to one, so the JKFFs each act as TFFs. Moreover,the Q output of the first JKFF is fed into Clock input of the second JKFF. As a result ofthis, the second JKFF undergoes one toggle in output value for every two toggles of theoutput of the first JKFF. In this manner, the frequency of the output signal from the counteris ¼ the input clock frequency. Additionally, for each input clock cycle a binary number isproduced by the two cells (JKFFs). For the count-to-4 counter the numbers cyclesequentially between 0,1,2 & 3.Use LabVIEW to record and decode the counter in real-time. If you have trouble usingLabVIEW to do this, then just use the logic indicators on the 503 board. After verifyingthe counter’s operation, take a look at the frequency division of the output signals fromyour array of JKFFs. You can do this using a digital scope.PHY 351/651 LAB 9Page 12

PHY351/651 DIGITAL ELECTRONICS – THE BASICS - LAB 9Use four JKFFs in DFF mode to build a 4-bit serial shift register (Fig. 9b). Shift registersare used to transfer data between elements in a network. For the case of the circuit in Fig.9b, the JKFFs are wired in series, and thus data introduced at the first JKFF (either a oneor zero) propagates along the chain of JKFFs, moving from one FF to the next on eachnegative edge of the clock.Use LabVIEW to record the operation of the shift-register in real-time. Again, if you havedifficulty using LabVIEW to do this, simply use the LED logic indicators on the 503 board.One thing to note is that we only have a couple of the 74HC76N dual JKFF ICs in the lab. Thussome of you will have to use the SN74LS76AN. For the latter IC, SET is referred to as PRE andRESET is referred to as CLR in the datasheet.**For your lab report: Show a screen shot of your LabVIEW program for recording the count-to-16 counter (youshould have it showing the number 16). If you were not able to decode the counter, thendescribe the operation of the counter (as measured using the LED indicators) and discussthe frequency division that you observed using the digital scope. Show a screen shot of your LabVIEW program for recording the operation of the shiftregister. Research and discuss the importance of counters and shift registers in digital computers.(a)(b)𝑄"ClockFrequency f𝑄#𝑄" ToggleFrequency f/2𝑄# ToggleFrequency f/4DataInClock PulsestimeFigure 9: Adapted from http://hyperphysics.phy-astr.gsu.edu/. (a) Schematic of a 2-bit binary countermade from two JKFFs. For operation, J K 1. Operation described in the text. (b) Schematic of a 4-bitserial shift register made from 4 JKFFs. All JKFFs are initialized with output equal to zero (A B C D 0).Then a pulse (a one) is sent into the Data terminal. On the next positive clock edge, this toggles the outputof the first JKFF to one (A 1). The output A is fed into terminal J of the second JKFF. Then on the nextpositive clock edge, the output of the second JKFF toggles to one (B 1). And so on, until the data istransferred to the end of the register.PHY 351/651 LAB 9Page 13

PHY351/651DIGITAL ELECTRONICS – THE BASICS - LAB 9Activity 5 – The 555 Timer and DAQ Counters*For PHY 651 (Optional for PHY 351)*The 555 Timer, Fig. 10a, is a classic IC that is used by scientists, engineers and hobbyists alike formany applications including pulse generation, timing circuits and waveform generation. In fact,whole books have been dedicated to this device (see the following website for a list of suchreferences: http://www.sentex.ca/ mec1995/gadgets/555/555.html).In this activity, you willlearn about two different modes of operation of the 555: the astable mode, which is used forgenerating square wave oscillations with controlled frequency and duty cycle; and the monostablemode, which is used for generating individual pulses and finite pulse trains.The 555 in astable modeFigure 10b illustrates the appropriate circuit connections for operating the 555 in astable mode. Inthis mode, the 555 essentially acts as a square wave oscillator. One can understand how this modeworks by first looking at the simplified internal circuit schematic for the 555 in Fig. 10a andnoticing several important things. (1) Terminal 7 is connected to the collector of a BJT switch(remember Lab6?); when the base of the BJT is low, terminal 7 is an open circuit; when the baseof the BJT is high, terminal 7 is a short to ground. (2) Whether the BJT base is low or high iscontrolled by the 𝑄 output of a flip flop, which itself is controlled by two inputs S and R. Finally,(3) whether S and R are high or low are contr

PHY 351/651 LAB 9 Page 4 PHY351/651 DIGITAL ELECTRONICS - THE BASICS - LAB 9 represented as X; X AND Y is represented with X Y; X OR Y is represented with X Y; and X XOR Y is represented with X Y or equivalently as (X ) ( ). The physical implementation of such gates can be readily achieved using an array of transistors