ESP-PSRAM64 ESP-PSRAM64H Datasheet EN - Espressif
ESP-PSRAM64 &ESP-PSRAM64HDatasheetVersion 1.1Copyright 2020
About This DocumentThis document introduces the specifications of ESP-PSRAM64 and ESP-PSRAM64H.Release NotesDateVersionRelease notes2018.06V1.0First release.2020.10V1.1Updated Appendix–Device Marking Convention.Documentation Change NotificationEspressif provides email notifications to keep customers updated on changes to technicaldocumentation. Please subscribe at www.espressif.com/en/subscribe.CertificationPlease download the product certificate(s) from here.
Table of Contents1. Introduction .12. Pin Description .23. Power-up Initialization .34. Wrap Boundary Toggle Operation .45. Interface Description .65.1. Address Space .65.2. Page Size .65.3. Power-on Status .65.4. Truth Table .65.5. Command Termination .76. SPI Mode Operations.86.1. SPI Read Operations .86.2. SPI Write Operations .96.3. SPI Quad Mode Enable Operation .106.4. SPI Read ID Operation .117. QPI Mode Operations .127.1. QPI Read Operations .127.2. QPI Write Operations .127.3. QPI Quad Mode Exit Operation.138. Reset Operation .149. Input/Output Timing .1510.Electrical Specifications .1610.1. Absolute Maximum Ratings .1610.2. Operating Conditions .1610.3. Pin Capacitance .1610.4. DC Electrical Characteristics .1710.5. AC Electrical Characteristics .1711.Product Outline Dimension .19A. Appendix–Device Marking Convention .20
1. Introduction1.IntroductionThe ESP-PSRAM64 and ESP-PSRAM64H are 64 Mbit serial pseudo SRAM devices that areorganized as 8Mx8 bits. They are fabricated using very high-performance, high-reliability CMOStechnology. ESP-PSRAM64 operates at 1.8V and can offer high data bandwidth at 144 MHz clockrate , while ESP-PSRAM64H operates at 3.3V and can support up to 133 MHz clock rate. Notehowever that burst operations which cross page boundary have a lower max input clock frequencyof 84 MHz.Both of the PSRAM devices are accessed via a simple Serial Peripheral Interface(SPI) compatibleserial bus. Additionally, Quad Peripheral Interface (QPI) is supported if the application needs fasterdata rates. The devices also supports unlimited reads and writes to the memory array.Note that the information in this data sheet is applicable to both of the PSRAM devices; otherwise,the differences will be specified.Table 1-1. Ordering Information of ESP-PSRAM64 and ESP-PSRAM64HPart lock rateOperatingtemperatureProductcarrierGreen codeTape &ReelRoHS CompliantPackage andGreen/ReachPackage144 MHz64 MbitESP-PSRAM64HEspressif SystemsSOP8-150 mil–40 85 133 MHz1/21Submit Documentation FeedbackOperatingvoltageRead/Writeoperation modeSPI mode1 KB PagesStandard/Quad SPI1.8V3.3V2020.10
This device also suppoto the memory array.4M x 8-bit organization-1K byte per page!High ReliabilityGreen package availablePackage : 8-pin 150mil SOP2.The LY68S3200 op2.supplyPin Descriptionof 1.8V and can104MHz clock rate andPin DescriptionThe LY68S3200 offerPIN DESCRIPTIONPINofCONFIGURATIONFigure 2-1 shows the pin layoutESP-PSRAM64 and ESP-PSRAM64H.SYMBOLSPI re 2-1. Pin Layout of ESP-PSRAM64 and ESP-PSRAM64HCE#ChipSCLKClockVCCPoweVSSGrouTable 2-1. Signals TableABSOLUTE MAXIMUN RATINGS*PinSignal Type SPI Mode FunctionQPI Mode FunctionVCCPowerVssGroundCE#InputCLKInput*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damagClock signalSI/SIO[0]I/OSerial inputI/O[0]SO/SIO[1]I/OSerial BOLVoltage on VCC relative to VSSVT1Core supplygroundVoltageon any other pin relative to VSSVT2Operating TemperatureTAChip select signal, active low. When CE# 1, the chip is in standby state.Storage TemperatureTSTGCore supply, 1.8V for ESP-PSRAM64, 3.3V for ESP-PSRAM64H.RATING-0.2 to 2.4-0.3 to VCC -25 to 85-55 to 150rating only and functional operation of the device or any other conditions above those indicated in thespecification is not implied. Exposure to the absolute maximum rating conditions for extended period! "# %&'() * !reserves the rights to change the specifications and products without notice.I/O[3]2F, No. 17, lndustry E. Rd. II, Science-BasedIndustrial Park, Hsinchu 300, TaiwanTEL: 886-3-6668838FAX: 886-3-66688361Espressif Systems2/21Submit Documentation Feedback2020.10
3. Power-up Initialization3.Power-up InitializationSPI/QPI products include an on-chip voltage sensor used to start the self-initialization process.When Vcc reaches a stable level at or above the minimum Vcc, the device will need 150 μs anduser-issued reset operation (see Section 8) to complete its self-initialization process. From thebeginning of power ramp to the end of the 150-μs period, CLK should remain low, CE# shouldremain high (to track Vcc within 200 mV) and SI/SO/SIO[3:0] should remain low.After the 150-μs period, the device will then be ready for normal operation.VCCM INVCCtPU150 µsDevice InitializationDeviceResetDevice ready for normal operationCE#Figure 3-1. Power-up Initialization TimingEspressif Systems3/21Submit Documentation Feedback2020.10
4. Wrap Boundary Toggle Operation4. Wrap Boundary Toggle OperationThe Wrap Boundary Toggle Operation switches the device’s wrapped boundary between LinearBurst which crosses the 1K page boundary (CA[9:0]) and wrap 32 (CA[4:0]) bytes. Default setting isLinear Burst.Linear Burst allows the device to burst through page boundary. Page boundary crossing is invisibleto the memory controller and limited to lower max CLK frequency of 84 MHz. Table 4-1 shows anexample of the sequence of bytes.0123456711000000CLKCE#SISOHigh-ZWrap Boundary Toggle (hC0)Don't CareUndefinedFigure 4-1. SPI Wrap Boundary Toggle ‘hC001CLKCE#SIO[3:0]C0CMDWB Toggle(hC0)Don't CareFigure 4-2. QPI Wrap Boundary Toggle ‘hC0Espressif Systems4/21Submit Documentation Feedback2020.10
4. Wrap Boundary Toggle OperationTable 4-1. Burst Type/LengthBurst Type/LengthStarting AddressByte SequenceLinear Burst4[4,5,6,.1023,1024,1025,1026,.]Wrap 324[4,5,6,.31,0,1,2,.]Espressif Systems5/21Submit Documentation Feedback2020.10
5. Interface Description5.Interface Description5.1. Address SpaceSPI/QPI PSRAM device is byte-addressable. 64M device is addressed with A[22:0].5.2. Page SizeThe page size is 1K (CA[9:0]). Default burst setting is linear bursting that crosses page boundary ina continuous manner. Note however that burst operations which cross page boundary have alower max input clock frequency of 84 MHz. Optionally, the device can also be set to wrap 32(CA[4:0]) via the Wrap Boundary Toggle command and is not allowed to cross page boundary inthis configuration.5.3. Power-on StatusThe device powers up in SPI Mode. It is required to have CE# high before beginning anyoperations.5.4. Truth TableThe device recognizes the following commands specified by the various input methods.SPI Mode (QE 0)CommandCodeQPI Mode (QE X Freq.Read'h03S*note1S0S33N/AFast Read'h0BSS8S144/133N/AFast ReadQuad'hEBSQ6Q*note1 4/133*note2Quad Write'h38SQ0Q144/133Same as 'h02Enter QuadMode'h35S---144/133N/AExit QuadMode'hF5N/AQ---144/133Reset Enable 144/133Set BurstLength'hC0S---144/133Q---144/133Espressif Systems6/21Submit Documentation Feedback2020.10
5. Interface DescriptionSPI Mode (QE 0)CommandRead IDCode'h9FQPI Mode (QE WaitCycleDIOMAX Freq. Notes*:1. S Serial I/O; Q Quad I/O.2. 144/133 MHz max without crossing page boundary, and 84 MHz max when burst commands cross pageboundary.3. For ESP-PSRAM64, the maximum frequency is 144 MHz, while for ESP-PSRAM64H, it is 133 MHz.5.5. Command TerminationAll Reads & Writes must be completed by raising CE# high immediately afterwards in order toterminate the active command and set the device into standby. Not doing so will block internalrefresh operations and cause memory failure.Write TerminatedCLKtCHDCE#t HDSI/SIO[#]Data IntS PDon 't CareFigure 5-1. Write Command TerminationFor a memory controller to correctly latch the last piece of data prior to read termination, it isrecommended to provide a longer CE# hold time (tCHD tACLK tCLK) for a sufficient data window.Read TerminatedCLKCE#t CHDt A CLKSO/SIO[#]tHZHigh- ZData OutDon't CareUndefinedFigure 5-2. Read Command TerminationEspressif Systems7/21Submit Documentation Feedback2020.10
6. SPI Mode Operations6.SPI Mode OperationsThe device enters SPI mode on power-up by default but can also be switched into QPI mode.6.1. SPI Read OperationsFor all reads, data will be available tACLK after the falling edge of CLK. SPI reads can be done inthree ways: ‘h03: Serial CMD, Serial I/O, slow frequency, with linear or burst wrap of 32 byte configurability. ‘h0B: Serial CMD, Serial I/O, fast frequency, with burst wrap of 32/1K byte configurability. ‘hEB: Serial CMD, Quad I/O, fast frequency, with burst wrap of 32/1K byte d Command (h03)24bit Address6543210Data Out1Don't Care7654Data Out2UndefinedFigure 6-1. SPI Read ‘h03 (Max frequency: 33 MHz)Figure 6-2. SPI Fast Read ‘h0B (Max frequency: 104 MHz)(Max frequency: 144 MHz for ESP-PSRAM64, 133 MHz for ESP-PSRAM64H)Espressif Systems8/21Submit Documentation Feedback2020.10
6. SPI Mode OperationsFigure 6-3. SPI Fast Quad Read ‘hEB(Max frequency: 144 MHz for ESP-PSRAM64, 133 MHz for ESP-PSRAM64H)6.2. SPI Write te Command( h02 )24bit AddressData In1Don't CareData In2UndefinedFigure 6-4. SPI Write ‘h02Espressif Systems9/21Submit Documentation Feedback2020.10
6. SPI Mode OperationsFigure 6-5. SPI Quad Write ‘h386.3. SPI Quad Mode Enable OperationThis command switches the device into quad I/O mode.0123456700110101CLKCE#SISOHigh-ZEnter Quad Mode CMD(Don't Careh35 )UndefinedFigure 6-6. Quad Mode Enable ‘h35 (available only in SPI mode)Espressif Systems10/21Submit Documentation Feedback2020.10
6. SPI Mode Operations6.4. SPI Read ID OperationThis command is similar to Fast Read, but without the wait cycles and the device outputs EIDvalue instead of data.Figure 6-7. SPI Read ID ‘h9F (Available Only in SPI Mode)Table 6-1. Known Good Die (KGD)KDG[7:0]Known Good Die‘b0101 0101Fail‘b0101 1101Pass Note:Default is FAIL die, and only mark PASS after all tests passed.Espressif Systems11/21Submit Documentation Feedback2020.10
7. QPI Mode Operations7.7.1.QPI Mode OperationsQPI Read OperationsFor all reads, data will be available tACLK after the falling edge of ]EB 23:20 19:16 15:12 11:8 7:43:0High-Z24bit Address7:43:07:43:0Wait CyclesFast ReadCMD( hEB)Data Out 1 Data Out 2Don't CareFigure 7-1. QPI Fast Read ‘hEB(Max frequency: 144 MHz for ESP-PSRAM64, 133 MHz for ESP-PSRAM64H)7.2. QPI Write OperationsQPI write command can be input as ‘h02 or [3:0]23:20 19:16 15:12 11:824bit AddressQPI WriteCMD( h02 or 38)Data In1Data In2Don't CareFigure 7-2. QPI Write ‘h02 or ‘h38Espressif Systems12/21Submit Documentation Feedback2020.10
7. QPI Mode Operations7.3. QPI Quad Mode Exit OperationThis command will switch the device back into serial I/O mode.01F5CLKCE#SIO[3:0]Quad Mode ExitCMD( hF5)Don't CareFigure 15 : Quad Mode Exit hF5(only available in QPI mode )Figure 7-3. Quad Mode Exit ‘hF5 (Only Available in QPI Mode)Espressif Systems13/21Submit Documentation Feedback2020.10
8. Reset Operation8.Reset OperationThe reset operation is used as a system (software) reset that puts the device in SPI standby mode,which is also the default mode after power-up. This operation consists of two commands: ResetEnable (RSTEN) and Reset SISOHigh-ZReset Enable CMD(h 66)Reset CMD(Don't Careh99)UndefinedFigure 16 : SPI ResetFigure 8-1. SPI Reset01236699CLKCE#SIO[3:0]RSTENCMD( h66)RSTCMD( h99)Don 't CareFigure 17 : QPI ResetFigure 8-2. QPI ResetReset command has to immediately follow the Reset-Enable command in order for the resetoperation to take effect. Any command other than the Reset command after the Reset-Enablecommand will cause the device to exit Reset-Enable state and abandon reset operation.Espressif Systems14/21Submit Documentation Feedback2020.10
9. Input/Output Timing9.Input/Output B inLSB intSPSOHigh-ZDon't CareUndefinedFigure 18 : Input TimingFigure 10-1. Input TimingtCLKtCHtCLCLKCE#tHZtACLKSIADDR LSB intKOHSOHigh-ZMSB outLSB outDon't CareUndefinedFigure 19 : Output TimingFigure 10-2. Output TimingEspressif Systems15/21Submit Documentation Feedback2020.10
10. Electrical Specifications10.Electrical Specifications10.1. Absolute Maximum RatingsTable 10-1. Absolute Maximum RatingsSymbolParameterRatingUnitVTVoltage to any pad except Vcc relative to Vss 0.3 Vcc 0.3VVccVoltage on Vcc relative to VssESP-PSRAM64: –0.2 2.45ESP-PSRAM64H: 0.2 4.2VTSTGStorage Temperature* 55 150 C Note:*Storage temperature refers to the case surface temperature on the center/top side of the PSRAM. Notice:Exposing the device to stress greater than the listed absolute maximum ratings could cause permanent damage. Thedevice is not meant to be operated under conditions outside the limits specified in this document. Exposure toAbsolute Maximum Rating conditions for extended periods may affect device reliability.10.2. Operating ConditionsTable 10-2. Operating CharacteristicsParameterMinMaxUnitOperating Temperature–4085 C10.3. Pin CapacitanceTable 10-3. Package Pin CapacitanceSymbolParameterMinMaxUnitNotesCINInput Pin Capacitance-6pFVIN 0VCOUTOutput Pin Capacitance-8pFVOUT 0VEspressif Systems16/21Submit Documentation Feedback2020.10
10. Electrical Specifications10.4. DC Electrical CharacteristicsTable 10-4. DC CharacteristicsSymbolParameterMinMaxUnitVccSupply voltageESP-PSRAM64: 1.62ESP-PSRAM64H: 2.7ESP-PSRAM64: 1.98ESP-PSRAM64H: 3.6VVIHInput high voltageVcc – 0.4Vcc 0.2VVILInput low voltage–0.20.4VVOHOutput high voltage (IOH –0.2 mA)0.8 Vcc-VVOLOutput low voltage (IOL 0.2 mA)-0.2 VccVILIInput leakage current-1μAILOOutput leakage current-1μAICCRead/Write-ESP-PSRAM64: 25ESP-PSRAM64H: 40mAISBStandby current*-200μA Note:*Standby current is measured when CLK is in DC low state.10.5. AC Electrical CharacteristicsTable 10-5. Read/Write TimingSymbolParameterMinCLK period—SPI Read (’h03)30.3tCLKMaxUnit-nsNotes33 MHzCLK period—all other operations7tCH/tCLClock high/low width0.450.55tCLK (min)-tKHKLClock rise or fall time-1.5ns-tCPHCE# HIGH between subsequent burst operations50-ns-tCEMCE# low pulse width-8μs-tCSPCE# setup time to CLK rising edge2.5--tCHDCE# hold time from CLK rising edge20--tSPSetup time to active CLK edge2--tHDHold time from active CLK edge2-Espressif Systems17/21Submit Documentation Feedback144/133 MHz*ns-2020.10
10. Electrical p disable to DQ output hight-Z-6-tACLKCLK to output delay26-tKOHData hold time from clock falling edge1.5-- Note*:1. Only Linear Burst allows page boundary crossing. Frequency limits are therefore 144/133 MHz MAX. without crossing page boundary, and 84 MHz MAX. when burst commands cross page boundary.2. For ESP-PSRAM64, the maximum frequency is 144 MHz, while for ESP-PSRAM64H, it is 133 MHz.3. For operating frequencies 84 MHz, refer to JEDEC JESD84-B50 for data sampling training.Espressif Systems18/21Submit Documentation Feedback2020.10
11. Product Outline Dimension11.Espressif SystemsProduct Outline Dimension19/21Submit Documentation Feedback2020.10
Appendix A – Device Marking ConventionA.Appendix–Device MarkingConventionPin1 LocationCompany LogoESPPSRAM64WWYYYYXXXXXXXXXXCompany NameDevice NameAssembly Date CodeWW – number of weekYYYY – calendar yearTracking InformationFigure A-1. Device Marking of ESP-PSRAM64Pin1 LocationCompany LogoESPPSRAM64HWWYYYYXXXXXXXXXXCompany NameDevice NameAssembly Date CodeWW – number of weekYYYY – calendar yearTracking InformationFigure A-2. Device Marking of ESP-PSRAM64H Note:The content and the number of digits of the Tracking Information are subject to change.Espressif Systems20/21Submit Documentation Feedback2020.10
Disclaimer and Copyright NoticeInformation in this document, including URL references, is subject to change withoutnotice.THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER,INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESSFOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUTOF ANY PROPOSAL, SPECIFICATION OR SAMPLE.All liability, including liability for infringement of any proprietary rights, relating to the use ofinformation in this document, is disclaimed. No licenses express or implied, by estoppel orotherwise, to any intellectual property rights are granted herein.The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo isa registered trademark of Bluetooth SIG.Espressif IoT TeamAll trade names, trademarks and registered trademarks mentioned in this document areproperty of their respective owners, and are hereby acknowledged.www.espressif.comCopyright 2020 Espressif Inc. All rights reserved.
2. Pin Description 2. Pin Description Figure 2-1 shows the pin layout of ESP-PSRAM64 and ESP-PSRAM64H. Figure 2-1. Pin Layout of ESP-PSRAM64 and ESP-PSRAM64H LY68S3200 Rev. 1.3 32M Bits Serial Pseudo-SRAM with SPI and QPI ! "# %&'() * !reserves the rights to change the specifications and products without notice.
ESP-PSRAM64 and ESP-PSRAM64H are 64 Mbit serial pseudo SRAM devices that are organized in 8Mx8 bits. They are fabricated using the high-performance and high-reliability CMOS technology. ESP-PSRAM64 operates at 1.8V and can offer high data bandwidth at 144 MHz clock rate, while ESP-PSRAM64H o
TTL and CMOS logic 74 Series 74ls00 datasheet, 74ls02 datasheet, 74ls04 datasheet, 74ls08 datasheet, 74ls11 datasheet, 7414 datasheet, 74ls14 datasheet, 74ls20 datasheet, 74ls30 datasheet, 74ls32
Datasheet Includes: ESP-WROOM-02D ESP-WROOM-02U. About This Guide This document provides introduction to the specifications of ESP-WROOM-02D and ESP- . Core ESP8266 ESP8266 Antenna Onboard antenna IPEX antenna Dimensions (unit: mm) (18.00 0.10) x (20.00 0.10) x (3.20 0.10)
Kodak AiO Ink Technology Deep Dive ESP 1.2 / 3.2ESP 1.2 / 3.2 Hero 9.1Hero 9.1 Hero 7.1Hero 7.1 Office Hero 6.1Office Hero 6.1 Hero 5.1Hero 5.1 Hero 3.1Hero 3.1 2011‐ 2013 ESP C110, C310, C315 ESP Office 2150/2170 ESP Office 6150 ESP 7250 ESP 9250 2010‐ ESP 3250 ESP 5250 ESP3 ESP5 ESP7 ESP9 2011 2008‐ 2009 Easyshare 5100 Easyshare 5300 .
ESP 88 and ESP 00 can support a total of 4 cards per ESP for a total of 16 mic/ line inputs and 16 line outputs. The ESP-88 comes pre-loaded with two 4x4 mic/line cards, allowing two additional 4x4 cards to be added. The ESP-00 does not include these cards, so 8 audio input or output cards can be added. PC 0
1 subl 12 , %esp 1 function : 2 movl 3 , 8(%esp ) 2 pushl %ebp 3 movl 2 , 4(%esp ) 3 movl %esp , %ebp 4 movl 1 , (%esp ) 4 subl 16 , %esp 5 c a l l function. Pushes the base pointer (EBP) in the stack, now it’s a saved frame pointer (SFP). Moves the stack pointer (ESP) in EBP, subst
Description of major functional modules integrated on ESP-WROOM-02, including CPU, flash, memory and interfaces. Chapter 4 Electrical Characteristic Electrical data of ESP-WROOM-02. Chapter 5 Schematics ESP-WROOM-02 schematics and peripheral schematics. Appendix A Learning Resources ESP
Previous editions of this Standard were issued in 2003, 2012, and 2016. The 2019 edition of this Standard was approved by the American National Standards Institute as an American National Standard on December 4, 2019. v This is a preview of "ASME PVHO-2-2019". Click here to purchase the full version from the ANSI store.
