The New Era Of Scaling In An SoCWorld

2009 ISSCCThe New Era of Scalingin an SoC WorldMark BohrIntel Senior FellowLogic Technology Development1

The End of Scaling is Near?“Optical lithography will reach its limits in the range of 0.75-0.50 microns”“Minimum geometries will saturate in the range of 0.3 to 0.5 microns”“X-ray lithography will be needed below 1 micron”“Minimum gate oxide thickness is limited to 2 nm”“Copper interconnects will never work”“Scaling will end in 10 years”Perceived barriers are meant to besurmounted, circumvented or tunneled through2

Outline Transistor Scaling Microprocessor Evolution Vision of the Future3

Scaling Trends10CPU Transistor Count1092x every 2 020Transistor dimensions scale to improve performance,reduce power and reduce cost per transistor4

Scaling Trends10CPU Transistor Count1092x every 2 yearsMicrons11070.1Feature Size65nm45nm32nm1050.7x every 2 years0.01197010319801990200020102020Transistor dimensions scale to improve performance,reduce power and reduce cost per transistor5

MOSFET ScalingDevice or Circuit ParameterScaling FactorDevice dimension tox, L, W1/κDoping concentration NaκVoltage V1/κCurrent I1/κCapacitance εA/t1/κDelay time/circuit VC/I1/κPower dissipation/circuit VI1/κ2Power density VI/A1R. Dennard, IEEE JSSC, 1974Classical MOSFET scaling was first described in 19746

30 Years of MOSFET ScalingDennard 1974Intel 20051 µmGate Length:1.0 µm35 nmGate Oxide Thickness:35 nm1.2 nmOperating Voltage:4.0 V1.2 VClassical scaling ended in the early 2000sdue to gate oxide leakage limits7

90 nm Strained Silicon TransistorsNMOSPMOSHighStressFilmSiGeSiN cap layerTensile channel strainSiGeSiGe source-drainCompressive channel strainStrained silicon provided increased drive currents,making up for lack of gate oxide scaling8

High-k Metal Gate Transistors65 nm Transistor45 nm HK MGSiO2 dielectricPolysilicon gate electrodeHafnium-based dielectricMetal gate electrodeHigh-k metal gate transistorsbreak through gate oxide scaling barrier9

Transistor Performance IncreaseNMOSPMOS1000100065nm 45nm100 12%5x1011.0 V65nmIOFF (nA/um)IOFF (nA/um)1.0 V1001045nm 50%100x10.6 0.8 1.0 1.2 1.4 1.6 1.8ION (mA/um)0.4 0.6 0.8 1.0 1.2 1.4 1.6ION (mA/um)45 nm HK MG provides average 30% drive currentincrease or 5x IOFF leakage reductionRef. K. Mistry, IEDM ’0710

Gate Leakage ReductionN o rm a liz e d G a te L e a k a g e100SiON/Poly 65nm1025x1SiON/Poly 65nm0.11000x0.010.001HiK MG 45nmHiK MG 45nm0.00010.00001-1.2NMOSPMOS-1-0.8 -0.6 -0.4 -0.200.2 0.4 0.6 0.811.2VGS (V)HK MG significantly reduces gate leakage11

Bitcell Leakage Reduction12Normalized Cell Leakage1.0V 25C1086IGATE10x4IOFF2IJUNCT065nm45nmSRAM bitcell leakage reduced 10x12

VT Variability ReductionC2Normalizedto 180nm1.110.90.80.70.60.50.4Minimaloxide scale HiK MGLess VTvariationTox scaling180nm 130nm 90nm 65nm 45nmσVTran 4 4q 3ε siφB 2 T ox ε ox 4 N Leff ZeffC 1 c22 2 Leff Zeff ( HK MG provides oxide scaling needed for variability reductionRef. K. Kuhn, IEDM ’0713

Interconnect Trends101086M2 Pitch1(um)40.7x pergeneration0.1500# MetalLayers2035025018013090654532Technology Generation (nm)Added metal layers material improvementsenable interconnect scaling14

Interconnect Trends101086M2 Pitch1(um)40.7x pergeneration0.1500# MetalLayers2035025018013090654532Technology Generation (nm)Added metal layers material improvementsenable interconnect scaling15

Interconnect Trends101086M2 Pitch1(um)4SiO2SiOFLow-kAl0.1500Lower-k# MetalLayers2Cu035025018013090654532Technology Generation (nm)Added metal layers material improvementsenable interconnect scaling16

45 nm InterconnectsPitch (nm)Loose pitch thick metalon upper layers High speed global -k Low resistance power gridTight pitch on lower layers Maximum density forlocal interconnectsHierarchical interconnect pitches17

45 nm InterconnectsPolymerM97 µm CuM1-8Thick M9 for very low resistance on-die power routing18

45 nm Microprocessor ProductsSingle Core6 CoreDual CoreQuad Core8 Core45 nm process serves microprocessor applicationsfrom low power to high performance19

32 nm 0202020

32 nm Logic Technology 2nd generation high-k metal gate transistors- High-k EOT scaled from 1.0 nm to 0.9 nm- Replacement metal gate process flow- 4th generation strained silicon 9 copper low-k interconnect layers- Hierarchical interconnect pitches- Thick M9 for power routing Immersion lithography on critical layers- 70% transistor and interconnect pitch scaling- 50% SRAM cell area scaling Pb-free and halogen-free packagesHigher performance, lower power, lower cost per transistor21

Contacted Gate Pitch Trend1000PitchGate Pitch(nm)0.7x every2 years100199532 nm Generation112.5 nm Pitch200020052010Transistor gate pitch continues to scale 0.7x every 2 years22

Transistor Performance2.02.01.0 V, 100 nA IOFF32nm45nm1.5DriveCurrent Gate Pitch (nm)0.0100Drive currents continue to increase while gate pitch scales23

32 nm Interconnects8 um CuM9Pitch 112.5112.5Hierarchical interconnect pitches24

SRAM Cell Size Scaling10Cell Area2(um )10.5x every2 years0.11995200032 nm Generation0.171 um2 Cell20052010Transistor density continues to double every 2 years25

SRAM Cell Scaling65 nm0.570 µm245 nm0.346 µm232 nm0.171 µm2Good pattern resolution while scaling feature sizeand continuing with 193 nm exposure wavelength26

32 nm SRAM Test Chip 291 Mbit 0.171 um2 cell size 1.9 billion transistors 3.8 GHz operation Functional silicon in Aug ‘0732 nm SRAM test vehicle included all transistor andinterconnect features used on 32 nm microprocessorsRef. Y. Wang, paper 27.1, ISSCC ’0927

30 Years of ScalingContact1978Ten 32nm SRAM Cells20081 µm28

The Old Era of Device ScalingDevice or Circuit ParameterScaling FactorDevice dimension tox, L, W1/κDoping concentration NaκVoltage V1/κCurrent I1/κCapacitance εA/t1/κDelay time/circuit VC/I1/κPower dissipation/circuit VI1/κ2Power density VI/A1It has served us well for 30 years29

The New Era of Device ScalingSiGeCopper Low-kSiGeStrained SiliconHigh-k Metal GateModern CMOS scaling is as much aboutmaterial and structure innovation as dimensional scaling30

Outline Transistor Scaling Microprocessor Evolution Vision of the Future31

Microprocessor EvolutionMore transistorsHigher frequencyMore data bits per cycleInstruction parallelismOut-of-order issueMulti-threadingMany of these innovations have been for improved performance,now the challenge is to innovate for power efficiency32

45 nm Nehalem CPUModern microprocessors are a complex system on a chipwith multiple functional units and multiple interfaces33

45 nm Nehalem CPU23 master DLL circuits11 PLL circuits5 digital thermal sensorsMultiple clocking domains, local control34

SRAM Dynamic Sleep TransistorsVDDNormal SRAMsub-block leakageSleep transistorsshut off leakage ininactive sub-blocksSRAM CacheSub-BlockSleepControlSleepTransistorIREM images showing banks being accessedVSS5-10x leakage reduction during “retention/standby”Ref. K. Zhang, VLSI Circuits ‘0435

Integrated Power GatesVCCThick On-Die (M9)Interconnect LayerPower GatesNehalemCore0Core1Core2Core3Memory System, Cache, I/OVTT Shuts off both switching power and leakage power Enables idle cores to go to 0 power, independentof state of other cores on dieRef. R. Kumar, paper 3.2, ISSCC ’0936

Power Gates Enabled withDesign Process Co-optimizationM9M1-8Thick metal 9 layer for lowresistance on-die power routingUltra-low leakage transistor forhigh off-resistance power gates37

Nehalem Turbo Mode All cores operatingCore 3Core 2Core 1Core 0Core 3Core 2Core 1Lightly threaded workloads - Turbo ModeCore 0Core 3Core 2Core 1Core 0FrequencyMany threaded workloads Power gates shut off some cores Zero power for inactive cores Higher frequency for active coresDynamically delivering optimal performance and energy efficiencyRef. R. Kumar, paper 3.2, ISSCC ’0938

Nehalem Power Control UnitVccBCLKCore 0PLLVccFreq.Sensors Integrated proprietarymicrocontrollerPLLCore 1 Shifts control from hardware toembedded firmwareVccFreq.SensorsPLLCore 2PCUVccFreq.SensorsPLLCore 3UncoreLLCVccFreq.SensorsPLL Real time sensors for voltage,temperature, current/power Flexibility enables sophisticatedalgorithms, tuned for currentoperating conditionsRef. R. Kumar, paper 3.2, ISSCC ’0939

Adaptive Frequency SystemHigher freq.Lower freq.DigitalVoltageSupply Adaptive PLL frequency– Higher frequency during voltage peaks– Lower frequency during voltage droops Up to 5% frequency improvement at same voltage Lower power at same frequencyRef. N. Kurd, VLSI Circuits ’0840

PC Platform heDataSRAMIntel386TMProcessorIntel387 MDRAMDRAMDRAMDRAMDRAMDRAMDRAMModern microprocessors integrate many of theseparate system components from past platforms41

Microprocessor EvolutionTransistor Count:Frequency:# Cores:Cache Size:I/O Peak Bandwidth:Adaptive Circuits:Intel386TMNehalem280 thousand731 million16 MHz 3.6 GHz14None8 MB64 MB/sec50 GB/secNoneSleep ModeTurbo ModePower GatingAdaptive Frequency Clocking42

45 nm SoC V10.1LowPower1.1VIOFF (nA/um)IOFF 0.010.6 0.8 1.0 1.2 1.4 1.6 1.80.4 0.6 0.8 1.0 1.2 1.4 1.6ION (mA/um)ION (mA/um)Wider range of transistor types provided for SoC:High performance and low powerRef. C. Jan, IEDM ‘0843

45 nm SoC I/O TransistorsNMOS @ 1.8VPMOS @ 1.8V10165nmSiO210.1I OFF (nA/um)I OFF (nA/um)65nm 45nmSiO2 HKMG 17%0.10.010.010.0010.0010.00010.40.50.60.7I ON (mA/um)0.845nmHKMG 57%0.20.30.40.50.6I ON (mA/um)Wider range of transistor types provided for SoC:High speed, high voltage I/ORef. C. Jan, IEDM ‘0844

Devices for SoC Analog CircuitsPassive Elements Precision resistor High Q varactor High Q inductor70Active Elements60 RF CMOS A to D, D to A converters50Gain (dB)RF Mixed Signal Circuits40H2130-20dB/dec.Mason’s U RF transceiver20 LCPLL10 High speed I/ONMOS28nmx0.9umx100VDS 1.1VVG 0.6VfT 395 GHzfMAX 410 GHz00.1110100Frequency (GHz)1000Ref. C. Jan, IEDM ‘0845

The Old Era of Microprocessor ScalingLarger CoresHigher FrequencyHigher PowerIt has served us well for 30 years46

The New Era of Microprocessor ScalingMany-CoreMulti-CoreMulti-FunctionSystem on a ChipAvoiding the power wall requires a systemic approach fromprocess technology through circuit design to micro-architectureto deliver products with power efficient performance47

Outline Transistor Scaling Microprocessor Evolution Vision of the Future48

Future Scaling Challenges Patterning ever-smaller features sizes Transistor and interconnect technologies thatprovide higher performance at lower power Continued voltage scaling for low power Integrating a wider range of device types forsystem-on-chip or system-in-package products49

Lithography11000Wavelength248nm193nmOPCmicron 0.1100 nmPhase shiftImmersion32nm22nmFeature Size15nm0.011980199020002010EUV13.5nm102020193 nm enhancements got us to the 32 nm generation50

Layout Restrictions65 nm Layout Style32 nm Layout Style Bi-directional features Uni-directional features Varied gate dimensions Uniform gate dimension Varied pitches Gridded layout51

Lithography Options for Beyond 32 nmPitch Doubling2-D FeaturesPixilated MaskPrinted ImageDouble Patterning Pitch doubling Improved 2-D featuresComputational Lithography Pixilated mask Existing 193 nm litho tools52

Extreme Ultraviolet LithographyCymer beta sourceIntel EUV MaskASML ADT printed wafer20071H’1H’08C2H’2H’08TargetPhilips beta source2H 08Photoresist DevelopmentNikon EUV1 printed waferContinued progress towards EUV implementation53

Transistor Options340 110 Increased p-channel mobility? Impact on n-channel mobility 100 2902Substrate EngineeringHole Mobility (cm /Vs)Hole 110 240(100)190 100 111 2x14090 110 (110)(100) Mobility(110) Mobility40-3000-2000-10000 110 Stress (MPa)FinFETMulti-Gate FETs Improved electrostatics Steeper sub-threshold slope? Higher parasitic resistanceGAA? Higher parasitic capacitance54