Dynamic Noise Analysis: Definitions, Models And Tool

3/8/2013Double-Pole Approximation (2P)Victim 1P approximation:H (s) a2 s 2 a1s a0b3s 3 b2 s 2 b1s 1H1 ( s ) Aggressor time constant:Victim waveform: Vout (t ) t X t ra1sb1s 1t A C AL RA (C AM C X ,eff C AR ,eff )( RA RAL ) tt 1 A e t / t A V e t / tV t trtV t A tV t A tA t (e t / t A e (t tr ) / t A ) V (e t / tV e (t tr ) / tV ) t trtV t A tV t A tXtrt X C X ( RV RVL )tV CVL RV (CVM C X )( RV RVL ) CVR ( RV RVL RVR )Comparison of models 1P model predicts wrong noise peak time 1P model waveform is not smooth 2P model matches SPICE very wellt peak tr tV t A 1 e tr / t A lntV t A 1 e tr / tV Maximum noise voltage (based on 5000 random circuits):MethodAverage errorCases 5% errorCases 10% error3 sigma errorDominant pole8.3%37.3%66.8%26%Double pole2.3%92.6%99.9%8%27

3/8/2013Experiments on Industrial Circuits 30 noise-prone industrial circuits in 0.15 micron techAverage number of aggressors: 5Average number of RC elements: 128Average victim wire length: 2.1 mmResults of the Proposed Method (2-Pole, 6-nodes template) Average peak noise error: Reduced from 11.7%(aggressors nets and branches are reduced by previousnaïve methods) to 2.7% Maximum peak noise error: Reduced from 21.3%(previous naïve methods) to 7.8%Conclusions Method for quiet aggressor nets reduction Method for tree reduction Double-pole model for template circuit Efficient crosstalk noise estimation framework28

3/8/2013Noise ClassificationNoiseLocal NoiseCircuit NoiseGlobal NoiseInterconnect NoiseSubstrate NoisePower/Gnd NoiseLeakage NoiseCapacitive CrosstalkMinor. Carrier Q Injec.Charge SharingInductive CrosstalkBulk Voltage EffectMiller CouplingResistive Voltage DropBack-gate CouplingInductive Voltage BounceOutline Motivation of the research Equivalent circuit for SNN modeling ASDM for MOS devices SSN analysis and formulation Effect of parasitic capacitance29

3/8/2013Motivations SSN is caused by parasitic inductance atpower/ground network SSN is a serious problem in VDSM VLSI chips1.2.3.4.Generate glitches on the power/ground wiresIncrease delayCause output signal distortionReduce overall margin of a system Simple formulation is desired for SSN estimation Previous formulations are not adequateEquivalent Circuit for SSN Modeling* R IR drop* L SSNPower (VDD) Pin andBonding ParasiticsNFETsGround (VSS) Pin andBonding ParasiticsGround (VSS) Pin and1. Assume there are N identical drivers Bonding Parasitics2. Drivers switch simultaneously3. Drivers switch at the same direction4. Large capacitance load at the drivers5. Since CL is large and NFETs are in Saturation, theycan be replaced by Current Sources30

3/8/2013Typical WaveformsL 1.0nH1 driverL 2.0nH5 driversL 5.0nH10 driversMOSFET ModelingLong channel MOSFET model (Shockley’s Model):Short channel MOSFET model(Sakurai & Newton’s -Power Law Model)31

3/8/2013SSN Analysis – Inductance Only -Power Law Model:V NLdI DdtI D K (VIN V VTH ) Ignore Capacitance* No analytical solution!* How do we proceed?Previous Works Sethinathan and Prince, JSSC91 (long channel model, linear) Vemuru, TPCK96 ( -power model, Taylor) Jou et al., CICC98 ( -power model, Taylor2) Song, Ismail, et al., ISCAS99 ( -power model, linear Taylor)V NLdI DdtI D K (VIN V VTH ) * Why approximation?* Why -power law model?32

3/8/2013Application-Specific Device Modeling -power law model:Linear model:I D K (VG VS VTH ) I D K (VG VS V0 )Extracted Model ParametersProcess*VDD (V)TypeK (mA/V)V0 (V) 81.080.25um0.35um2.53.3* TSMC processes, available through MOSIS33

3/8/2013Simple SSN FormulationSolution to 1st order ODE:dIV L DdtI D NK (VG VS V0 )dVVs rdt NLK V (t ) NLsr K (1 eVm NLsr K (1 e t t 0 NLKV V DD 0 NLsr K))I D (t ) K (sr t V0 NLsr K (1 e t t 0 NLK))rising slew rate sr VDD / t rComparison with Previous WorksPrior worksModeling ErrorThis workModeling ErrorEqn. Deriv. Error34

3/8/2013A Figure of Merit – HVm NLsr K (1 e VDD V0 NLsr K)H NLsrVm HK (1 e VDD V0 HK) H is the only circuit-related parameter H depends equally on three variables: N, L, and srSSN Modeling with CapacitanceV LdI LdtI L NK (VG VS V0 ) CCd 2Vdt 2 NK dVdtdV 1 V NKsrdt L N 2 K 2 2 4C / L As N underdamp critical damp overdampFor a FixedTechnologyas No. OfDriversIncreasesN High speedLow speed35

3/8/2013Transient WaveformsCase 1: over dampedCase 2: critically dampedCase 3a: under damped (F)Case 3b: under damped (S)Comparison of Peak Noise VoltageSingle ground pad:Two ground pads:L 5nH, C 1pFL 2.5nH, C 2pFI N crit2 C critK LIIN crit 2 CcritK LI 2 N crit36

3/8/2013Contributions Simple & accurate modeling of SSN for chipoutput drivers Parasitic capacitance effect discussed andmodeled Idea of application-specific device modeling isgenericTHE END37

3/8/2013List of Tools In Research Papers– ClariNet– Harmony / Global HarmonySubstrateStorm Previously called Layin (created by SnakeTech) Modeling, noise analysis for RF, analog, mixedsignal IC designs Characterization of CMOS, BiCMOS, and bipolarprocesses using lightly doped, epitaxial orsilicon-on-insulator (SOI) bulks In addition to its path through an IC well, it canalso find the frequencies at which the noiseenters the substrate cells38

3/8/2013SubstrateStorm FEM-like analysis 3D mesh to model IC substrate– Vertical gridlines: doping profiles– Surface grid: IC layout Inputs– IC layout information– Technology characterization (CMOS,BiCMOS etc.) Modeling accuracy: upto 20% of actual SiGateScope Created by Moscape (now part of Magma) Goals– Analyze design for noise problems– Locate noise violations– Generates data to automate repair Employs assertion-based technology toidentify and correct noise problemscaused by cross-coupling effects in ASICdesigns at 0.18 µm and below39

3/8/2013GateScope Noise affecting functionality timing Whole-chip noise detection run followed by highlydetailed analysis Works initially at gate level to isolate ‘noisy’ circuits Info from static timing analysis to determine whichsignals are likely to switch at the same time and whethercrosstalk interference will cause stable levels to switch Then detects aggressor-victim combos and descends totransistor level Deterministic transient analysis to methodically eliminatefalse errors on multimillion gate designs.Nova From IBM Full-chip power supply noise analysis tool can simultaneously analyze resistive IR dropand inductive delta-I noise on a full-chip scale Designers can–––––easily identify the hot spots,optimize decoupling capacitor placement,minimize power supply noise,preserve signal integrity,improve circuit performance40

3/8/2013Eldo / Eldo RF From Mentor Graphics Both are fast transistor-level structuresimulators driven by a Spice netlist– Include noise analysis tools Eldo RF supports phase noise analysis Description available is for the circuitsimulation tool. Nothing specific aboutnoise analysis.CeltIC From Cadence Identifies nets with low noise immunity to avertpotential noise-related problems and lethalsilicon failures before tapeout. Accurately calculates the impact of noise onboth the delay and functionality of cell-baseddesigns. Performs SoC noise analysis and generatesrepairs back into place-and-route.41

3/8/2013CeltIC Key features and benefits– Prevents silicon respins due to noise relatedfunctional failures– Accurately accounts for crosstalk effects on timing– Improves yield by fixing nets with low noise immunity– Reduces design iterations via early detection of signalintegrity problems– Isolates and repairs crosstalk-induced functional anddelay failures– Calculates the impact of noise on delay and slew forfeedback to STACeltIC Key features and benefits (contd.)– Reduces SI closure iterations by filtering false failures by over 10to 100X versus other crosstalk analyzers– Predicts functional, timing, and yield problems resulting frombootstrap and overshoot/undershoot noise– Performs accurate glitch propagation to verify noise immunitywith no additional overhead characterization– Performs internal timing window convergence to reducepessimism– Automates noise library creation for cells, memories, I/Os, andcustom macros– Handles multimillion SoC designs flat or hierarchically usingECHO models42

3/8/2013Swan Substrate-noise Waveform Analysis fromInteruniversity Microelectronics Centre Substrate noise analysis on SOCs wherelarge digital circuits generate groundbounce Uses macromodels to analyze noise– Adapts techniques for low-ohmic devices tostudy of high-ohmic substratesSwan Swan consists of two parts– Standard cell-library characterization Record substrate-noise generation and powersupply current related to switching activity for allstandard cells. Once-only for given technology and cell library– Substrate-noise waveform computation Switching events from gate-level VHDL sim Combine switching-noise generation model &switch data to get waveform and ground bounce.43

3/8/2013Substrate Noise Analyst Substrate noise analyzer for RF, analog, and mixed-signal ICs from Cadence It provides a silicon-accurate model for substratecoupling effects to enable chip integration Captures full-chip noise effects using static anddynamic techniques to model switching noise Accelerates noise simulation on sensitiveanalog/RF circuits by utilizing RC reduction Reduces noise coupling through isolationanalysis using graphical visualization of surfacenoise distributionSubstrate Noise Analyst Other features– Accurate 3D substrate modeling Advanced semiconductor physics based Minimum of 80% accuracy across various techs– Advanced digital noise modeling New static noise modeling techniques– Simulation netlist Generates substrate RC network connected tobulk terminals of selected devices44

3/8/2013Pacific Static Noise Analyzer Analyzes the combined impact of majornoise sources including crosstalk, IR drop,and propagated noise on the design Prevents functional chip failures due tonoise in custom digital circuits Improves chip yield by identifying noisesensitivity circuitry Calculates crosstalk impact on timing toassist static timing signoffPacific Static Noise Analyzer Other features– Advanced circuit and interconnect noiseanalysis non-linear transistor-level transient simulationengine and advanced RLCK network solver for efficientlyanalyzing large coupled networks Interconnect noise due to crosstalk combined withcircuit noise due to charge-sharing, leakage, IRdrop, overshoot, undershoot, and noisepropagating from previous logic stages45

3/8/2013Pacific Static Noise Analyst Other features (contd.)– Noise stability Uses sensitivity-based noise stability metric todetermine noise immunity of every node metric helps localize failures near their source andguarantees adequate noise immunity circuit cross-section with the appropriate waveformstimulus required to replicate the problemPacific Static Noise Analyst Other features (contd.)– Full-chip hierarchical analysis Uses high-level noise abstractions Supports UDN model (incomplete or non-digitalblocks) and ECHO model (transistor level)– SOI noise analysis Account for floating-body and parasitic effects46

3/8/2013Definition of VOH and VOL Given by -1 slopepoints Stable logic statesof an infinite chainof inverters or abistable inverterpairStatic Noise Margin Criteria Odd gateVout f( Vin )xfgate 1yggate 2 Even gateVout g( Vin )47

3/8/2013Noise Margin Criteria Coincidence of roots of flip-flopequationx g ( f ( x)) 0 Small-signal closed loop gain f x g y 1Noise Margin Criteria Jacobian of Kirchhoff equation is zeroF1 x g ( y ) 0F2 y f ( x ) 0 F1 xJ F2 x F1 y 0 F2 y48

3/8/2013Static Noise Margin Criteria Maximum squarebetween normal andmirrored VTC NMH·NML is Maximum(maximum productcriteria)Checking DNM Onlyis not Enough No noise violation if only Check VIH for VA Check VIL for VBfor individual stage Noise violation if considerthe impact of last stage soneed to Record VIH, VIL, VOH, VOL49

3/8/2013Simplified dynamic noise margin definitionComparison of dynamic noise margin valueModeling DNM for NAND50

3/8/2013Phase I: Worst-Case Noise Margin BasedVoltage transfercharacteristicUnity gain baseddefinitionMaximum squarebased definitionComparison of Basic DNA Tool withStatic Timing Analysis ToolsDNASTAPropagate NoiseUsing Superpositionor MaximizationPropagate Delay UsingMaximizationGateDynamic Noise MarginModeling of GatesGate Delay ModelingCriteriaDynamic Noise MarginDelay ConstraintsIN1OUTINkBaselineAlgorithmSimilar AlgorithmsConditional PropagationFalse Path Elimination51

3/8/2013DNA Organization and TasksDNM LibraryNoise LibraryNoise EvaluationEngineBasic Longest/Shortest Path AlgorithmInterconnectTemplatesSimple Algorithm ForConstraints OptimizationAs a PlusSimplified dynamic noise margin definitionComparison of dynamic noise margin valuesPercentage that the simplified method underestimates52

Improving Dynamic CMOS Circuit NoiseTolerance Using Resonant Tunneling DevicesGSRA: Li DingPresented by: Prof. Pinaki MazumderDepartment of Electrical Engineering and Computer ScienceUniversity of Michigan, Ann ArborDesign Automation and Test in Europe (DATE)Noise In Digital SystemsWhat is Noise? – Any deviation from expected state/valueCKCKABIleakCKCKCKAAABBBCKCKCKWhy Important? – Noise margin is continuously decreasingYear20012004200720102013Tech (um)1309065453222Density (M)38.677.2154.3171835327208VDD (V)20161.1-1.2 1.0-1.1 0.7-0.9 0.6-0.8 0.5-0.7 0.4-0.61

Three Central QuestionsHow much noise is generated?Will noise affect chip functionality?How to ensure chip functionality?Generate less noiseMake circuits more noise tolerantDynamic CMOS logic gates areemployed in High-speed CircuitsAchilles hill: Low Noise ImmunityExisting NT Design Techniques - IEmploying keeperPrecharging internal nodesRaising source voltageConstructing complementary p-networkAlways-on keeperKrambeck 82DC power consumptionFeedback keeperOklobdzija 85HS feedback keeperAnis 00Leakage noise OnlyConditional keeperAlvandpour 01Leakage noise Only2

Existing NT Design Techniques - IIEmploying keeperPrecharging internal nodesRaising source voltageConstructing complementary p-networkPrecharge all nodesLee 86Partial prechargePretorius 86Area overheadCharge sharing onlyCharge sharing onlyExisting NT Design Techniques - IIIEmploying keeperPrecharging internal nodesRaising source voltageConstructing complementary p-networkPMOS pull-upD’Souza 96DC power consumpNMOS pull-upSchorn 98DC power consumpMirror techniqueWang 99Area overheadDelay overheadTwin transistorBalamurugan 99Area overheadOnly for some logics3

Existing NT Design Techniques - IVEmploying keeperPrecharging internal nodesRaising source voltageConstructing complementary p-networkComp. P-networkMurabayashi 95Area overheadCMOS inverterCovino 97Gated CMOS inverterEvans 98Triple transistorBobba 99Area overheadArea overheadOnly for some logics Only for some logicsArea overheadDelay overheadMetrics for NT-Technique EvaluationNoise criterion – Improve tolerance against all noise typesFunctionality criterion – Suitable for all circuit functionsPower criterion – No DC power consumptionArea criterion – Limited circuit area overheadDelay criterion – Limited circuit delay overhead4

Comparison of Existing TechniquesNoise Func Power Area DelayAlways-on keeper6Feedback keeper1HS feedback keeper2Conditional fdbk keeper 2Precharge internal nodes 3Partial precharge2PMOS pull-up3NMOS pull-up (fdbk)3Mirror technique5Twin transistor3PassedallcriteriaComplementary p-networkCMOS inverter4Gated CMOS inverter4Triple transistor5The DilemmaIHigh noise tolerance large keeper strength ( W/L ratio)High performance small keeper strengthConflicting goals: Speed v. Area for noise optimizationDilemma : How to choose the size of the keeper?5

The IdeaKeeper strength for gate speedI sp 2VDDVDD / 2 0I (V ) dVKeeper strength for noise toleranceI nm max I (V ) 0 V VDWith PMOS KeeperSaferegionSaferegionPoor TradeoffWith NDR KeeperIspInmInmIspExcellentTradeoffSmart KeepersSmart Keeper: NDR keeper that aggressively explores difference betweenkeeper strengths for speed and for noise toleranceMaximum input noise voltageVmaxI P VDD VT VTI0Large IPGate delay VCVDD C I 0 C t d T t r ln WV22 I 0 I P I 0 I P I 0 DDSmall WDesign Goal of NDR: High Peak Current (IP), Low Valley Voltage (VV)6

Circuit Implementations - ISmart Keeper Design 1: SK1Two cross-coupled MOS transistorsDepletion mode transistors are neededCircuit Implementations - IISmart Keeper Design 2: SK2RTD provide folded-back I-V characteristicMOS devices completely shut down the keeper7

Time-independent effective massSchrodinger Equation 2 1 V ( r ) n ( r )2m E ( k ) En (0) n ( r )Fermi-DiracStatisticsE3 D EC 2 k x2 2 k 2Device Current Density:,2m2m where EC is the conduction J tot q W ( k ).k 1 k ( x ) Im k ( x ) km ( x ) x band energyk Transverse Momentum k x2 k y2J tot E2 D E0 2m where k02 2m ( E0 EC ) / 22 2 3 T ( E x ).EC E Ex 1 exp F kBT log E F E x qV A 1 e xp kBT 2 k 2Electrons having momentain the disk tunnel through,qm k B TE0 E1 E2 h (Phonon Recombination) 2 T (E ) E3 h (Phonon Emissio

Static noise analysis is pessimistic Worst-case analysis is pessimistic Full waveform evaluation is time consuming Proposed Framework DNA has three phases: 1. Worst-case noise margin based method 2. Multiple noise margins based approach 3. Complete dynamic noise evaluation To be developed under this project To be obtained from Third Party .