Design Of Low Power 6-bit Digitally-Controlled Oscillator (DCO) - Ijeei
International Journal on Electrical Engineering and Informatics - Volume 6, Number 2, June 2014Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)Mohammad Anisur Rahman, Habibah Binti Mohamed, Mamun Bin Ibne Reaz, Sawal HamidMd Ali, and Wan Mimi Diyana Wan ZakiDepartment of Electrical, Electronic and Systems EngineeringFaculty of Engineering and Built EnvironmentUniversiti Kebangsaan Malaysia, 43600 UKM, Bangi, Selangor, MALAYSIAAbstract: A low power 6-bit CMOS ring based digitally controlled oscillator (DCO)design is presented. The design is proposed based on binary-to-thermometer (BT)decoder current mirror digital-to-analog converter (DAC) and ring-based voltagecontrolled oscillator (VCO). The DCO is implemented using 0.18 µm CEDEC MentorGraphic CMOS process at 2.0 V supply voltage. The simulation results show that theproposed DCO consumed only 9.5764 mW of power besides the output voltage is1.8121 V and local oscillator clock frequency is 33 MHz. The phase noise parameter is 132 dBc/Hz with an offset frequency of 100 kHz has also been reported for theproposed circuits.Keyword: Ring Oscillator,Converter, Phase alog1. IntroductionRadios, mobile phones, televisions, computers, are just a few models that depend on PLLsfor right process that has been used widely in the communications world. A PLL is a controlsystem that produces an output signal [1] [3]. The phase is linked to the phase of an inputreference signal. There are comprised of a phase detector and a variable frequency oscillator.From the oscillator’s output, the PLLs measure the input signal’s phase with the phase of thesignal derived and regulate the oscillator’s frequency to hold the phases coordinated. Tocontrol the oscillator in a feedback mesh circuit, the phase detector’s signal has been used. Theother essential purpose of a PLL is to synchronize communications between chips [1]. Areference clock is directed along with the parallel data is interconnected. Since chip-to-chipcommunication most frequently happens at a lower rate than the on-chip clock rate, thereference clock is separated, but still synchronize with the system clock. However other chipthe reference clock is used to synchronize all the input flip-flop, which can present a significantclock load in the case of wide data buses [4]. Applying clock buffers to deal with this problemintroduces skew between the data and the sample clock. A PLL aligns, that is de-skews, theoutput of the clock buffer with the respect to the data. In addition, the PLL can multiply thefrequency of the incoming reference clock, allowing the core of the second chip to operate athigher frequency than the input reference clock [5].There are some types of PLLs that are, analog phase-locked loop (APLL), also known as alinear phase-locked loop (LPLL), software phase-locked loop (SPLL), all digital phase-lockedloop (ADPLL), and digital phase-locked loop (DPLL) [6] [8]. The upsurge of the operatingrange by adding more capacitance loading will effect in a lower maximum frequency andhigher power consumption. The reduction of the power consumption has developed a keyalarm in modern electronic systems since power consumption is of great fear for portablebattery-charger in the computing system.This paper proposed ring-based DCO, which is the combination of a (DAC) [9] anddifferential ring-based VCO [10, 11]. The current-steering converter is the leading formationfor extremely high speed DAC. The current-steering DAC has the benefits of being quite costefficient. Generally, a self-calibrated circuit can be designed to solve these problems [12] Received: November 3rd, 2013. Accepted: April 18th, 2014297
Mohammad Anisur Rahman, et al.[14] but the circuit will utilize more power and need a large chip area. The segmented currentsteering is the current method for designing digital-to-analog converters. It merges the benefitsof binary weighted and thermometer-coded designs. Successively, the circuit area is reducedwith the segmented DAC, as shown in Figure 1.Figure 1. Single ended DAC construction [9]Ring oscillators can be developed in any standard CMOS process and might need fewerchip area. The design is forthright and ring architectures can be used to offer multiple outputphases and wide tuning ranges. With the purpose of reducing the chip area, design of a CMOSdifferential ring oscillator has been performed notwithstanding its characteristic decreased thephase noise. Therefore, Ring-based VCO (RVCO) is normally familiar because of amoderately small area and toughness over process and temperature changes. The RVCO mustbe implemented by using differential as a substitute of single ended circuits as delay circuits.2. Construction of DCONormally oscillators are found in wireless communication devices and used in synthesizers,mixers and phase lock loops. Apart from a controllable frequency, the specifications for DCOare frequency range, tuning sensitivity, power consumption, output power, phase noise etc. Inthis paper, we present a DCO for fully digital PLL application capable of supplying localoscillator clocks at 33 MHz to 3 GHz with low phase noise as well as low power consumption.As mentioned earlier, the proposed DCO is consists of single ended current steering DAC andring-based VCO, as shown in figure 2. The DAC circuit contained BT decoders and currentmirror circuits. There are three current mirrors of different weighting in the current mirrorscircuit. Each current mirror regulated a 2-bit BT code decoder.DigitalcodeinputBTDecoderCurrentmirror andswitchi itThree stagesRing-basedVCOVout1Vout2RGNFigure 2. The proposed ring-based DCOThe DAC has gained the advantage of low chip area. It is been obliged low transistor countof this formation. Hence, this DAC has more probability to use low power. The constructioncircuit of one 2-bit BT decoder comprises of one AND gate and one OR gate in the transistorslevel. Figure 3 represents the circuit of one 2-bit current mirror circuit of DAC. The transistorsM2, M3 and M4, act as switches. These switches turned on the current route. The BT decoderstage generated the signals, S0, S1 and S2. When the switches were turned on, operativeresistance looks as if in the middle of the drain of M1 and GND.298
Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)(a)(b)Figure 3. TheT Current mirrormDAC circcuits (a) Schemmatic, (b) layouutThe Iunitrent of the unitt output of the 2-bit DAC whhen the inputs ofo the switchessu was the curris 1002. TheT I1 was verrified by the parallelpresistannce of the swittches (M2, M3 and M4). Theecurrent swwitch of the 6-bbit single-endeed DAC needs 9 NMOS transsistors acted ass switches. Theeswitches sets the current will be on or off.o Iout accumuulated the curreents from the currentcmirrors.PMOS traansistors M0 annd M1 were accted as a basic current mirrorr. The widths ofo the switchess(M2, M3, M4) transistoors were amennded to achievve an appropriiate current onn M1. Figure 4mDAC.describes a 2-bit BT deccoder current mirrorFigureF4. A 2-bbit BT decoder current mirrorr DACwof the PMOSPM0. Thee DAC neededdDifferrent current weere acquired byy altering the widththree diffeferent current sources that aree Iunit, 4Iunit andd 16Iunit. It is thhe purpose of smallersarea off299
Mohammad Anisur Rahman, et al.the DAC. The aspect raatio of M0/M1 werewattuned tot get the unit current Iunit, The aspect ratiooof M2/M4 and M10/M111 also attuned tot obtain the currentcunit forr each current mirror circuit,,which is 4I4 unit and 16Iuniit respectively. As for VCO, theretare massiive study has beenbperformeddto evaluatte and amend thet phase noisee of ring oscilllator [15] [18]. From thesee studies, it hassbeen testiified that the phasepnoise is reduced by thhe improved chhannel thermall noise and theedecreasedd output voltage swing. Thee Ring-based VCO circuit consists of thhree-stage ringgoscillator.ned for every CMOS, eitherr PMOS or NMMOS, is W/L 0.9/0.18. TheeThe circuit is designwis usingg multiple-passs loop, adds suupplementary feedfforward looops that workkmethod, whichin conjunction with the main loop. It is to decrease thhe delay of thee stages. Other configurationssare possibble to obtain a different frequuency increase or decrease evven though thee illustration offan oscillaator with an oddd number of stages,swith the feed forwardd loops passingg over a singleestage. Addjusting the strength of the laatch using the Vcontrol , from Vdac that is coonnected to theeswitches N11 and N133 regulates thee interval of thhe stage, and the VCO freqquency. Higherrveffectt in a strongger connectionn between N55 and N7. It creates moreecontrol voltagescomplicatted to switch thhe output voltaage, and therefoore reducing thhe frequency.3. Resultss and DiscussiionAs meentioned above, the proposeed ring-based DCODis a commbination of DACDand ring-based VCCO. The propoosed ring-basedd DCO circuit is designed foor low phase noisenand wideefrequencyy tuning range. These circuitts are implemeented using EDDA CEDEC MentorMGraphicc0.18 µm CMOSCprocesss. It is 6-bit rinng-based Digitaally Controlledd Oscillator wiith the value offsupply vooltage is 2.0 V.V The value off the load resisstor, RL, is 50 Ω, meanwhilee the transistorrcount is 757 MOS. For DAC,Dthe Vdacc is 69.810 mVV, meanwhile thet output volttages for VCOOare, Vout1 is 1.8121 V. TheT power disssipation is 9.57764 mW. The corecsize is esttimated aroundd6000 µm2 (130.02 µm X 46.21 µm).From the wave outpput, Figure 5 showssthe digiital input by usingufunction ‘Pattern’. Theenput, VIH, is 2 V meanwhile thet input voltagge for low inpuut, VIL, is -2 V.input volttage for high inThis DCOO has 6 inputs sincesit is 6-bitt DCO.Figure 5.5 The inputs foor 6-bit DCOFiguree 6 depicts thaat the output voltagevfor 6-bit BT decodeer current mirrror DAC. Theeoutput vooltage, Vdac, is 69.810 mV. ThisT output volttage will be thhe input voltage or Vcontrol forrthree-stagge ring oscillatoor.300
Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)Figure 6. The output vooltage for DACCw be the Vcoontrol to the threee-stage ring oscillatorofor VCO.VThe volttage output forrVdac willDCO is 1.81211V, sligghtly lower thaan the supply voltage (2 V), might be theere are currenttdissipatedd through the circuits.cIt disssipated 9. 395%%. In figure 7, the phase noiise point out attoffset freqquency 100KHHz is -132 dBc//Hz.Figure 7. PhasePnoise at offsetofrequency.301
Mohammad Anisur Rahman, et al.Furtheer down, it shoows Figure 8 (a)( the complette circuit for riing-based DCOO in schematiccand Figurre 8 (b) shows the layout of DCO. The sizze of DCO corre cell is approoximately 60000µm2 (1300.02 µm X 46.221 µm). The performance Coomparisons with earlier reported circuits innterms of powerpconsummption, phase noisenand frequuency range aree presented in Table 1. It hassbeen obseerved that the proposed circuuits show conssiderable poweer saving, a suufficient tuninggrange andd better phase noise.n(a)(b)Figure 8. The ring-based digitally conntrolled oscillattor circuit (a) schematic diagrram, (b) layouttTablle 1. The ring-bbased DCO performance Commparison.PowerOutputtPhasse Hz)(mW)63.40.333–1.4472–106 @1@ 5.36–114 @1@ MHzRRef.[21]98.79–9.17–105 @1@ MHzRRef.[22]9.57640.033–33-132@@100 KHzPreesent work302Technology(µm)0.350.180.180.180.18
Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)ConclusionThe structure of low power 6-bit ring-based DCO was proposed using a 0.18 µm CMOSprocess have been presented in this paper. This circuit is a combination of BT decoder, currentDAC and three-stage ring-based VCO. Simulation results indicate the new 6-bit DCO is able tooperate at low supply voltage of 2V and low power consumption is 9.5764 mW. The presentedresults demonstrate that the proposed design is feasible for various clock control systems forfull digital implementations. The performance, flexibility, and robustness make the 6-bit ringbased DCO feasible for high performance fully digital PLL application.References[1] Hwang, S. Lee, S. Lee, and S. Kim, “A digitally controlled phase-locked loop with fastlocking scheme for clock synthesis application”, Proceedings of the 47th Annual IEEEInternational Solid-State Circuits Conference (ISSCC ’00), pp. 168–169, February 2000.[2] D. W. Boerstler, “Low-jitter PLL clock generator for micro- processors with lock rangeof 340–612 MHz”, IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 513–519,1999.[3] Y. K. Teh, F. Mohd-Yasin, F. Choong, M. I. Reaz, and A. V. Kordesch, “Design andanalysis of UHF micropower CMOS DTMOST rectifiers”, IEEE Transactions onCircuits and Systems II: Express Briefs, vol. 56, pp. 122-126, 2009.[4] P. Larsson, “A 2–166MHz 1.2–2.5V CMOS clock-recovery PLL with feedback phaseselection and averaging phase- interpolation for jitter reduction”, Proceedings of IEEEInternational Solid-State Circuits Conference (ISSCC ’99), pp. 356–357, February 1999.[5] Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 110 MHz oflock range for microprocessors”, IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp.1599– 1607, 1992.[6] D.-K. Jeong, G. Borriello, D. Hodges, and R. H. Katz, “Design of PLL –based clockgeneration circuits”, IEEE Journal of Solid-State Circuits, vol. 22, no. 2, pp. 255-261,1987.[7] R. E. Best, “Phase-Locked Loops: Design, Simulation and Applications”, 6th ed.McGraw Hill, 2007.[8] L. F. Rahman, M. B. I. Reaz, M. A. Mohd. Ali and M. Kamada, “Design of an EEPROMin RFID tag: Employing mapped EPC and IPv6 address”, Proceedings IEEE Asia-PacificConference on Circuits and Systems pp. 168-171, December 2010.[9] S.-C. Yi, “An 8-bit current-steering digital to analog converter”, International Journal ofElectronics and Communications, vol. 66, pp. 433-437, 2012.[10] Y. A. Eken and J. Uyemura, “A 5.9-GHz voltage-controlled ring oscillator in 0.18-µmCMOS”, IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 230-233, 2004.[11] J. Jalil, M. B. I. Reaz, L. F. Rahman and Mohd Marufuzzaman, “Differential Ring BasedVoltage Controlled Oscillator for Readerless RFID Transponder”, 4th InternationalConference on Intelligent and Advanced Systems (ICIAS2012), pp. 807-810, 2012.[12] M. P. Tiilikainen, “A 14-bit 1.8-V 20mW1-mm2 CMOS DAC”, IEEE Journal of SolidState Circuits, vol. 36, pp. 1144-1147, 2001.[13] M. K. Khaw, F. Mohd-Yasin, and M. I. Reaz, “Recent advances in the integrated circuitdesign of RFID transponder”, Proceedings of IEEE International Conference onSemiconductor Electronics (ICSE 2004), pp. 326-330, 2004.[14] R. Bugeja and S. Bang-Sup, “A self trimming 14-b 100MS/s CMOS DAC”, IEEEJournal of Solid-State Circuits, vol. 35, pp. 1841-1852, 2000.[15] N. B. Romli, M. Mamun, M. A. S. Bhuiyan, and H. Husain, “Design of a Low PowerDissipation and Low Input Voltage Range Level Shifter in Cedec 0.18-µm CmosProcess”, World Applied Sciences Journal, vol. 19, pp. 1140-1148, 2012.[16] C.-H. Park and B. Kim, “A low-noise 900-MHz VCO in 0.6-μm CMOS”, IEEE Journalof Solid-State Circuits, vol. 34, no. 5, pp. 586–591, 1999.303
Mohammad Anisur Rahman, et al.[17] F. Mohd-Yasin,MM.M K. Khaw and M. B. I.I Reaz, “Raddio frequency identification::Evollution of transpponder circuit design”,dMicroowave Journal,, vol. 49, pp. 56-70, 2006.[18] J. Zhhao and Y.-B. Kim, “A low--power digitallyy controlled osscillator for alll digital phase-lockked loops”, Hinndawi Publishinng Corporation, vol. 2010, ppp.2, 2009.[19] Tommar, R. Pokhareel, O. Nizhnik,, H. Kanaya, annd K. Yoshidaa, “Design of 1.11 GHz highlyylineaar digitally-conntrolled ring oscillatorowithh wide tuning range,” IEEEE InternationallWorrkshop on Radiio-Frequency IntegrationITechnology, 20007. RFIT 007 pp.pp 82-85, 9-111December 2007.M. Chung andd C.-L. Wei, “An all-digital phase-lockked loop for digital powerr[20] Y.-Mmannagement integgrated chips,”. IEEEIInternattional Symposium on Circuitss and Systems,,pp. 2413-2416,224-27 May 2009.[21] R. Pokharel,PK. Ucchida, A. Tommar, H. Kanayaa, and K. Yoshiida, “Low phaase noise 10 bitt5 GHHz DCO usingg on-chip CPWW resonator in 0.18 µm CMOOS technologyy,” First AsiannHimmalayas Internaational Confereence on Interneet, pp. 1-4, 3-55 November, 20009.[22] R. B.B Staszewski,, C.-M. Hungg, N. Barton, M.-C.MLee, annd D. Leipoldd, “A digitallyyconttrolled oscillatoor in a 90 nm digitaldCMOS process for moobile phones,”” IEEE Journallof Soolid-State Circcuits, vol. 40, no. 11, pp. 22033-2211, 2005.ammad Anisuur Rahman wasw born in Raajshahi, Banglaadesh in 1989.MohaHe reeceived his B.SSc. degree in ElectricalEand Electronic Enggineering frommRajshhahi Universitty of Engineering & Technology, BangladeshBinn2011.Currently he is pursuing his Master Degreee by Researchh in the area offA based multi--standard baseeband processoor under the DepartmentDoffFPGAElectrrical, Electronnic and Systemms Engineeringg in Universitti KebangsaannMalayysia, Malaysiaa. His researcch interest iss in the fieldd of Wirelessscommmunication, Maathematical moodeling, VLSI design.dHabiibah Mohameed was born inn Malaysia, in 13 April 1981. She receiveddher B.Sc.Band M.Scc. degree in Eleectronics, both from Universiiti KebangsaannMalayysia (UKM), Malaysia,Min 20042and 20133, respectivelyy. Her researchhintereests are in the following fiellds: RF Analoog and Mixed Signal design,,Wirelless Communiccation, SoC deesign and fabriccation.mun Bin Ibne Reaz was boorn in Bangladdesh, in Decemmber 1963. HeeMamreceivved his B.Sc. and M.Sc. deegree in Appliied Physics annd Electronics,,both from Univerrsity of Rajhhashi, Bangladesh, in 19885 and 1986,,2from Ibaraaki University,,respeectively. He recceived his D.Enng. degree in 2007Japann. He is currenntly an Associaate Professor in the Universiiti KebangsaannMalayysia, Malaysia involving in teachingg, research andaindustriallconsuultation. He iss a regular asssociate of the Abdus Salamm InternationallCenteer for Theoretical Physics sinnce 2008. He hash vast researcch experiencessin Norwaay, Ireland andd Malaysia. Hee has publishedd extensively ini the area of ICI Design anddBiomediccal application IC. He is autthor and co-auuthor of more thant100 reseaarch articles inndesign auutomation and ICI design for biomedicalbappplications.304
Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)Sawaal Hamid Md Ali iss a Senior Lecturer iniUniversitiiKebanngsaan Malayssia. He compleeted his PhD inn 2009. His ressearch interestssare AnalogAMixedd Signal Desiggn, VLSI, Beehavioral Moddeling, SystemmOptimmizationMin 022Wan Mimi Diyanaa Wan Zaki joined Universitti Kebangsaan Malaysiampleted her PhhD from Multiimedia Univerrsity, Malaysia.June 2008. She comrinterests are in the fields medical imaging andd digital imageeHer researchprocessing. She is currentlyy a Senior Lecturer iniUniversitiingsaan Malayssia involved in teaching, research andaindustriallKebanconsuultation.305
Keyword: Ring Oscillator, Digitally-Controlled Oscillator, Digital-to-Analog Converter, Phase Noise. 1. Introduction Radios, mobile phones, televisions, computers, are just a few models that depend on PLLs for right process that has been used widely in the communications world. A PLL is a control system that produces an output signal [1] [3].
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ECE 451 -Jose Schutt‐Aine 8 Transistor Technologies Si Bipolar GaAs MESFET GaAs HBT InP HBT base resistance high - low low transit time high - low low Beta*Early voltage low - high high col-subst capacitance high - low low turn on voltage 0.8 - 1.4 0.3 thermal conductivity high - low medium transconductance 50X 1 50X 50X device matching 1 mV 10 mV 1 mV 1 mV
